1
// SPDX-License-Identifier: GPL-2.0-only
3
* rt5663.c -- RT5663 ALSA SoC audio codec driver
5
* Copyright 2016 Realtek Semiconductor Corp.
6
* Author: Jack Yu <jack.yu@realtek.com>
8
#include <linux/module.h>
9
#include <linux/moduleparam.h>
10
#include <linux/init.h>
11
#include <linux/delay.h>
13
#include <linux/i2c.h>
14
#include <linux/platform_device.h>
15
#include <linux/spi/spi.h>
16
#include <linux/acpi.h>
17
#include <linux/regulator/consumer.h>
18
#include <linux/workqueue.h>
19
#include <sound/core.h>
20
#include <sound/pcm.h>
21
#include <sound/pcm_params.h>
22
#include <sound/jack.h>
23
#include <sound/soc.h>
24
#include <sound/soc-dapm.h>
25
#include <sound/initval.h>
26
#include <sound/tlv.h>
31
#define RT5663_DEVICE_ID_2 0x6451
32
#define RT5663_DEVICE_ID_1 0x6406
34
#define RT5663_POWER_ON_DELAY_MS 300
35
#define RT5663_SUPPLY_CURRENT_UA 500000
42
struct impedance_mapping_table {
46
unsigned int dc_offset_l_manual;
47
unsigned int dc_offset_r_manual;
48
unsigned int dc_offset_l_manual_mic;
49
unsigned int dc_offset_r_manual_mic;
52
static const char *const rt5663_supply_names[] = {
58
struct snd_soc_component *component;
59
struct rt5663_platform_data pdata;
60
struct regmap *regmap;
61
struct delayed_work jack_detect_work, jd_unplug_work;
62
struct snd_soc_jack *hs_jack;
63
struct timer_list btn_check_timer;
64
struct impedance_mapping_table *imp_table;
65
struct regulator_bulk_data supplies[ARRAY_SIZE(rt5663_supply_names)];
79
static const struct reg_sequence rt5663_patch_list[] = {
87
static const struct reg_default rt5663_v2_reg[] = {
489
static const struct reg_default rt5663_reg[] = {
747
static bool rt5663_volatile_register(struct device *dev, unsigned int reg)
751
case RT5663_SIL_DET_CTL:
752
case RT5663_HP_IMP_GAIN_2:
753
case RT5663_AD_DA_MIXER:
754
case RT5663_FRAC_DIV_2:
755
case RT5663_MICBIAS_1:
756
case RT5663_ASRC_11_2:
757
case RT5663_ADC_EQ_1:
758
case RT5663_INT_ST_1:
759
case RT5663_INT_ST_2:
760
case RT5663_GPIO_STA1:
761
case RT5663_SIN_GEN_1:
762
case RT5663_IL_CMD_1:
763
case RT5663_IL_CMD_5:
764
case RT5663_IL_CMD_PWRSAV1:
765
case RT5663_EM_JACK_TYPE_1:
766
case RT5663_EM_JACK_TYPE_2:
767
case RT5663_EM_JACK_TYPE_3:
768
case RT5663_JD_CTRL2:
769
case RT5663_VENDOR_ID:
770
case RT5663_VENDOR_ID_1:
771
case RT5663_VENDOR_ID_2:
772
case RT5663_PLL_INT_REG:
773
case RT5663_SOFT_RAMP:
774
case RT5663_STO_DRE_1:
775
case RT5663_STO_DRE_5:
776
case RT5663_STO_DRE_6:
777
case RT5663_STO_DRE_7:
778
case RT5663_MIC_DECRO_1:
779
case RT5663_MIC_DECRO_4:
780
case RT5663_HP_IMP_SEN_1:
781
case RT5663_HP_IMP_SEN_3:
782
case RT5663_HP_IMP_SEN_4:
783
case RT5663_HP_IMP_SEN_5:
784
case RT5663_HP_CALIB_1_1:
785
case RT5663_HP_CALIB_9:
786
case RT5663_HP_CALIB_ST1:
787
case RT5663_HP_CALIB_ST2:
788
case RT5663_HP_CALIB_ST3:
789
case RT5663_HP_CALIB_ST4:
790
case RT5663_HP_CALIB_ST5:
791
case RT5663_HP_CALIB_ST6:
792
case RT5663_HP_CALIB_ST7:
793
case RT5663_HP_CALIB_ST8:
794
case RT5663_HP_CALIB_ST9:
802
static bool rt5663_readable_register(struct device *dev, unsigned int reg)
806
case RT5663_HP_OUT_EN:
807
case RT5663_HP_LCH_DRE:
808
case RT5663_HP_RCH_DRE:
809
case RT5663_CALIB_BST:
811
case RT5663_SIL_DET_CTL:
812
case RT5663_PWR_SAV_SILDET:
813
case RT5663_SIDETONE_CTL:
814
case RT5663_STO1_DAC_DIG_VOL:
815
case RT5663_STO1_ADC_DIG_VOL:
816
case RT5663_STO1_BOOST:
817
case RT5663_HP_IMP_GAIN_1:
818
case RT5663_HP_IMP_GAIN_2:
819
case RT5663_STO1_ADC_MIXER:
820
case RT5663_AD_DA_MIXER:
821
case RT5663_STO_DAC_MIXER:
822
case RT5663_DIG_SIDE_MIXER:
823
case RT5663_BYPASS_STO_DAC:
824
case RT5663_CALIB_REC_MIX:
825
case RT5663_PWR_DIG_1:
826
case RT5663_PWR_DIG_2:
827
case RT5663_PWR_ANLG_1:
828
case RT5663_PWR_ANLG_2:
829
case RT5663_PWR_ANLG_3:
830
case RT5663_PWR_MIXER:
831
case RT5663_SIG_CLK_DET:
832
case RT5663_PRE_DIV_GATING_1:
833
case RT5663_PRE_DIV_GATING_2:
834
case RT5663_I2S1_SDP:
835
case RT5663_ADDA_CLK_1:
836
case RT5663_ADDA_RST:
837
case RT5663_FRAC_DIV_1:
838
case RT5663_FRAC_DIV_2:
850
case RT5663_DUMMY_REG:
857
case RT5663_HP_CHARGE_PUMP_1:
858
case RT5663_HP_CHARGE_PUMP_2:
859
case RT5663_MICBIAS_1:
861
case RT5663_ASRC_11_2:
862
case RT5663_DUMMY_REG_2:
863
case RT5663_REC_PATH_GAIN:
864
case RT5663_AUTO_1MRC_CLK:
865
case RT5663_ADC_EQ_1:
866
case RT5663_ADC_EQ_2:
872
case RT5663_INT_ST_1:
873
case RT5663_INT_ST_2:
876
case RT5663_GPIO_STA1:
877
case RT5663_SIN_GEN_1:
878
case RT5663_SIN_GEN_2:
879
case RT5663_SIN_GEN_3:
880
case RT5663_SOF_VOL_ZC1:
881
case RT5663_IL_CMD_1:
882
case RT5663_IL_CMD_2:
883
case RT5663_IL_CMD_3:
884
case RT5663_IL_CMD_4:
885
case RT5663_IL_CMD_5:
886
case RT5663_IL_CMD_6:
887
case RT5663_IL_CMD_7:
888
case RT5663_IL_CMD_8:
889
case RT5663_IL_CMD_PWRSAV1:
890
case RT5663_IL_CMD_PWRSAV2:
891
case RT5663_EM_JACK_TYPE_1:
892
case RT5663_EM_JACK_TYPE_2:
893
case RT5663_EM_JACK_TYPE_3:
894
case RT5663_EM_JACK_TYPE_4:
895
case RT5663_EM_JACK_TYPE_5:
896
case RT5663_EM_JACK_TYPE_6:
897
case RT5663_STO1_HPF_ADJ1:
898
case RT5663_STO1_HPF_ADJ2:
899
case RT5663_FAST_OFF_MICBIAS:
900
case RT5663_JD_CTRL1:
901
case RT5663_JD_CTRL2:
902
case RT5663_DIG_MISC:
903
case RT5663_VENDOR_ID:
904
case RT5663_VENDOR_ID_1:
905
case RT5663_VENDOR_ID_2:
906
case RT5663_DIG_VOL_ZCD:
907
case RT5663_ANA_BIAS_CUR_1:
908
case RT5663_ANA_BIAS_CUR_2:
909
case RT5663_ANA_BIAS_CUR_3:
910
case RT5663_ANA_BIAS_CUR_4:
911
case RT5663_ANA_BIAS_CUR_5:
912
case RT5663_ANA_BIAS_CUR_6:
913
case RT5663_BIAS_CUR_5:
914
case RT5663_BIAS_CUR_6:
915
case RT5663_BIAS_CUR_7:
916
case RT5663_BIAS_CUR_8:
917
case RT5663_DACREF_LDO:
918
case RT5663_DUMMY_REG_3:
919
case RT5663_BIAS_CUR_9:
920
case RT5663_DUMMY_REG_4:
921
case RT5663_VREFADJ_OP:
922
case RT5663_VREF_RECMIX:
923
case RT5663_CHARGE_PUMP_1:
924
case RT5663_CHARGE_PUMP_1_2:
925
case RT5663_CHARGE_PUMP_1_3:
926
case RT5663_CHARGE_PUMP_2:
927
case RT5663_DIG_IN_PIN1:
928
case RT5663_PAD_DRV_CTL:
929
case RT5663_PLL_INT_REG:
930
case RT5663_CHOP_DAC_L:
931
case RT5663_CHOP_ADC:
932
case RT5663_CALIB_ADC:
933
case RT5663_CHOP_DAC_R:
934
case RT5663_DUMMY_CTL_DACLR:
935
case RT5663_DUMMY_REG_5:
936
case RT5663_SOFT_RAMP:
937
case RT5663_TEST_MODE_1:
938
case RT5663_TEST_MODE_2:
939
case RT5663_TEST_MODE_3:
940
case RT5663_STO_DRE_1:
941
case RT5663_STO_DRE_2:
942
case RT5663_STO_DRE_3:
943
case RT5663_STO_DRE_4:
944
case RT5663_STO_DRE_5:
945
case RT5663_STO_DRE_6:
946
case RT5663_STO_DRE_7:
947
case RT5663_STO_DRE_8:
948
case RT5663_STO_DRE_9:
949
case RT5663_STO_DRE_10:
950
case RT5663_MIC_DECRO_1:
951
case RT5663_MIC_DECRO_2:
952
case RT5663_MIC_DECRO_3:
953
case RT5663_MIC_DECRO_4:
954
case RT5663_MIC_DECRO_5:
955
case RT5663_MIC_DECRO_6:
956
case RT5663_HP_DECRO_1:
957
case RT5663_HP_DECRO_2:
958
case RT5663_HP_DECRO_3:
959
case RT5663_HP_DECRO_4:
960
case RT5663_HP_DECOUP:
961
case RT5663_HP_IMP_SEN_MAP8:
962
case RT5663_HP_IMP_SEN_MAP9:
963
case RT5663_HP_IMP_SEN_MAP10:
964
case RT5663_HP_IMP_SEN_MAP11:
965
case RT5663_HP_IMP_SEN_1:
966
case RT5663_HP_IMP_SEN_2:
967
case RT5663_HP_IMP_SEN_3:
968
case RT5663_HP_IMP_SEN_4:
969
case RT5663_HP_IMP_SEN_5:
970
case RT5663_HP_IMP_SEN_6:
971
case RT5663_HP_IMP_SEN_7:
972
case RT5663_HP_IMP_SEN_8:
973
case RT5663_HP_IMP_SEN_9:
974
case RT5663_HP_IMP_SEN_10:
975
case RT5663_HP_IMP_SEN_11:
976
case RT5663_HP_IMP_SEN_12:
977
case RT5663_HP_IMP_SEN_13:
978
case RT5663_HP_IMP_SEN_14:
979
case RT5663_HP_IMP_SEN_15:
980
case RT5663_HP_IMP_SEN_16:
981
case RT5663_HP_IMP_SEN_17:
982
case RT5663_HP_IMP_SEN_18:
983
case RT5663_HP_IMP_SEN_19:
984
case RT5663_HP_IMPSEN_DIG5:
985
case RT5663_HP_IMPSEN_MAP1:
986
case RT5663_HP_IMPSEN_MAP2:
987
case RT5663_HP_IMPSEN_MAP3:
988
case RT5663_HP_IMPSEN_MAP4:
989
case RT5663_HP_IMPSEN_MAP5:
990
case RT5663_HP_IMPSEN_MAP7:
991
case RT5663_HP_LOGIC_1:
992
case RT5663_HP_LOGIC_2:
993
case RT5663_HP_CALIB_1:
994
case RT5663_HP_CALIB_1_1:
995
case RT5663_HP_CALIB_2:
996
case RT5663_HP_CALIB_3:
997
case RT5663_HP_CALIB_4:
998
case RT5663_HP_CALIB_5:
999
case RT5663_HP_CALIB_5_1:
1000
case RT5663_HP_CALIB_6:
1001
case RT5663_HP_CALIB_7:
1002
case RT5663_HP_CALIB_9:
1003
case RT5663_HP_CALIB_10:
1004
case RT5663_HP_CALIB_11:
1005
case RT5663_HP_CALIB_ST1:
1006
case RT5663_HP_CALIB_ST2:
1007
case RT5663_HP_CALIB_ST3:
1008
case RT5663_HP_CALIB_ST4:
1009
case RT5663_HP_CALIB_ST5:
1010
case RT5663_HP_CALIB_ST6:
1011
case RT5663_HP_CALIB_ST7:
1012
case RT5663_HP_CALIB_ST8:
1013
case RT5663_HP_CALIB_ST9:
1014
case RT5663_HP_AMP_DET:
1015
case RT5663_DUMMY_REG_6:
1016
case RT5663_HP_BIAS:
1020
case RT5663_DUMMY_1:
1021
case RT5663_DUMMY_2:
1022
case RT5663_DUMMY_3:
1024
case RT5663_ADC_LCH_LPF1_A1:
1025
case RT5663_ADC_RCH_LPF1_A1:
1026
case RT5663_ADC_LCH_LPF1_H0:
1027
case RT5663_ADC_RCH_LPF1_H0:
1028
case RT5663_ADC_LCH_BPF1_A1:
1029
case RT5663_ADC_RCH_BPF1_A1:
1030
case RT5663_ADC_LCH_BPF1_A2:
1031
case RT5663_ADC_RCH_BPF1_A2:
1032
case RT5663_ADC_LCH_BPF1_H0:
1033
case RT5663_ADC_RCH_BPF1_H0:
1034
case RT5663_ADC_LCH_BPF2_A1:
1035
case RT5663_ADC_RCH_BPF2_A1:
1036
case RT5663_ADC_LCH_BPF2_A2:
1037
case RT5663_ADC_RCH_BPF2_A2:
1038
case RT5663_ADC_LCH_BPF2_H0:
1039
case RT5663_ADC_RCH_BPF2_H0:
1040
case RT5663_ADC_LCH_BPF3_A1:
1041
case RT5663_ADC_RCH_BPF3_A1:
1042
case RT5663_ADC_LCH_BPF3_A2:
1043
case RT5663_ADC_RCH_BPF3_A2:
1044
case RT5663_ADC_LCH_BPF3_H0:
1045
case RT5663_ADC_RCH_BPF3_H0:
1046
case RT5663_ADC_LCH_BPF4_A1:
1047
case RT5663_ADC_RCH_BPF4_A1:
1048
case RT5663_ADC_LCH_BPF4_A2:
1049
case RT5663_ADC_RCH_BPF4_A2:
1050
case RT5663_ADC_LCH_BPF4_H0:
1051
case RT5663_ADC_RCH_BPF4_H0:
1052
case RT5663_ADC_LCH_HPF1_A1:
1053
case RT5663_ADC_RCH_HPF1_A1:
1054
case RT5663_ADC_LCH_HPF1_H0:
1055
case RT5663_ADC_RCH_HPF1_H0:
1056
case RT5663_ADC_EQ_PRE_VOL_L:
1057
case RT5663_ADC_EQ_PRE_VOL_R:
1058
case RT5663_ADC_EQ_POST_VOL_L:
1059
case RT5663_ADC_EQ_POST_VOL_R:
1066
static bool rt5663_v2_volatile_register(struct device *dev, unsigned int reg)
1070
case RT5663_CBJ_TYPE_2:
1071
case RT5663_PDM_OUT_CTL:
1072
case RT5663_PDM_I2C_DATA_CTL1:
1073
case RT5663_PDM_I2C_DATA_CTL4:
1074
case RT5663_ALC_BK_GAIN:
1076
case RT5663_MICBIAS_1:
1077
case RT5663_ADC_EQ_1:
1078
case RT5663_INT_ST_1:
1079
case RT5663_GPIO_STA2:
1080
case RT5663_IL_CMD_1:
1081
case RT5663_IL_CMD_5:
1082
case RT5663_A_JD_CTRL:
1083
case RT5663_JD_CTRL2:
1084
case RT5663_VENDOR_ID:
1085
case RT5663_VENDOR_ID_1:
1086
case RT5663_VENDOR_ID_2:
1087
case RT5663_STO_DRE_1:
1088
case RT5663_STO_DRE_5:
1089
case RT5663_STO_DRE_6:
1090
case RT5663_STO_DRE_7:
1091
case RT5663_MONO_DYNA_6:
1092
case RT5663_STO1_SIL_DET:
1093
case RT5663_MONOL_SIL_DET:
1094
case RT5663_MONOR_SIL_DET:
1095
case RT5663_STO2_DAC_SIL:
1096
case RT5663_MONO_AMP_CAL_ST1:
1097
case RT5663_MONO_AMP_CAL_ST2:
1098
case RT5663_MONO_AMP_CAL_ST3:
1099
case RT5663_MONO_AMP_CAL_ST4:
1100
case RT5663_HP_IMP_SEN_2:
1101
case RT5663_HP_IMP_SEN_3:
1102
case RT5663_HP_IMP_SEN_4:
1103
case RT5663_HP_IMP_SEN_10:
1104
case RT5663_HP_CALIB_1:
1105
case RT5663_HP_CALIB_10:
1106
case RT5663_HP_CALIB_ST1:
1107
case RT5663_HP_CALIB_ST4:
1108
case RT5663_HP_CALIB_ST5:
1109
case RT5663_HP_CALIB_ST6:
1110
case RT5663_HP_CALIB_ST7:
1111
case RT5663_HP_CALIB_ST8:
1112
case RT5663_HP_CALIB_ST9:
1113
case RT5663_HP_CALIB_ST10:
1114
case RT5663_HP_CALIB_ST11:
1121
static bool rt5663_v2_readable_register(struct device *dev, unsigned int reg)
1124
case RT5663_LOUT_CTRL:
1125
case RT5663_HP_AMP_2:
1126
case RT5663_MONO_OUT:
1127
case RT5663_MONO_GAIN:
1128
case RT5663_AEC_BST:
1129
case RT5663_IN1_IN2:
1130
case RT5663_IN3_IN4:
1131
case RT5663_INL1_INR1:
1132
case RT5663_CBJ_TYPE_2:
1133
case RT5663_CBJ_TYPE_3:
1134
case RT5663_CBJ_TYPE_4:
1135
case RT5663_CBJ_TYPE_5:
1136
case RT5663_CBJ_TYPE_8:
1137
case RT5663_DAC3_DIG_VOL:
1138
case RT5663_DAC3_CTRL:
1139
case RT5663_MONO_ADC_DIG_VOL:
1140
case RT5663_STO2_ADC_DIG_VOL:
1141
case RT5663_MONO_ADC_BST_GAIN:
1142
case RT5663_STO2_ADC_BST_GAIN:
1143
case RT5663_SIDETONE_CTRL:
1144
case RT5663_MONO1_ADC_MIXER:
1145
case RT5663_STO2_ADC_MIXER:
1146
case RT5663_MONO_DAC_MIXER:
1147
case RT5663_DAC2_SRC_CTRL:
1148
case RT5663_IF_3_4_DATA_CTL:
1149
case RT5663_IF_5_DATA_CTL:
1150
case RT5663_PDM_OUT_CTL:
1151
case RT5663_PDM_I2C_DATA_CTL1:
1152
case RT5663_PDM_I2C_DATA_CTL2:
1153
case RT5663_PDM_I2C_DATA_CTL3:
1154
case RT5663_PDM_I2C_DATA_CTL4:
1155
case RT5663_RECMIX1_NEW:
1156
case RT5663_RECMIX1L_0:
1157
case RT5663_RECMIX1L:
1158
case RT5663_RECMIX1R_0:
1159
case RT5663_RECMIX1R:
1160
case RT5663_RECMIX2_NEW:
1161
case RT5663_RECMIX2_L_2:
1162
case RT5663_RECMIX2_R:
1163
case RT5663_RECMIX2_R_2:
1164
case RT5663_CALIB_REC_LR:
1165
case RT5663_ALC_BK_GAIN:
1166
case RT5663_MONOMIX_GAIN:
1167
case RT5663_MONOMIX_IN_GAIN:
1168
case RT5663_OUT_MIXL_GAIN:
1169
case RT5663_OUT_LMIX_IN_GAIN:
1170
case RT5663_OUT_RMIX_IN_GAIN:
1171
case RT5663_OUT_RMIX_IN_GAIN1:
1172
case RT5663_LOUT_MIXER_CTRL:
1173
case RT5663_PWR_VOL:
1174
case RT5663_ADCDAC_RST:
1175
case RT5663_I2S34_SDP:
1176
case RT5663_I2S5_SDP:
1184
case RT5663_PLL_TRK_13:
1185
case RT5663_I2S_M_CLK_CTL:
1186
case RT5663_FDIV_I2S34_M_CLK:
1187
case RT5663_FDIV_I2S34_M_CLK2:
1188
case RT5663_FDIV_I2S5_M_CLK:
1189
case RT5663_FDIV_I2S5_M_CLK2:
1190
case RT5663_V2_IRQ_4:
1193
case RT5663_GPIO_STA2:
1194
case RT5663_HP_AMP_DET1:
1195
case RT5663_HP_AMP_DET2:
1196
case RT5663_HP_AMP_DET3:
1197
case RT5663_MID_BD_HP_AMP:
1198
case RT5663_LOW_BD_HP_AMP:
1199
case RT5663_SOF_VOL_ZC2:
1200
case RT5663_ADC_STO2_ADJ1:
1201
case RT5663_ADC_STO2_ADJ2:
1202
case RT5663_A_JD_CTRL:
1203
case RT5663_JD1_TRES_CTRL:
1204
case RT5663_JD2_TRES_CTRL:
1205
case RT5663_V2_JD_CTRL2:
1206
case RT5663_DUM_REG_2:
1207
case RT5663_DUM_REG_3:
1208
case RT5663_VENDOR_ID:
1209
case RT5663_VENDOR_ID_1:
1210
case RT5663_VENDOR_ID_2:
1211
case RT5663_DACADC_DIG_VOL2:
1212
case RT5663_DIG_IN_PIN2:
1213
case RT5663_PAD_DRV_CTL1:
1214
case RT5663_SOF_RAM_DEPOP:
1215
case RT5663_VOL_TEST:
1216
case RT5663_TEST_MODE_4:
1217
case RT5663_TEST_MODE_5:
1218
case RT5663_STO_DRE_9:
1219
case RT5663_MONO_DYNA_1:
1220
case RT5663_MONO_DYNA_2:
1221
case RT5663_MONO_DYNA_3:
1222
case RT5663_MONO_DYNA_4:
1223
case RT5663_MONO_DYNA_5:
1224
case RT5663_MONO_DYNA_6:
1225
case RT5663_STO1_SIL_DET:
1226
case RT5663_MONOL_SIL_DET:
1227
case RT5663_MONOR_SIL_DET:
1228
case RT5663_STO2_DAC_SIL:
1229
case RT5663_PWR_SAV_CTL1:
1230
case RT5663_PWR_SAV_CTL2:
1231
case RT5663_PWR_SAV_CTL3:
1232
case RT5663_PWR_SAV_CTL4:
1233
case RT5663_PWR_SAV_CTL5:
1234
case RT5663_PWR_SAV_CTL6:
1235
case RT5663_MONO_AMP_CAL1:
1236
case RT5663_MONO_AMP_CAL2:
1237
case RT5663_MONO_AMP_CAL3:
1238
case RT5663_MONO_AMP_CAL4:
1239
case RT5663_MONO_AMP_CAL5:
1240
case RT5663_MONO_AMP_CAL6:
1241
case RT5663_MONO_AMP_CAL7:
1242
case RT5663_MONO_AMP_CAL_ST1:
1243
case RT5663_MONO_AMP_CAL_ST2:
1244
case RT5663_MONO_AMP_CAL_ST3:
1245
case RT5663_MONO_AMP_CAL_ST4:
1246
case RT5663_MONO_AMP_CAL_ST5:
1247
case RT5663_V2_HP_IMP_SEN_13:
1248
case RT5663_V2_HP_IMP_SEN_14:
1249
case RT5663_V2_HP_IMP_SEN_6:
1250
case RT5663_V2_HP_IMP_SEN_7:
1251
case RT5663_V2_HP_IMP_SEN_8:
1252
case RT5663_V2_HP_IMP_SEN_9:
1253
case RT5663_V2_HP_IMP_SEN_10:
1254
case RT5663_HP_LOGIC_3:
1255
case RT5663_HP_CALIB_ST10:
1256
case RT5663_HP_CALIB_ST11:
1257
case RT5663_PRO_REG_TBL_4:
1258
case RT5663_PRO_REG_TBL_5:
1259
case RT5663_PRO_REG_TBL_6:
1260
case RT5663_PRO_REG_TBL_7:
1261
case RT5663_PRO_REG_TBL_8:
1262
case RT5663_PRO_REG_TBL_9:
1263
case RT5663_SAR_ADC_INL_1:
1264
case RT5663_SAR_ADC_INL_2:
1265
case RT5663_SAR_ADC_INL_3:
1266
case RT5663_SAR_ADC_INL_4:
1267
case RT5663_SAR_ADC_INL_5:
1268
case RT5663_SAR_ADC_INL_6:
1269
case RT5663_SAR_ADC_INL_7:
1270
case RT5663_SAR_ADC_INL_8:
1271
case RT5663_SAR_ADC_INL_9:
1272
case RT5663_SAR_ADC_INL_10:
1273
case RT5663_SAR_ADC_INL_11:
1274
case RT5663_SAR_ADC_INL_12:
1275
case RT5663_DRC_CTRL_1:
1276
case RT5663_DRC1_CTRL_2:
1277
case RT5663_DRC1_CTRL_3:
1278
case RT5663_DRC1_CTRL_4:
1279
case RT5663_DRC1_CTRL_5:
1280
case RT5663_DRC1_CTRL_6:
1281
case RT5663_DRC1_HD_CTRL_1:
1282
case RT5663_DRC1_HD_CTRL_2:
1283
case RT5663_DRC1_PRI_REG_1:
1284
case RT5663_DRC1_PRI_REG_2:
1285
case RT5663_DRC1_PRI_REG_3:
1286
case RT5663_DRC1_PRI_REG_4:
1287
case RT5663_DRC1_PRI_REG_5:
1288
case RT5663_DRC1_PRI_REG_6:
1289
case RT5663_DRC1_PRI_REG_7:
1290
case RT5663_DRC1_PRI_REG_8:
1291
case RT5663_ALC_PGA_CTL_1:
1292
case RT5663_ALC_PGA_CTL_2:
1293
case RT5663_ALC_PGA_CTL_3:
1294
case RT5663_ALC_PGA_CTL_4:
1295
case RT5663_ALC_PGA_CTL_5:
1296
case RT5663_ALC_PGA_CTL_6:
1297
case RT5663_ALC_PGA_CTL_7:
1298
case RT5663_ALC_PGA_CTL_8:
1299
case RT5663_ALC_PGA_REG_1:
1300
case RT5663_ALC_PGA_REG_2:
1301
case RT5663_ALC_PGA_REG_3:
1302
case RT5663_ADC_EQ_RECOV_1:
1303
case RT5663_ADC_EQ_RECOV_2:
1304
case RT5663_ADC_EQ_RECOV_3:
1305
case RT5663_ADC_EQ_RECOV_4:
1306
case RT5663_ADC_EQ_RECOV_5:
1307
case RT5663_ADC_EQ_RECOV_6:
1308
case RT5663_ADC_EQ_RECOV_7:
1309
case RT5663_ADC_EQ_RECOV_8:
1310
case RT5663_ADC_EQ_RECOV_9:
1311
case RT5663_ADC_EQ_RECOV_10:
1312
case RT5663_ADC_EQ_RECOV_11:
1313
case RT5663_ADC_EQ_RECOV_12:
1314
case RT5663_ADC_EQ_RECOV_13:
1315
case RT5663_VID_HIDDEN:
1316
case RT5663_VID_CUSTOMER:
1317
case RT5663_SCAN_MODE:
1318
case RT5663_I2C_BYPA:
1321
case RT5663_DEPOP_3:
1322
case RT5663_ASRC_11_2:
1323
case RT5663_INT_ST_2:
1324
case RT5663_GPIO_STA1:
1325
case RT5663_SIN_GEN_1:
1326
case RT5663_SIN_GEN_2:
1327
case RT5663_SIN_GEN_3:
1328
case RT5663_IL_CMD_PWRSAV1:
1329
case RT5663_IL_CMD_PWRSAV2:
1330
case RT5663_EM_JACK_TYPE_1:
1331
case RT5663_EM_JACK_TYPE_2:
1332
case RT5663_EM_JACK_TYPE_3:
1333
case RT5663_EM_JACK_TYPE_4:
1334
case RT5663_FAST_OFF_MICBIAS:
1335
case RT5663_ANA_BIAS_CUR_1:
1336
case RT5663_ANA_BIAS_CUR_2:
1337
case RT5663_BIAS_CUR_9:
1338
case RT5663_DUMMY_REG_4:
1339
case RT5663_VREF_RECMIX:
1340
case RT5663_CHARGE_PUMP_1_2:
1341
case RT5663_CHARGE_PUMP_1_3:
1342
case RT5663_CHARGE_PUMP_2:
1343
case RT5663_CHOP_DAC_R:
1344
case RT5663_DUMMY_CTL_DACLR:
1345
case RT5663_DUMMY_REG_5:
1346
case RT5663_SOFT_RAMP:
1347
case RT5663_TEST_MODE_1:
1348
case RT5663_STO_DRE_10:
1349
case RT5663_MIC_DECRO_1:
1350
case RT5663_MIC_DECRO_2:
1351
case RT5663_MIC_DECRO_3:
1352
case RT5663_MIC_DECRO_4:
1353
case RT5663_MIC_DECRO_5:
1354
case RT5663_MIC_DECRO_6:
1355
case RT5663_HP_DECRO_1:
1356
case RT5663_HP_DECRO_2:
1357
case RT5663_HP_DECRO_3:
1358
case RT5663_HP_DECRO_4:
1359
case RT5663_HP_DECOUP:
1360
case RT5663_HP_IMPSEN_MAP4:
1361
case RT5663_HP_IMPSEN_MAP5:
1362
case RT5663_HP_IMPSEN_MAP7:
1363
case RT5663_HP_CALIB_1:
1369
return rt5663_readable_register(dev, reg);
1373
static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0);
1374
static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv, -2250, 150, 0);
1375
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
1376
static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1378
/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
1379
static const DECLARE_TLV_DB_RANGE(in_bst_tlv,
1380
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1381
1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
1382
2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
1383
3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
1384
6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
1385
7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
1386
8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
1389
/* Interface data select */
1390
static const char * const rt5663_if1_adc_data_select[] = {
1391
"L/R", "R/L", "L/L", "R/R"
1394
static SOC_ENUM_SINGLE_DECL(rt5663_if1_adc_enum, RT5663_TDM_2,
1395
RT5663_DATA_SWAP_ADCDAT1_SHIFT, rt5663_if1_adc_data_select);
1397
static void rt5663_enable_push_button_irq(struct snd_soc_component *component,
1400
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1403
snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1404
RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_EN);
1405
/* reset in-line command */
1406
snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1407
RT5663_RESET_4BTN_INL_MASK,
1408
RT5663_RESET_4BTN_INL_RESET);
1409
snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1410
RT5663_RESET_4BTN_INL_MASK,
1411
RT5663_RESET_4BTN_INL_NOR);
1412
switch (rt5663->codec_ver) {
1414
snd_soc_component_update_bits(component, RT5663_IRQ_3,
1415
RT5663_V2_EN_IRQ_INLINE_MASK,
1416
RT5663_V2_EN_IRQ_INLINE_NOR);
1419
snd_soc_component_update_bits(component, RT5663_IRQ_2,
1420
RT5663_EN_IRQ_INLINE_MASK,
1421
RT5663_EN_IRQ_INLINE_NOR);
1424
dev_err(component->dev, "Unknown CODEC Version\n");
1427
switch (rt5663->codec_ver) {
1429
snd_soc_component_update_bits(component, RT5663_IRQ_3,
1430
RT5663_V2_EN_IRQ_INLINE_MASK,
1431
RT5663_V2_EN_IRQ_INLINE_BYP);
1434
snd_soc_component_update_bits(component, RT5663_IRQ_2,
1435
RT5663_EN_IRQ_INLINE_MASK,
1436
RT5663_EN_IRQ_INLINE_BYP);
1439
dev_err(component->dev, "Unknown CODEC Version\n");
1441
snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1442
RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_DIS);
1443
/* reset in-line command */
1444
snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1445
RT5663_RESET_4BTN_INL_MASK,
1446
RT5663_RESET_4BTN_INL_RESET);
1447
snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1448
RT5663_RESET_4BTN_INL_MASK,
1449
RT5663_RESET_4BTN_INL_NOR);
1454
* rt5663_v2_jack_detect - Detect headset.
1455
* @component: SoC audio component device.
1456
* @jack_insert: Jack insert or not.
1458
* Detect whether is headset or not when jack inserted.
1460
* Returns detect status.
1463
static int rt5663_v2_jack_detect(struct snd_soc_component *component, int jack_insert)
1465
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1466
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1467
int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
1469
dev_dbg(component->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1471
snd_soc_component_write(component, RT5663_CBJ_TYPE_2, 0x8040);
1472
snd_soc_component_write(component, RT5663_CBJ_TYPE_3, 0x1484);
1474
snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1475
snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
1476
snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
1477
snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
1478
snd_soc_dapm_sync(dapm);
1479
snd_soc_component_update_bits(component, RT5663_RC_CLK,
1480
RT5663_DIG_1M_CLK_MASK, RT5663_DIG_1M_CLK_EN);
1481
snd_soc_component_update_bits(component, RT5663_RECMIX, 0x8, 0x8);
1484
msleep(sleep_time[i]);
1485
val = snd_soc_component_read32(component, RT5663_CBJ_TYPE_2) & 0x0003;
1486
if (val == 0x1 || val == 0x2 || val == 0x3)
1488
dev_dbg(component->dev, "%s: MX-0011 val=%x sleep %d\n",
1489
__func__, val, sleep_time[i]);
1492
dev_dbg(component->dev, "%s val = %d\n", __func__, val);
1496
rt5663->jack_type = SND_JACK_HEADSET;
1497
rt5663_enable_push_button_irq(component, true);
1500
snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1501
snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1502
snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1503
snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1504
snd_soc_dapm_sync(dapm);
1505
rt5663->jack_type = SND_JACK_HEADPHONE;
1509
snd_soc_component_update_bits(component, RT5663_RECMIX, 0x8, 0x0);
1511
if (rt5663->jack_type == SND_JACK_HEADSET) {
1512
rt5663_enable_push_button_irq(component, false);
1513
snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1514
snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1515
snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1516
snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1517
snd_soc_dapm_sync(dapm);
1519
rt5663->jack_type = 0;
1522
dev_dbg(component->dev, "jack_type = %d\n", rt5663->jack_type);
1523
return rt5663->jack_type;
1527
* rt5663_jack_detect - Detect headset.
1528
* @component: SoC audio component device.
1529
* @jack_insert: Jack insert or not.
1531
* Detect whether is headset or not when jack inserted.
1533
* Returns detect status.
1535
static int rt5663_jack_detect(struct snd_soc_component *component, int jack_insert)
1537
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1540
dev_dbg(component->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1543
snd_soc_component_update_bits(component, RT5663_DIG_MISC,
1544
RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
1545
snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
1546
RT5663_SI_HP_MASK | RT5663_OSW_HP_L_MASK |
1547
RT5663_OSW_HP_R_MASK, RT5663_SI_HP_EN |
1548
RT5663_OSW_HP_L_DIS | RT5663_OSW_HP_R_DIS);
1549
snd_soc_component_update_bits(component, RT5663_DUMMY_1,
1550
RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK |
1551
RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN |
1552
RT5663_HPA_CPL_BIAS_1 | RT5663_HPA_CPR_BIAS_1);
1553
snd_soc_component_update_bits(component, RT5663_CBJ_1,
1554
RT5663_INBUF_CBJ_BST1_MASK | RT5663_CBJ_SENSE_BST1_MASK,
1555
RT5663_INBUF_CBJ_BST1_ON | RT5663_CBJ_SENSE_BST1_L);
1556
snd_soc_component_update_bits(component, RT5663_IL_CMD_2,
1557
RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON);
1558
/* BST1 power on for JD */
1559
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
1560
RT5663_PWR_BST1_MASK, RT5663_PWR_BST1_ON);
1561
snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
1562
RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK |
1563
RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN |
1564
RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN);
1565
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1566
RT5663_PWR_MB_MASK | RT5663_LDO1_DVO_MASK |
1567
RT5663_AMP_HP_MASK, RT5663_PWR_MB |
1568
RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
1569
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1570
RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
1571
RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1572
RT5663_PWR_VREF1 | RT5663_PWR_VREF2);
1574
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1575
RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1576
RT5663_PWR_FV1 | RT5663_PWR_FV2);
1577
snd_soc_component_update_bits(component, RT5663_AUTO_1MRC_CLK,
1578
RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN);
1579
snd_soc_component_update_bits(component, RT5663_IRQ_1,
1580
RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
1581
snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
1582
RT5663_EM_JD_MASK, RT5663_EM_JD_RST);
1583
snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
1584
RT5663_EM_JD_MASK, RT5663_EM_JD_NOR);
1587
regmap_read(rt5663->regmap, RT5663_INT_ST_2, &val);
1589
usleep_range(10000, 10005);
1598
val = snd_soc_component_read32(component, RT5663_EM_JACK_TYPE_2) & 0x0003;
1599
dev_dbg(component->dev, "%s val = %d\n", __func__, val);
1601
snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
1602
RT5663_OSW_HP_L_MASK | RT5663_OSW_HP_R_MASK,
1603
RT5663_OSW_HP_L_EN | RT5663_OSW_HP_R_EN);
1608
rt5663->jack_type = SND_JACK_HEADSET;
1609
rt5663_enable_push_button_irq(component, true);
1611
if (rt5663->pdata.impedance_sensing_num)
1614
if (rt5663->pdata.dc_offset_l_manual_mic) {
1615
regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
1616
rt5663->pdata.dc_offset_l_manual_mic >>
1618
regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
1619
rt5663->pdata.dc_offset_l_manual_mic &
1623
if (rt5663->pdata.dc_offset_r_manual_mic) {
1624
regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
1625
rt5663->pdata.dc_offset_r_manual_mic >>
1627
regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
1628
rt5663->pdata.dc_offset_r_manual_mic &
1633
rt5663->jack_type = SND_JACK_HEADPHONE;
1634
snd_soc_component_update_bits(component,
1636
RT5663_PWR_MB_MASK | RT5663_PWR_VREF1_MASK |
1637
RT5663_PWR_VREF2_MASK, 0);
1638
if (rt5663->pdata.impedance_sensing_num)
1641
if (rt5663->pdata.dc_offset_l_manual) {
1642
regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
1643
rt5663->pdata.dc_offset_l_manual >> 16);
1644
regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
1645
rt5663->pdata.dc_offset_l_manual &
1649
if (rt5663->pdata.dc_offset_r_manual) {
1650
regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
1651
rt5663->pdata.dc_offset_r_manual >> 16);
1652
regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
1653
rt5663->pdata.dc_offset_r_manual &
1659
if (rt5663->jack_type == SND_JACK_HEADSET)
1660
rt5663_enable_push_button_irq(component, false);
1661
rt5663->jack_type = 0;
1662
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1663
RT5663_PWR_MB_MASK | RT5663_PWR_VREF1_MASK |
1664
RT5663_PWR_VREF2_MASK, 0);
1667
dev_dbg(component->dev, "jack_type = %d\n", rt5663->jack_type);
1668
return rt5663->jack_type;
1671
static int rt5663_impedance_sensing(struct snd_soc_component *component)
1673
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1674
unsigned int value, i, reg84, reg26, reg2fa, reg91, reg10, reg80;
1676
for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) {
1677
if (rt5663->imp_table[i].vol == 7)
1681
if (rt5663->jack_type == SND_JACK_HEADSET) {
1682
snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1683
rt5663->imp_table[i].dc_offset_l_manual_mic >> 16);
1684
snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1685
rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff);
1686
snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1687
rt5663->imp_table[i].dc_offset_r_manual_mic >> 16);
1688
snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1689
rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff);
1691
snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1692
rt5663->imp_table[i].dc_offset_l_manual >> 16);
1693
snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1694
rt5663->imp_table[i].dc_offset_l_manual & 0xffff);
1695
snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1696
rt5663->imp_table[i].dc_offset_r_manual >> 16);
1697
snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1698
rt5663->imp_table[i].dc_offset_r_manual & 0xffff);
1701
reg84 = snd_soc_component_read32(component, RT5663_ASRC_2);
1702
reg26 = snd_soc_component_read32(component, RT5663_STO1_ADC_MIXER);
1703
reg2fa = snd_soc_component_read32(component, RT5663_DUMMY_1);
1704
reg91 = snd_soc_component_read32(component, RT5663_HP_CHARGE_PUMP_1);
1705
reg10 = snd_soc_component_read32(component, RT5663_RECMIX);
1706
reg80 = snd_soc_component_read32(component, RT5663_GLB_CLK);
1708
snd_soc_component_update_bits(component, RT5663_STO_DRE_1, 0x8000, 0);
1709
snd_soc_component_write(component, RT5663_ASRC_2, 0);
1710
snd_soc_component_write(component, RT5663_STO1_ADC_MIXER, 0x4040);
1711
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1712
RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
1713
RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1714
RT5663_PWR_VREF1 | RT5663_PWR_VREF2);
1715
usleep_range(10000, 10005);
1716
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1717
RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1718
RT5663_PWR_FV1 | RT5663_PWR_FV2);
1719
snd_soc_component_update_bits(component, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
1720
RT5663_SCLK_SRC_RCCLK);
1721
snd_soc_component_update_bits(component, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK,
1722
RT5663_DIG_25M_CLK_EN);
1723
snd_soc_component_update_bits(component, RT5663_ADDA_CLK_1, RT5663_I2S_PD1_MASK, 0);
1724
snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0xff00);
1725
snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0xfffc);
1726
snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_1, 0x1232);
1727
snd_soc_component_write(component, RT5663_HP_LOGIC_2, 0x0005);
1728
snd_soc_component_write(component, RT5663_DEPOP_2, 0x3003);
1729
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0x0030);
1730
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0x0003);
1731
snd_soc_component_update_bits(component, RT5663_PWR_DIG_2,
1732
RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F,
1733
RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F);
1734
snd_soc_component_update_bits(component, RT5663_PWR_DIG_1,
1735
RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1736
RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 |
1738
RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1739
RT5663_PWR_LDO_DACREF_ON | RT5663_PWR_ADC_L1 |
1742
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
1743
RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2,
1744
RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2);
1746
snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_2, 0x1371);
1747
snd_soc_component_write(component, RT5663_STO_DAC_MIXER, 0);
1748
snd_soc_component_write(component, RT5663_BYPASS_STO_DAC, 0x000c);
1749
snd_soc_component_write(component, RT5663_HP_BIAS, 0xafaa);
1750
snd_soc_component_write(component, RT5663_CHARGE_PUMP_1, 0x2224);
1751
snd_soc_component_write(component, RT5663_HP_OUT_EN, 0x8088);
1752
snd_soc_component_write(component, RT5663_CHOP_ADC, 0x3000);
1753
snd_soc_component_write(component, RT5663_ADDA_RST, 0xc000);
1754
snd_soc_component_write(component, RT5663_STO1_HPF_ADJ1, 0x3320);
1755
snd_soc_component_write(component, RT5663_HP_CALIB_2, 0x00c9);
1756
snd_soc_component_write(component, RT5663_DUMMY_1, 0x004c);
1757
snd_soc_component_write(component, RT5663_ANA_BIAS_CUR_1, 0x7733);
1758
snd_soc_component_write(component, RT5663_CHARGE_PUMP_2, 0x7777);
1759
snd_soc_component_write(component, RT5663_STO_DRE_9, 0x0007);
1760
snd_soc_component_write(component, RT5663_STO_DRE_10, 0x0007);
1761
snd_soc_component_write(component, RT5663_DUMMY_2, 0x02a4);
1762
snd_soc_component_write(component, RT5663_RECMIX, 0x0005);
1763
snd_soc_component_write(component, RT5663_HP_IMP_SEN_1, 0x4334);
1764
snd_soc_component_update_bits(component, RT5663_IRQ_3, 0x0004, 0x0004);
1765
snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0x2200);
1766
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0x3000);
1767
snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0x6200);
1769
for (i = 0; i < 100; i++) {
1771
if (snd_soc_component_read32(component, RT5663_INT_ST_1) & 0x2)
1775
value = snd_soc_component_read32(component, RT5663_HP_IMP_SEN_4);
1777
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0);
1778
snd_soc_component_write(component, RT5663_INT_ST_1, 0);
1779
snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0);
1780
snd_soc_component_update_bits(component, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK,
1781
RT5663_DIG_25M_CLK_DIS);
1782
snd_soc_component_write(component, RT5663_GLB_CLK, reg80);
1783
snd_soc_component_write(component, RT5663_RECMIX, reg10);
1784
snd_soc_component_write(component, RT5663_DUMMY_2, 0x00a4);
1785
snd_soc_component_write(component, RT5663_DUMMY_1, reg2fa);
1786
snd_soc_component_write(component, RT5663_HP_CALIB_2, 0x00c8);
1787
snd_soc_component_write(component, RT5663_STO1_HPF_ADJ1, 0xb320);
1788
snd_soc_component_write(component, RT5663_ADDA_RST, 0xe400);
1789
snd_soc_component_write(component, RT5663_CHOP_ADC, 0x2000);
1790
snd_soc_component_write(component, RT5663_HP_OUT_EN, 0x0008);
1791
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
1792
RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2, 0);
1793
snd_soc_component_update_bits(component, RT5663_PWR_DIG_1,
1794
RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1795
RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 |
1796
RT5663_PWR_ADC_R1, 0);
1797
snd_soc_component_update_bits(component, RT5663_PWR_DIG_2,
1798
RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F, 0);
1799
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0);
1800
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0);
1801
snd_soc_component_write(component, RT5663_HP_LOGIC_2, 0);
1802
snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_1, reg91);
1803
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1804
RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK, 0);
1805
snd_soc_component_write(component, RT5663_STO1_ADC_MIXER, reg26);
1806
snd_soc_component_write(component, RT5663_ASRC_2, reg84);
1808
for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) {
1809
if (value >= rt5663->imp_table[i].imp_min &&
1810
value <= rt5663->imp_table[i].imp_max)
1814
snd_soc_component_update_bits(component, RT5663_STO_DRE_9, RT5663_DRE_GAIN_HP_MASK,
1815
rt5663->imp_table[i].vol);
1816
snd_soc_component_update_bits(component, RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_MASK,
1817
rt5663->imp_table[i].vol);
1819
if (rt5663->jack_type == SND_JACK_HEADSET) {
1820
snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1821
rt5663->imp_table[i].dc_offset_l_manual_mic >> 16);
1822
snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1823
rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff);
1824
snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1825
rt5663->imp_table[i].dc_offset_r_manual_mic >> 16);
1826
snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1827
rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff);
1829
snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1830
rt5663->imp_table[i].dc_offset_l_manual >> 16);
1831
snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1832
rt5663->imp_table[i].dc_offset_l_manual & 0xffff);
1833
snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1834
rt5663->imp_table[i].dc_offset_r_manual >> 16);
1835
snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1836
rt5663->imp_table[i].dc_offset_r_manual & 0xffff);
1842
static int rt5663_button_detect(struct snd_soc_component *component)
1846
val = snd_soc_component_read32(component, RT5663_IL_CMD_5);
1847
dev_dbg(component->dev, "%s: val=0x%x\n", __func__, val);
1848
btn_type = val & 0xfff0;
1849
snd_soc_component_write(component, RT5663_IL_CMD_5, val);
1854
static irqreturn_t rt5663_irq(int irq, void *data)
1856
struct rt5663_priv *rt5663 = data;
1858
dev_dbg(regmap_get_device(rt5663->regmap), "%s IRQ queue work\n",
1861
queue_delayed_work(system_wq, &rt5663->jack_detect_work,
1862
msecs_to_jiffies(250));
1867
static int rt5663_set_jack_detect(struct snd_soc_component *component,
1868
struct snd_soc_jack *hs_jack, void *data)
1870
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1872
rt5663->hs_jack = hs_jack;
1874
rt5663_irq(0, rt5663);
1879
static bool rt5663_check_jd_status(struct snd_soc_component *component)
1881
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1882
int val = snd_soc_component_read32(component, RT5663_INT_ST_1);
1884
dev_dbg(component->dev, "%s val=%x\n", __func__, val);
1887
switch (rt5663->codec_ver) {
1889
return !(val & 0x2000);
1891
return !(val & 0x1000);
1893
dev_err(component->dev, "Unknown CODEC Version\n");
1899
static void rt5663_jack_detect_work(struct work_struct *work)
1901
struct rt5663_priv *rt5663 =
1902
container_of(work, struct rt5663_priv, jack_detect_work.work);
1903
struct snd_soc_component *component = rt5663->component;
1904
int btn_type, report = 0;
1909
if (rt5663_check_jd_status(component)) {
1911
if (rt5663->jack_type == 0) {
1912
/* jack was out, report jack type */
1913
switch (rt5663->codec_ver) {
1915
report = rt5663_v2_jack_detect(
1916
rt5663->component, 1);
1919
report = rt5663_jack_detect(rt5663->component, 1);
1920
if (rt5663->pdata.impedance_sensing_num)
1921
rt5663_impedance_sensing(rt5663->component);
1924
dev_err(component->dev, "Unknown CODEC Version\n");
1927
/* Delay the jack insert report to avoid pop noise */
1930
/* jack is already in, report button event */
1931
report = SND_JACK_HEADSET;
1932
btn_type = rt5663_button_detect(rt5663->component);
1934
* rt5663 can report three kinds of button behavior,
1935
* one click, double click and hold. However,
1936
* currently we will report button pressed/released
1937
* event. So all the three button behaviors are
1938
* treated as button pressed.
1944
report |= SND_JACK_BTN_0;
1949
report |= SND_JACK_BTN_1;
1954
report |= SND_JACK_BTN_2;
1959
report |= SND_JACK_BTN_3;
1961
case 0x0000: /* unpressed */
1965
dev_err(rt5663->component->dev,
1966
"Unexpected button code 0x%04x\n",
1970
/* button release or spurious interrput*/
1971
if (btn_type == 0) {
1972
report = rt5663->jack_type;
1973
cancel_delayed_work_sync(
1974
&rt5663->jd_unplug_work);
1976
queue_delayed_work(system_wq,
1977
&rt5663->jd_unplug_work,
1978
msecs_to_jiffies(500));
1983
switch (rt5663->codec_ver) {
1985
report = rt5663_v2_jack_detect(rt5663->component, 0);
1988
report = rt5663_jack_detect(rt5663->component, 0);
1991
dev_err(component->dev, "Unknown CODEC Version\n");
1994
dev_dbg(component->dev, "%s jack report: 0x%04x\n", __func__, report);
1995
snd_soc_jack_report(rt5663->hs_jack, report, SND_JACK_HEADSET |
1996
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1997
SND_JACK_BTN_2 | SND_JACK_BTN_3);
2000
static void rt5663_jd_unplug_work(struct work_struct *work)
2002
struct rt5663_priv *rt5663 =
2003
container_of(work, struct rt5663_priv, jd_unplug_work.work);
2004
struct snd_soc_component *component = rt5663->component;
2009
if (!rt5663_check_jd_status(component)) {
2011
switch (rt5663->codec_ver) {
2013
rt5663_v2_jack_detect(rt5663->component, 0);
2016
rt5663_jack_detect(rt5663->component, 0);
2019
dev_err(component->dev, "Unknown CODEC Version\n");
2022
snd_soc_jack_report(rt5663->hs_jack, 0, SND_JACK_HEADSET |
2023
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
2024
SND_JACK_BTN_2 | SND_JACK_BTN_3);
2026
queue_delayed_work(system_wq, &rt5663->jd_unplug_work,
2027
msecs_to_jiffies(500));
2031
static const struct snd_kcontrol_new rt5663_snd_controls[] = {
2032
/* DAC Digital Volume */
2033
SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL,
2034
RT5663_DAC_L1_VOL_SHIFT + 1, RT5663_DAC_R1_VOL_SHIFT + 1,
2035
87, 0, dac_vol_tlv),
2036
/* ADC Digital Volume Control */
2037
SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL,
2038
RT5663_ADC_L_MUTE_SHIFT, RT5663_ADC_R_MUTE_SHIFT, 1, 1),
2039
SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL,
2040
RT5663_ADC_L_VOL_SHIFT + 1, RT5663_ADC_R_VOL_SHIFT + 1,
2041
63, 0, adc_vol_tlv),
2044
static const struct snd_kcontrol_new rt5663_v2_specific_controls[] = {
2045
/* Headphone Output Volume */
2046
SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE,
2047
RT5663_HP_RCH_DRE, RT5663_GAIN_HP_SHIFT, 15, 1,
2048
rt5663_v2_hp_vol_tlv),
2049
/* Mic Boost Volume */
2050
SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_AEC_BST,
2051
RT5663_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv),
2054
static const struct snd_kcontrol_new rt5663_specific_controls[] = {
2055
/* Mic Boost Volume*/
2056
SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_CBJ_2,
2057
RT5663_GAIN_BST1_SHIFT, 8, 0, in_bst_tlv),
2058
/* Data Swap for Slot0/1 in ADCDAT1 */
2059
SOC_ENUM("IF1 ADC Data Swap", rt5663_if1_adc_enum),
2062
static const struct snd_kcontrol_new rt5663_hpvol_controls[] = {
2063
/* Headphone Output Volume */
2064
SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_STO_DRE_9,
2065
RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_SHIFT, 23, 1,
2069
static int rt5663_is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
2070
struct snd_soc_dapm_widget *sink)
2073
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2075
val = snd_soc_component_read32(component, RT5663_GLB_CLK);
2076
val &= RT5663_SCLK_SRC_MASK;
2077
if (val == RT5663_SCLK_SRC_PLL1)
2083
static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w,
2084
struct snd_soc_dapm_widget *sink)
2086
unsigned int reg, shift, val;
2087
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2088
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2090
if (rt5663->codec_ver == CODEC_VER_1) {
2092
case RT5663_ADC_STO1_ASRC_SHIFT:
2093
reg = RT5663_ASRC_3;
2094
shift = RT5663_V2_AD_STO1_TRACK_SHIFT;
2096
case RT5663_DAC_STO1_ASRC_SHIFT:
2097
reg = RT5663_ASRC_2;
2098
shift = RT5663_DA_STO1_TRACK_SHIFT;
2105
case RT5663_ADC_STO1_ASRC_SHIFT:
2106
reg = RT5663_ASRC_2;
2107
shift = RT5663_AD_STO1_TRACK_SHIFT;
2109
case RT5663_DAC_STO1_ASRC_SHIFT:
2110
reg = RT5663_ASRC_2;
2111
shift = RT5663_DA_STO1_TRACK_SHIFT;
2118
val = (snd_soc_component_read32(component, reg) >> shift) & 0x7;
2126
static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
2127
struct snd_soc_dapm_widget *sink)
2129
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
2130
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2131
int da_asrc_en, ad_asrc_en;
2133
da_asrc_en = (snd_soc_component_read32(component, RT5663_ASRC_2) &
2134
RT5663_DA_STO1_TRACK_MASK) ? 1 : 0;
2135
switch (rt5663->codec_ver) {
2137
ad_asrc_en = (snd_soc_component_read32(component, RT5663_ASRC_3) &
2138
RT5663_V2_AD_STO1_TRACK_MASK) ? 1 : 0;
2141
ad_asrc_en = (snd_soc_component_read32(component, RT5663_ASRC_2) &
2142
RT5663_AD_STO1_TRACK_MASK) ? 1 : 0;
2145
dev_err(component->dev, "Unknown CODEC Version\n");
2149
if (da_asrc_en || ad_asrc_en)
2150
if (rt5663->sysclk > rt5663->lrck * 384)
2153
dev_err(component->dev, "sysclk < 384 x fs, disable i2s asrc\n");
2159
* rt5663_sel_asrc_clk_src - select ASRC clock source for a set of filters
2160
* @component: SoC audio component device.
2161
* @filter_mask: mask of filters.
2162
* @clk_src: clock source
2164
* The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5663 can
2165
* only support standard 32fs or 64fs i2s format, ASRC should be enabled to
2166
* support special i2s clock format such as Intel's 100fs(100 * sampling rate).
2167
* ASRC function will track i2s clock and generate a corresponding system clock
2168
* for codec. This function provides an API to select the clock source for a
2169
* set of filters specified by the mask. And the codec driver will turn on ASRC
2170
* for these filters if ASRC is selected as their clock source.
2172
int rt5663_sel_asrc_clk_src(struct snd_soc_component *component,
2173
unsigned int filter_mask, unsigned int clk_src)
2175
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2176
unsigned int asrc2_mask = 0;
2177
unsigned int asrc2_value = 0;
2178
unsigned int asrc3_mask = 0;
2179
unsigned int asrc3_value = 0;
2182
case RT5663_CLK_SEL_SYS:
2183
case RT5663_CLK_SEL_I2S1_ASRC:
2190
if (filter_mask & RT5663_DA_STEREO_FILTER) {
2191
asrc2_mask |= RT5663_DA_STO1_TRACK_MASK;
2192
asrc2_value |= clk_src << RT5663_DA_STO1_TRACK_SHIFT;
2195
if (filter_mask & RT5663_AD_STEREO_FILTER) {
2196
switch (rt5663->codec_ver) {
2198
asrc3_mask |= RT5663_V2_AD_STO1_TRACK_MASK;
2199
asrc3_value |= clk_src << RT5663_V2_AD_STO1_TRACK_SHIFT;
2202
asrc2_mask |= RT5663_AD_STO1_TRACK_MASK;
2203
asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT;
2206
dev_err(component->dev, "Unknown CODEC Version\n");
2211
snd_soc_component_update_bits(component, RT5663_ASRC_2, asrc2_mask,
2215
snd_soc_component_update_bits(component, RT5663_ASRC_3, asrc3_mask,
2220
EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src);
2223
static const struct snd_kcontrol_new rt5663_recmix1l[] = {
2224
SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1L,
2225
RT5663_RECMIX1L_BST2_SHIFT, 1, 1),
2226
SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5663_RECMIX1L,
2227
RT5663_RECMIX1L_BST1_CBJ_SHIFT, 1, 1),
2230
static const struct snd_kcontrol_new rt5663_recmix1r[] = {
2231
SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1R,
2232
RT5663_RECMIX1R_BST2_SHIFT, 1, 1),
2236
static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = {
2237
SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
2238
RT5663_M_STO1_ADC_L1_SHIFT, 1, 1),
2239
SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
2240
RT5663_M_STO1_ADC_L2_SHIFT, 1, 1),
2243
static const struct snd_kcontrol_new rt5663_sto1_adc_r_mix[] = {
2244
SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
2245
RT5663_M_STO1_ADC_R1_SHIFT, 1, 1),
2246
SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
2247
RT5663_M_STO1_ADC_R2_SHIFT, 1, 1),
2250
static const struct snd_kcontrol_new rt5663_adda_l_mix[] = {
2251
SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER,
2252
RT5663_M_ADCMIX_L_SHIFT, 1, 1),
2253
SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER,
2254
RT5663_M_DAC1_L_SHIFT, 1, 1),
2257
static const struct snd_kcontrol_new rt5663_adda_r_mix[] = {
2258
SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER,
2259
RT5663_M_ADCMIX_R_SHIFT, 1, 1),
2260
SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER,
2261
RT5663_M_DAC1_R_SHIFT, 1, 1),
2264
static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = {
2265
SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
2266
RT5663_M_DAC_L1_STO_L_SHIFT, 1, 1),
2269
static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = {
2270
SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
2271
RT5663_M_DAC_R1_STO_R_SHIFT, 1, 1),
2275
static const struct snd_kcontrol_new rt5663_hpo_switch =
2276
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5663_HP_AMP_2,
2277
RT5663_EN_DAC_HPO_SHIFT, 1, 0);
2279
/* Stereo ADC source */
2280
static const char * const rt5663_sto1_adc_src[] = {
2284
static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcl_enum, RT5663_STO1_ADC_MIXER,
2285
RT5663_STO1_ADC_L_SRC_SHIFT, rt5663_sto1_adc_src);
2287
static const struct snd_kcontrol_new rt5663_sto1_adcl_mux =
2288
SOC_DAPM_ENUM("STO1 ADC L Mux", rt5663_sto1_adcl_enum);
2290
static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcr_enum, RT5663_STO1_ADC_MIXER,
2291
RT5663_STO1_ADC_R_SRC_SHIFT, rt5663_sto1_adc_src);
2293
static const struct snd_kcontrol_new rt5663_sto1_adcr_mux =
2294
SOC_DAPM_ENUM("STO1 ADC R Mux", rt5663_sto1_adcr_enum);
2296
/* RT5663: Analog DACL1 input source */
2297
static const char * const rt5663_alg_dacl_src[] = {
2298
"DAC L", "STO DAC MIXL"
2301
static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacl_enum, RT5663_BYPASS_STO_DAC,
2302
RT5663_DACL1_SRC_SHIFT, rt5663_alg_dacl_src);
2304
static const struct snd_kcontrol_new rt5663_alg_dacl_mux =
2305
SOC_DAPM_ENUM("DAC L Mux", rt5663_alg_dacl_enum);
2307
/* RT5663: Analog DACR1 input source */
2308
static const char * const rt5663_alg_dacr_src[] = {
2309
"DAC R", "STO DAC MIXR"
2312
static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacr_enum, RT5663_BYPASS_STO_DAC,
2313
RT5663_DACR1_SRC_SHIFT, rt5663_alg_dacr_src);
2315
static const struct snd_kcontrol_new rt5663_alg_dacr_mux =
2316
SOC_DAPM_ENUM("DAC R Mux", rt5663_alg_dacr_enum);
2318
static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
2319
struct snd_kcontrol *kcontrol, int event)
2321
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2322
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2325
case SND_SOC_DAPM_POST_PMU:
2326
if (rt5663->codec_ver == CODEC_VER_1) {
2327
snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
2328
RT5663_SEL_PM_HP_SHIFT, RT5663_SEL_PM_HP_HIGH);
2329
snd_soc_component_update_bits(component, RT5663_HP_LOGIC_2,
2330
RT5663_HP_SIG_SRC1_MASK,
2331
RT5663_HP_SIG_SRC1_SILENCE);
2333
snd_soc_component_update_bits(component,
2334
RT5663_DACREF_LDO, 0x3e0e, 0x3a0a);
2335
snd_soc_component_write(component, RT5663_DEPOP_2, 0x3003);
2336
snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
2337
RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS);
2338
snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_2, 0x1371);
2339
snd_soc_component_write(component, RT5663_HP_BIAS, 0xabba);
2340
snd_soc_component_write(component, RT5663_CHARGE_PUMP_1, 0x2224);
2341
snd_soc_component_write(component, RT5663_ANA_BIAS_CUR_1, 0x7766);
2342
snd_soc_component_write(component, RT5663_HP_BIAS, 0xafaa);
2343
snd_soc_component_write(component, RT5663_CHARGE_PUMP_2, 0x7777);
2344
snd_soc_component_update_bits(component, RT5663_STO_DRE_1, 0x8000,
2346
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000,
2348
snd_soc_component_update_bits(component,
2349
RT5663_DIG_VOL_ZCD, 0x00c0, 0x0080);
2353
case SND_SOC_DAPM_PRE_PMD:
2354
if (rt5663->codec_ver == CODEC_VER_1) {
2355
snd_soc_component_update_bits(component, RT5663_HP_LOGIC_2,
2356
RT5663_HP_SIG_SRC1_MASK,
2357
RT5663_HP_SIG_SRC1_REG);
2359
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0x0);
2360
snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
2361
RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN);
2362
snd_soc_component_update_bits(component,
2363
RT5663_DACREF_LDO, 0x3e0e, 0);
2364
snd_soc_component_update_bits(component,
2365
RT5663_DIG_VOL_ZCD, 0x00c0, 0);
2376
static int rt5663_charge_pump_event(struct snd_soc_dapm_widget *w,
2377
struct snd_kcontrol *kcontrol, int event)
2379
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2380
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2383
case SND_SOC_DAPM_PRE_PMU:
2384
if (rt5663->codec_ver == CODEC_VER_0) {
2385
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030,
2387
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003,
2392
case SND_SOC_DAPM_POST_PMD:
2393
if (rt5663->codec_ver == CODEC_VER_0) {
2394
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0);
2395
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0);
2406
static int rt5663_bst2_power(struct snd_soc_dapm_widget *w,
2407
struct snd_kcontrol *kcontrol, int event)
2409
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2412
case SND_SOC_DAPM_POST_PMU:
2413
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
2414
RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK,
2415
RT5663_PWR_BST2 | RT5663_PWR_BST2_OP);
2418
case SND_SOC_DAPM_PRE_PMD:
2419
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
2420
RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 0);
2430
static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w,
2431
struct snd_kcontrol *kcontrol, int event)
2433
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2436
case SND_SOC_DAPM_POST_PMU:
2437
snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0xff00);
2438
snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0xfffc);
2441
case SND_SOC_DAPM_PRE_PMD:
2442
snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0x0000);
2443
snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0x0000);
2453
static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
2454
SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5663_PWR_PLL_SHIFT, 0,
2458
SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2,
2459
RT5663_PWR_MB1_SHIFT, 0),
2460
SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2,
2461
RT5663_PWR_MB2_SHIFT, 0),
2464
SND_SOC_DAPM_INPUT("IN1P"),
2465
SND_SOC_DAPM_INPUT("IN1N"),
2467
/* REC Mixer Power */
2468
SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2,
2469
RT5663_PWR_RECMIX1_SHIFT, 0, NULL, 0),
2472
SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2473
SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1,
2474
RT5663_PWR_ADC_L1_SHIFT, 0, NULL, 0),
2475
SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC,
2476
RT5663_CKGEN_ADCC_SHIFT, 0, NULL, 0),
2479
SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM,
2480
0, 0, rt5663_sto1_adc_l_mix,
2481
ARRAY_SIZE(rt5663_sto1_adc_l_mix)),
2483
/* ADC Filter Power */
2484
SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2,
2485
RT5663_PWR_ADC_S1F_SHIFT, 0, NULL, 0),
2487
/* Digital Interface */
2488
SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5663_PWR_I2S1_SHIFT, 0,
2490
SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2491
SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2492
SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2493
SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2494
SND_SOC_DAPM_PGA("IF ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2496
/* Audio Interface */
2497
SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
2498
SND_SOC_DAPM_AIF_OUT("AIFTX", "AIF Capture", 0, SND_SOC_NOPM, 0, 0),
2500
/* DAC mixer before sound effect */
2501
SND_SOC_DAPM_MIXER("ADDA MIXL", SND_SOC_NOPM, 0, 0, rt5663_adda_l_mix,
2502
ARRAY_SIZE(rt5663_adda_l_mix)),
2503
SND_SOC_DAPM_MIXER("ADDA MIXR", SND_SOC_NOPM, 0, 0, rt5663_adda_r_mix,
2504
ARRAY_SIZE(rt5663_adda_r_mix)),
2505
SND_SOC_DAPM_PGA("DAC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2506
SND_SOC_DAPM_PGA("DAC R1", SND_SOC_NOPM, 0, 0, NULL, 0),
2509
SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2,
2510
RT5663_PWR_DAC_S1F_SHIFT, 0, NULL, 0),
2511
SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0,
2512
rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)),
2513
SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0,
2514
rt5663_sto1_dac_r_mix, ARRAY_SIZE(rt5663_sto1_dac_r_mix)),
2517
SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1,
2518
RT5663_PWR_DAC_L1_SHIFT, 0, NULL, 0),
2519
SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1,
2520
RT5663_PWR_DAC_R1_SHIFT, 0, NULL, 0),
2521
SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0),
2522
SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0),
2525
SND_SOC_DAPM_SUPPLY("HP Charge Pump", SND_SOC_NOPM, 0, 0,
2526
rt5663_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
2527
SND_SOC_DAPM_POST_PMD),
2528
SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5663_hp_event,
2529
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2532
SND_SOC_DAPM_OUTPUT("HPOL"),
2533
SND_SOC_DAPM_OUTPUT("HPOR"),
2536
static const struct snd_soc_dapm_widget rt5663_v2_specific_dapm_widgets[] = {
2537
SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3,
2538
RT5663_PWR_LDO2_SHIFT, 0, NULL, 0),
2539
SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5663_PWR_VOL,
2540
RT5663_V2_PWR_MIC_DET_SHIFT, 0, NULL, 0),
2541
SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1,
2542
RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2545
SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2546
RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2547
SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2548
RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2549
SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2550
RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2553
SND_SOC_DAPM_INPUT("IN2P"),
2554
SND_SOC_DAPM_INPUT("IN2N"),
2557
SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
2558
SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3,
2559
RT5663_PWR_CBJ_SHIFT, 0, NULL, 0),
2560
SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0),
2561
SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0,
2562
rt5663_bst2_power, SND_SOC_DAPM_PRE_PMD |
2563
SND_SOC_DAPM_POST_PMU),
2566
SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5663_recmix1l,
2567
ARRAY_SIZE(rt5663_recmix1l)),
2568
SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5663_recmix1r,
2569
ARRAY_SIZE(rt5663_recmix1r)),
2570
SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2,
2571
RT5663_PWR_RECMIX2_SHIFT, 0, NULL, 0),
2574
SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2575
SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1,
2576
RT5663_PWR_ADC_R1_SHIFT, 0, NULL, 0),
2579
SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER,
2580
RT5663_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0),
2581
SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER,
2582
RT5663_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0),
2583
SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER,
2584
RT5663_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0),
2585
SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER,
2586
RT5663_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0),
2588
SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2589
&rt5663_sto1_adcl_mux),
2590
SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2591
&rt5663_sto1_adcr_mux),
2594
SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2595
rt5663_sto1_adc_r_mix, ARRAY_SIZE(rt5663_sto1_adc_r_mix)),
2597
/* Analog DAC Clock */
2598
SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L,
2599
RT5663_CKGEN_DAC1_SHIFT, 0, NULL, 0),
2602
SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
2603
&rt5663_hpo_switch),
2606
static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
2607
/* System Clock Pre Divider Gating */
2608
SND_SOC_DAPM_SUPPLY("Pre Div Power", SND_SOC_NOPM, 0, 0,
2609
rt5663_pre_div_power, SND_SOC_DAPM_POST_PMU |
2610
SND_SOC_DAPM_PRE_PMD),
2613
SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1,
2614
RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2617
SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2618
RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2619
SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2620
RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2621
SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2622
RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2625
SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM, 0, 0, NULL, 0),
2628
SND_SOC_DAPM_PGA("STO1 ADC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2629
SND_SOC_DAPM_PGA("STO1 ADC L2", SND_SOC_NOPM, 0, 0, NULL, 0),
2631
/* Analog DAC source */
2632
SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacl_mux),
2633
SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacr_mux),
2636
static const struct snd_soc_dapm_route rt5663_dapm_routes[] = {
2638
{ "I2S", NULL, "PLL", rt5663_is_sys_clk_from_pll },
2641
{ "STO1 ADC Filter", NULL, "ADC ASRC", rt5663_is_using_asrc },
2642
{ "STO1 DAC Filter", NULL, "DAC ASRC", rt5663_is_using_asrc },
2643
{ "I2S", NULL, "I2S ASRC", rt5663_i2s_use_asrc },
2645
{ "ADC L", NULL, "ADC L Power" },
2646
{ "ADC L", NULL, "ADC Clock" },
2648
{ "STO1 ADC L2", NULL, "STO1 DAC MIXL" },
2650
{ "STO1 ADC MIXL", "ADC1 Switch", "STO1 ADC L1" },
2651
{ "STO1 ADC MIXL", "ADC2 Switch", "STO1 ADC L2" },
2652
{ "STO1 ADC MIXL", NULL, "STO1 ADC Filter" },
2654
{ "IF1 ADC1", NULL, "STO1 ADC MIXL" },
2655
{ "IF ADC", NULL, "IF1 ADC1" },
2656
{ "AIFTX", NULL, "IF ADC" },
2657
{ "AIFTX", NULL, "I2S" },
2659
{ "AIFRX", NULL, "I2S" },
2660
{ "IF DAC", NULL, "AIFRX" },
2661
{ "IF1 DAC1 L", NULL, "IF DAC" },
2662
{ "IF1 DAC1 R", NULL, "IF DAC" },
2664
{ "ADDA MIXL", "ADC L Switch", "STO1 ADC MIXL" },
2665
{ "ADDA MIXL", "DAC L Switch", "IF1 DAC1 L" },
2666
{ "ADDA MIXL", NULL, "STO1 DAC Filter" },
2667
{ "ADDA MIXL", NULL, "STO1 DAC L Power" },
2668
{ "ADDA MIXR", "DAC R Switch", "IF1 DAC1 R" },
2669
{ "ADDA MIXR", NULL, "STO1 DAC Filter" },
2670
{ "ADDA MIXR", NULL, "STO1 DAC R Power" },
2672
{ "DAC L1", NULL, "ADDA MIXL" },
2673
{ "DAC R1", NULL, "ADDA MIXR" },
2675
{ "STO1 DAC MIXL", "DAC L Switch", "DAC L1" },
2676
{ "STO1 DAC MIXL", NULL, "STO1 DAC L Power" },
2677
{ "STO1 DAC MIXL", NULL, "STO1 DAC Filter" },
2678
{ "STO1 DAC MIXR", "DAC R Switch", "DAC R1" },
2679
{ "STO1 DAC MIXR", NULL, "STO1 DAC R Power" },
2680
{ "STO1 DAC MIXR", NULL, "STO1 DAC Filter" },
2682
{ "HP Amp", NULL, "HP Charge Pump" },
2683
{ "HP Amp", NULL, "DAC L" },
2684
{ "HP Amp", NULL, "DAC R" },
2687
static const struct snd_soc_dapm_route rt5663_v2_specific_dapm_routes[] = {
2688
{ "MICBIAS1", NULL, "LDO2" },
2689
{ "MICBIAS2", NULL, "LDO2" },
2691
{ "BST1 CBJ", NULL, "IN1P" },
2692
{ "BST1 CBJ", NULL, "IN1N" },
2693
{ "BST1 CBJ", NULL, "CBJ Power" },
2695
{ "BST2", NULL, "IN2P" },
2696
{ "BST2", NULL, "IN2N" },
2697
{ "BST2", NULL, "BST2 Power" },
2699
{ "RECMIX1L", "BST2 Switch", "BST2" },
2700
{ "RECMIX1L", "BST1 CBJ Switch", "BST1 CBJ" },
2701
{ "RECMIX1L", NULL, "RECMIX1L Power" },
2702
{ "RECMIX1R", "BST2 Switch", "BST2" },
2703
{ "RECMIX1R", NULL, "RECMIX1R Power" },
2705
{ "ADC L", NULL, "RECMIX1L" },
2706
{ "ADC R", NULL, "RECMIX1R" },
2707
{ "ADC R", NULL, "ADC R Power" },
2708
{ "ADC R", NULL, "ADC Clock" },
2710
{ "STO1 ADC L Mux", "ADC L", "ADC L" },
2711
{ "STO1 ADC L Mux", "ADC R", "ADC R" },
2712
{ "STO1 ADC L1", NULL, "STO1 ADC L Mux" },
2714
{ "STO1 ADC R Mux", "ADC L", "ADC L" },
2715
{ "STO1 ADC R Mux", "ADC R", "ADC R" },
2716
{ "STO1 ADC R1", NULL, "STO1 ADC R Mux" },
2717
{ "STO1 ADC R2", NULL, "STO1 DAC MIXR" },
2719
{ "STO1 ADC MIXR", "ADC1 Switch", "STO1 ADC R1" },
2720
{ "STO1 ADC MIXR", "ADC2 Switch", "STO1 ADC R2" },
2721
{ "STO1 ADC MIXR", NULL, "STO1 ADC Filter" },
2723
{ "IF1 ADC1", NULL, "STO1 ADC MIXR" },
2725
{ "ADDA MIXR", "ADC R Switch", "STO1 ADC MIXR" },
2727
{ "DAC L", NULL, "STO1 DAC MIXL" },
2728
{ "DAC L", NULL, "LDO DAC" },
2729
{ "DAC L", NULL, "DAC Clock" },
2730
{ "DAC R", NULL, "STO1 DAC MIXR" },
2731
{ "DAC R", NULL, "LDO DAC" },
2732
{ "DAC R", NULL, "DAC Clock" },
2734
{ "HPO Playback", "Switch", "HP Amp" },
2735
{ "HPOL", NULL, "HPO Playback" },
2736
{ "HPOR", NULL, "HPO Playback" },
2739
static const struct snd_soc_dapm_route rt5663_specific_dapm_routes[] = {
2740
{ "I2S", NULL, "Pre Div Power" },
2742
{ "BST1", NULL, "IN1P" },
2743
{ "BST1", NULL, "IN1N" },
2744
{ "BST1", NULL, "RECMIX1L Power" },
2746
{ "ADC L", NULL, "BST1" },
2748
{ "STO1 ADC L1", NULL, "ADC L" },
2750
{ "DAC L Mux", "DAC L", "DAC L1" },
2751
{ "DAC L Mux", "STO DAC MIXL", "STO1 DAC MIXL" },
2752
{ "DAC R Mux", "DAC R", "DAC R1"},
2753
{ "DAC R Mux", "STO DAC MIXR", "STO1 DAC MIXR" },
2755
{ "DAC L", NULL, "DAC L Mux" },
2756
{ "DAC R", NULL, "DAC R Mux" },
2758
{ "HPOL", NULL, "HP Amp" },
2759
{ "HPOR", NULL, "HP Amp" },
2762
static int rt5663_hw_params(struct snd_pcm_substream *substream,
2763
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2765
struct snd_soc_component *component = dai->component;
2766
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2767
unsigned int val_len = 0;
2770
rt5663->lrck = params_rate(params);
2772
dev_dbg(dai->dev, "bclk is %dHz and sysclk is %dHz\n",
2773
rt5663->lrck, rt5663->sysclk);
2775
pre_div = rl6231_get_clk_info(rt5663->sysclk, rt5663->lrck);
2777
dev_err(component->dev, "Unsupported clock setting %d for DAI %d\n",
2778
rt5663->lrck, dai->id);
2782
dev_dbg(dai->dev, "pre_div is %d for iis %d\n", pre_div, dai->id);
2784
switch (params_width(params)) {
2786
val_len = RT5663_I2S_DL_8;
2789
val_len = RT5663_I2S_DL_16;
2792
val_len = RT5663_I2S_DL_20;
2795
val_len = RT5663_I2S_DL_24;
2801
snd_soc_component_update_bits(component, RT5663_I2S1_SDP,
2802
RT5663_I2S_DL_MASK, val_len);
2804
snd_soc_component_update_bits(component, RT5663_ADDA_CLK_1,
2805
RT5663_I2S_PD1_MASK, pre_div << RT5663_I2S_PD1_SHIFT);
2810
static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2812
struct snd_soc_component *component = dai->component;
2813
unsigned int reg_val = 0;
2815
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2816
case SND_SOC_DAIFMT_CBM_CFM:
2818
case SND_SOC_DAIFMT_CBS_CFS:
2819
reg_val |= RT5663_I2S_MS_S;
2825
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2826
case SND_SOC_DAIFMT_NB_NF:
2828
case SND_SOC_DAIFMT_IB_NF:
2829
reg_val |= RT5663_I2S_BP_INV;
2835
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2836
case SND_SOC_DAIFMT_I2S:
2838
case SND_SOC_DAIFMT_LEFT_J:
2839
reg_val |= RT5663_I2S_DF_LEFT;
2841
case SND_SOC_DAIFMT_DSP_A:
2842
reg_val |= RT5663_I2S_DF_PCM_A;
2844
case SND_SOC_DAIFMT_DSP_B:
2845
reg_val |= RT5663_I2S_DF_PCM_B;
2851
snd_soc_component_update_bits(component, RT5663_I2S1_SDP, RT5663_I2S_MS_MASK |
2852
RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val);
2857
static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2858
unsigned int freq, int dir)
2860
struct snd_soc_component *component = dai->component;
2861
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2862
unsigned int reg_val = 0;
2864
if (freq == rt5663->sysclk && clk_id == rt5663->sysclk_src)
2868
case RT5663_SCLK_S_MCLK:
2869
reg_val |= RT5663_SCLK_SRC_MCLK;
2871
case RT5663_SCLK_S_PLL1:
2872
reg_val |= RT5663_SCLK_SRC_PLL1;
2874
case RT5663_SCLK_S_RCCLK:
2875
reg_val |= RT5663_SCLK_SRC_RCCLK;
2878
dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2881
snd_soc_component_update_bits(component, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
2883
rt5663->sysclk = freq;
2884
rt5663->sysclk_src = clk_id;
2886
dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2892
static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2893
unsigned int freq_in, unsigned int freq_out)
2895
struct snd_soc_component *component = dai->component;
2896
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2897
struct rl6231_pll_code pll_code;
2899
int mask, shift, val;
2901
if (source == rt5663->pll_src && freq_in == rt5663->pll_in &&
2902
freq_out == rt5663->pll_out)
2905
if (!freq_in || !freq_out) {
2906
dev_dbg(component->dev, "PLL disabled\n");
2909
rt5663->pll_out = 0;
2910
snd_soc_component_update_bits(component, RT5663_GLB_CLK,
2911
RT5663_SCLK_SRC_MASK, RT5663_SCLK_SRC_MCLK);
2915
switch (rt5663->codec_ver) {
2917
mask = RT5663_V2_PLL1_SRC_MASK;
2918
shift = RT5663_V2_PLL1_SRC_SHIFT;
2921
mask = RT5663_PLL1_SRC_MASK;
2922
shift = RT5663_PLL1_SRC_SHIFT;
2925
dev_err(component->dev, "Unknown CODEC Version\n");
2930
case RT5663_PLL1_S_MCLK:
2933
case RT5663_PLL1_S_BCLK1:
2937
dev_err(component->dev, "Unknown PLL source %d\n", source);
2940
snd_soc_component_update_bits(component, RT5663_GLB_CLK, mask, (val << shift));
2942
ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2944
dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
2948
dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", pll_code.m_bp,
2949
(pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code,
2952
snd_soc_component_write(component, RT5663_PLL_1,
2953
pll_code.n_code << RT5663_PLL_N_SHIFT | pll_code.k_code);
2954
snd_soc_component_write(component, RT5663_PLL_2,
2955
(pll_code.m_bp ? 0 : pll_code.m_code) << RT5663_PLL_M_SHIFT |
2956
pll_code.m_bp << RT5663_PLL_M_BP_SHIFT);
2958
rt5663->pll_in = freq_in;
2959
rt5663->pll_out = freq_out;
2960
rt5663->pll_src = source;
2965
static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2966
unsigned int rx_mask, int slots, int slot_width)
2968
struct snd_soc_component *component = dai->component;
2969
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2970
unsigned int val = 0, reg;
2972
if (rx_mask || tx_mask)
2973
val |= RT5663_TDM_MODE_TDM;
2977
val |= RT5663_TDM_IN_CH_4;
2978
val |= RT5663_TDM_OUT_CH_4;
2981
val |= RT5663_TDM_IN_CH_6;
2982
val |= RT5663_TDM_OUT_CH_6;
2985
val |= RT5663_TDM_IN_CH_8;
2986
val |= RT5663_TDM_OUT_CH_8;
2994
switch (slot_width) {
2996
val |= RT5663_TDM_IN_LEN_20;
2997
val |= RT5663_TDM_OUT_LEN_20;
3000
val |= RT5663_TDM_IN_LEN_24;
3001
val |= RT5663_TDM_OUT_LEN_24;
3004
val |= RT5663_TDM_IN_LEN_32;
3005
val |= RT5663_TDM_OUT_LEN_32;
3013
switch (rt5663->codec_ver) {
3021
dev_err(component->dev, "Unknown CODEC Version\n");
3025
snd_soc_component_update_bits(component, reg, RT5663_TDM_MODE_MASK |
3026
RT5663_TDM_IN_CH_MASK | RT5663_TDM_OUT_CH_MASK |
3027
RT5663_TDM_IN_LEN_MASK | RT5663_TDM_OUT_LEN_MASK, val);
3032
static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
3034
struct snd_soc_component *component = dai->component;
3035
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3038
dev_dbg(component->dev, "%s ratio = %d\n", __func__, ratio);
3040
if (rt5663->codec_ver == CODEC_VER_1)
3047
snd_soc_component_update_bits(component, reg,
3048
RT5663_TDM_LENGTN_MASK,
3049
RT5663_TDM_LENGTN_16);
3052
snd_soc_component_update_bits(component, reg,
3053
RT5663_TDM_LENGTN_MASK,
3054
RT5663_TDM_LENGTN_20);
3057
snd_soc_component_update_bits(component, reg,
3058
RT5663_TDM_LENGTN_MASK,
3059
RT5663_TDM_LENGTN_24);
3062
snd_soc_component_update_bits(component, reg,
3063
RT5663_TDM_LENGTN_MASK,
3064
RT5663_TDM_LENGTN_32);
3067
dev_err(component->dev, "Invalid ratio!\n");
3074
static int rt5663_set_bias_level(struct snd_soc_component *component,
3075
enum snd_soc_bias_level level)
3077
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3080
case SND_SOC_BIAS_ON:
3081
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
3082
RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
3083
RT5663_PWR_FV1 | RT5663_PWR_FV2);
3086
case SND_SOC_BIAS_PREPARE:
3087
if (rt5663->codec_ver == CODEC_VER_1) {
3088
snd_soc_component_update_bits(component, RT5663_DIG_MISC,
3089
RT5663_DIG_GATE_CTRL_MASK,
3090
RT5663_DIG_GATE_CTRL_EN);
3091
snd_soc_component_update_bits(component, RT5663_SIG_CLK_DET,
3092
RT5663_EN_ANA_CLK_DET_MASK |
3093
RT5663_PWR_CLK_DET_MASK,
3094
RT5663_EN_ANA_CLK_DET_AUTO |
3095
RT5663_PWR_CLK_DET_EN);
3099
case SND_SOC_BIAS_STANDBY:
3100
if (rt5663->codec_ver == CODEC_VER_1)
3101
snd_soc_component_update_bits(component, RT5663_DIG_MISC,
3102
RT5663_DIG_GATE_CTRL_MASK,
3103
RT5663_DIG_GATE_CTRL_DIS);
3104
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
3105
RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
3106
RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK |
3107
RT5663_PWR_MB_MASK, RT5663_PWR_VREF1 |
3108
RT5663_PWR_VREF2 | RT5663_PWR_MB);
3109
usleep_range(10000, 10005);
3110
if (rt5663->codec_ver == CODEC_VER_1) {
3111
snd_soc_component_update_bits(component, RT5663_SIG_CLK_DET,
3112
RT5663_EN_ANA_CLK_DET_MASK |
3113
RT5663_PWR_CLK_DET_MASK,
3114
RT5663_EN_ANA_CLK_DET_DIS |
3115
RT5663_PWR_CLK_DET_DIS);
3119
case SND_SOC_BIAS_OFF:
3120
if (rt5663->jack_type != SND_JACK_HEADSET)
3121
snd_soc_component_update_bits(component,
3123
RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
3124
RT5663_PWR_FV1 | RT5663_PWR_FV2 |
3125
RT5663_PWR_MB_MASK, 0);
3127
snd_soc_component_update_bits(component,
3129
RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
3130
RT5663_PWR_FV1 | RT5663_PWR_FV2);
3140
static int rt5663_probe(struct snd_soc_component *component)
3142
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3143
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3145
rt5663->component = component;
3147
switch (rt5663->codec_ver) {
3149
snd_soc_dapm_new_controls(dapm,
3150
rt5663_v2_specific_dapm_widgets,
3151
ARRAY_SIZE(rt5663_v2_specific_dapm_widgets));
3152
snd_soc_dapm_add_routes(dapm,
3153
rt5663_v2_specific_dapm_routes,
3154
ARRAY_SIZE(rt5663_v2_specific_dapm_routes));
3155
snd_soc_add_component_controls(component, rt5663_v2_specific_controls,
3156
ARRAY_SIZE(rt5663_v2_specific_controls));
3159
snd_soc_dapm_new_controls(dapm,
3160
rt5663_specific_dapm_widgets,
3161
ARRAY_SIZE(rt5663_specific_dapm_widgets));
3162
snd_soc_dapm_add_routes(dapm,
3163
rt5663_specific_dapm_routes,
3164
ARRAY_SIZE(rt5663_specific_dapm_routes));
3165
snd_soc_add_component_controls(component, rt5663_specific_controls,
3166
ARRAY_SIZE(rt5663_specific_controls));
3168
if (!rt5663->imp_table)
3169
snd_soc_add_component_controls(component, rt5663_hpvol_controls,
3170
ARRAY_SIZE(rt5663_hpvol_controls));
3177
static void rt5663_remove(struct snd_soc_component *component)
3179
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3181
regmap_write(rt5663->regmap, RT5663_RESET, 0);
3185
static int rt5663_suspend(struct snd_soc_component *component)
3187
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3189
regcache_cache_only(rt5663->regmap, true);
3190
regcache_mark_dirty(rt5663->regmap);
3195
static int rt5663_resume(struct snd_soc_component *component)
3197
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3199
regcache_cache_only(rt5663->regmap, false);
3200
regcache_sync(rt5663->regmap);
3202
rt5663_irq(0, rt5663);
3207
#define rt5663_suspend NULL
3208
#define rt5663_resume NULL
3211
#define RT5663_STEREO_RATES SNDRV_PCM_RATE_8000_192000
3212
#define RT5663_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3213
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3215
static const struct snd_soc_dai_ops rt5663_aif_dai_ops = {
3216
.hw_params = rt5663_hw_params,
3217
.set_fmt = rt5663_set_dai_fmt,
3218
.set_sysclk = rt5663_set_dai_sysclk,
3219
.set_pll = rt5663_set_dai_pll,
3220
.set_tdm_slot = rt5663_set_tdm_slot,
3221
.set_bclk_ratio = rt5663_set_bclk_ratio,
3224
static struct snd_soc_dai_driver rt5663_dai[] = {
3226
.name = "rt5663-aif",
3229
.stream_name = "AIF Playback",
3232
.rates = RT5663_STEREO_RATES,
3233
.formats = RT5663_FORMATS,
3236
.stream_name = "AIF Capture",
3239
.rates = RT5663_STEREO_RATES,
3240
.formats = RT5663_FORMATS,
3242
.ops = &rt5663_aif_dai_ops,
3246
static const struct snd_soc_component_driver soc_component_dev_rt5663 = {
3247
.probe = rt5663_probe,
3248
.remove = rt5663_remove,
3249
.suspend = rt5663_suspend,
3250
.resume = rt5663_resume,
3251
.set_bias_level = rt5663_set_bias_level,
3252
.controls = rt5663_snd_controls,
3253
.num_controls = ARRAY_SIZE(rt5663_snd_controls),
3254
.dapm_widgets = rt5663_dapm_widgets,
3255
.num_dapm_widgets = ARRAY_SIZE(rt5663_dapm_widgets),
3256
.dapm_routes = rt5663_dapm_routes,
3257
.num_dapm_routes = ARRAY_SIZE(rt5663_dapm_routes),
3258
.set_jack = rt5663_set_jack_detect,
3259
.use_pmdown_time = 1,
3261
.non_legacy_dai_naming = 1,
3264
static const struct regmap_config rt5663_v2_regmap = {
3267
.use_single_read = true,
3268
.use_single_write = true,
3269
.max_register = 0x07fa,
3270
.volatile_reg = rt5663_v2_volatile_register,
3271
.readable_reg = rt5663_v2_readable_register,
3272
.cache_type = REGCACHE_RBTREE,
3273
.reg_defaults = rt5663_v2_reg,
3274
.num_reg_defaults = ARRAY_SIZE(rt5663_v2_reg),
3277
static const struct regmap_config rt5663_regmap = {
3280
.use_single_read = true,
3281
.use_single_write = true,
3282
.max_register = 0x03f3,
3283
.volatile_reg = rt5663_volatile_register,
3284
.readable_reg = rt5663_readable_register,
3285
.cache_type = REGCACHE_RBTREE,
3286
.reg_defaults = rt5663_reg,
3287
.num_reg_defaults = ARRAY_SIZE(rt5663_reg),
3290
static const struct regmap_config temp_regmap = {
3294
.use_single_read = true,
3295
.use_single_write = true,
3296
.max_register = 0x03f3,
3297
.cache_type = REGCACHE_NONE,
3300
static const struct i2c_device_id rt5663_i2c_id[] = {
3304
MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id);
3306
#if defined(CONFIG_OF)
3307
static const struct of_device_id rt5663_of_match[] = {
3308
{ .compatible = "realtek,rt5663", },
3311
MODULE_DEVICE_TABLE(of, rt5663_of_match);
3315
static const struct acpi_device_id rt5663_acpi_match[] = {
3319
MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match);
3322
static void rt5663_v2_calibrate(struct rt5663_priv *rt5663)
3324
regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3325
regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0100);
3326
regmap_write(rt5663->regmap, RT5663_RECMIX, 0x4040);
3327
regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x0001);
3328
regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
3329
regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
3330
regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
3331
regmap_write(rt5663->regmap, RT5663_CHOP_DAC_L, 0x3030);
3332
regmap_write(rt5663->regmap, RT5663_CALIB_ADC, 0x3c05);
3333
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23e);
3335
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23e);
3336
regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x0321);
3337
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0xfc00);
3341
static void rt5663_calibrate(struct rt5663_priv *rt5663)
3345
regmap_write(rt5663->regmap, RT5663_RESET, 0x0000);
3347
regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_4, 0x00a1);
3348
regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
3349
regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
3350
regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
3351
regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3352
regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x000c);
3353
regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x0324);
3354
regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001);
3355
regmap_write(rt5663->regmap, RT5663_VREFADJ_OP, 0x0f28);
3356
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23b);
3358
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23b);
3359
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8000);
3360
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x0008);
3361
regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
3362
regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
3363
regmap_write(rt5663->regmap, RT5663_CBJ_1, 0x8c10);
3364
regmap_write(rt5663->regmap, RT5663_IL_CMD_2, 0x00c1);
3365
regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb880);
3366
regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4110);
3367
regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4118);
3371
regmap_read(rt5663->regmap, RT5663_INT_ST_2, &value);
3372
if (!(value & 0x80))
3373
usleep_range(10000, 10005);
3381
regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x0000);
3382
regmap_write(rt5663->regmap, RT5663_DEPOP_2, 0x3003);
3383
regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0038);
3384
regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
3385
regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400);
3386
regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8);
3387
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8003);
3388
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c);
3389
regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
3390
regmap_write(rt5663->regmap, RT5663_DUMMY_2, 0x8089);
3391
regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b);
3393
regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x0000);
3394
regmap_write(rt5663->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
3395
regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xafaa);
3396
regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
3397
regmap_write(rt5663->regmap, RT5663_HP_OUT_EN, 0x8088);
3398
regmap_write(rt5663->regmap, RT5663_STO_DRE_9, 0x0017);
3399
regmap_write(rt5663->regmap, RT5663_STO_DRE_10, 0x0017);
3400
regmap_write(rt5663->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
3401
regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000);
3402
regmap_write(rt5663->regmap, RT5663_RECMIX, 0x0005);
3403
regmap_write(rt5663->regmap, RT5663_ADDA_RST, 0xc000);
3404
regmap_write(rt5663->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
3405
regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x00c9);
3406
regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x004c);
3407
regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x1111);
3408
regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4402);
3409
regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x3311);
3410
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0x0069);
3411
regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06ce);
3412
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6800);
3413
regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x1100);
3414
regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0057);
3415
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe800);
3419
regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
3421
usleep_range(10000, 10005);
3430
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6200);
3431
regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0059);
3432
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe200);
3436
regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
3438
usleep_range(10000, 10005);
3447
regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb8e0);
3448
usleep_range(10000, 10005);
3449
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0x003b);
3450
usleep_range(10000, 10005);
3451
regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0000);
3452
usleep_range(10000, 10005);
3453
regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x000b);
3454
usleep_range(10000, 10005);
3455
regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0008);
3456
usleep_range(10000, 10005);
3457
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0000);
3458
usleep_range(10000, 10005);
3461
static int rt5663_parse_dp(struct rt5663_priv *rt5663, struct device *dev)
3465
device_property_read_u32(dev, "realtek,dc_offset_l_manual",
3466
&rt5663->pdata.dc_offset_l_manual);
3467
device_property_read_u32(dev, "realtek,dc_offset_r_manual",
3468
&rt5663->pdata.dc_offset_r_manual);
3469
device_property_read_u32(dev, "realtek,dc_offset_l_manual_mic",
3470
&rt5663->pdata.dc_offset_l_manual_mic);
3471
device_property_read_u32(dev, "realtek,dc_offset_r_manual_mic",
3472
&rt5663->pdata.dc_offset_r_manual_mic);
3473
device_property_read_u32(dev, "realtek,impedance_sensing_num",
3474
&rt5663->pdata.impedance_sensing_num);
3476
if (rt5663->pdata.impedance_sensing_num) {
3477
table_size = sizeof(struct impedance_mapping_table) *
3478
rt5663->pdata.impedance_sensing_num;
3479
rt5663->imp_table = devm_kzalloc(dev, table_size, GFP_KERNEL);
3480
device_property_read_u32_array(dev,
3481
"realtek,impedance_sensing_table",
3482
(u32 *)rt5663->imp_table, table_size);
3488
static int rt5663_i2c_probe(struct i2c_client *i2c,
3489
const struct i2c_device_id *id)
3491
struct rt5663_platform_data *pdata = dev_get_platdata(&i2c->dev);
3492
struct rt5663_priv *rt5663;
3495
struct regmap *regmap;
3497
rt5663 = devm_kzalloc(&i2c->dev, sizeof(struct rt5663_priv),
3503
i2c_set_clientdata(i2c, rt5663);
3506
rt5663->pdata = *pdata;
3508
rt5663_parse_dp(rt5663, &i2c->dev);
3510
for (i = 0; i < ARRAY_SIZE(rt5663->supplies); i++)
3511
rt5663->supplies[i].supply = rt5663_supply_names[i];
3513
ret = devm_regulator_bulk_get(&i2c->dev,
3514
ARRAY_SIZE(rt5663->supplies),
3517
dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3521
/* Set load for regulator. */
3522
for (i = 0; i < ARRAY_SIZE(rt5663->supplies); i++) {
3523
ret = regulator_set_load(rt5663->supplies[i].consumer,
3524
RT5663_SUPPLY_CURRENT_UA);
3527
"Failed to set regulator load on %s, ret: %d\n",
3528
rt5663->supplies[i].supply, ret);
3533
ret = regulator_bulk_enable(ARRAY_SIZE(rt5663->supplies),
3537
dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3540
msleep(RT5663_POWER_ON_DELAY_MS);
3542
regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
3543
if (IS_ERR(regmap)) {
3544
ret = PTR_ERR(regmap);
3545
dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
3550
ret = regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3551
if (ret || (val != RT5663_DEVICE_ID_2 && val != RT5663_DEVICE_ID_1)) {
3553
"Device with ID register %#x is not rt5663, retry one time.\n",
3556
regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3560
case RT5663_DEVICE_ID_2:
3561
rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_v2_regmap);
3562
rt5663->codec_ver = CODEC_VER_1;
3564
case RT5663_DEVICE_ID_1:
3565
rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap);
3566
rt5663->codec_ver = CODEC_VER_0;
3570
"Device with ID register %#x is not rt5663\n",
3576
if (IS_ERR(rt5663->regmap)) {
3577
ret = PTR_ERR(rt5663->regmap);
3578
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3583
/* reset and calibrate */
3584
regmap_write(rt5663->regmap, RT5663_RESET, 0);
3585
regcache_cache_bypass(rt5663->regmap, true);
3586
switch (rt5663->codec_ver) {
3588
rt5663_v2_calibrate(rt5663);
3591
rt5663_calibrate(rt5663);
3594
dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3596
regcache_cache_bypass(rt5663->regmap, false);
3597
regmap_write(rt5663->regmap, RT5663_RESET, 0);
3598
dev_dbg(&i2c->dev, "calibrate done\n");
3600
switch (rt5663->codec_ver) {
3604
ret = regmap_register_patch(rt5663->regmap, rt5663_patch_list,
3605
ARRAY_SIZE(rt5663_patch_list));
3608
"Failed to apply regmap patch: %d\n", ret);
3611
dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3615
regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GP1_PIN_MASK,
3616
RT5663_GP1_PIN_IRQ);
3617
/* 4btn inline command debounce */
3618
regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5,
3619
RT5663_4BTN_CLK_DEB_MASK, RT5663_4BTN_CLK_DEB_65MS);
3621
switch (rt5663->codec_ver) {
3623
regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3625
regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
3626
RT5663_IRQ_POW_SAV_MASK | RT5663_IRQ_POW_SAV_JD1_MASK,
3627
RT5663_IRQ_POW_SAV_EN | RT5663_IRQ_POW_SAV_JD1_EN);
3628
regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2,
3629
RT5663_PWR_JD1_MASK, RT5663_PWR_JD1);
3630
regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3631
RT5663_EN_CB_JD_MASK, RT5663_EN_CB_JD_EN);
3633
regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2,
3634
RT5663_HP_SIG_SRC1_MASK, RT5663_HP_SIG_SRC1_REG);
3635
regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3636
RT5663_VREF_BIAS_MASK | RT5663_CBJ_DET_MASK |
3637
RT5663_DET_TYPE_MASK, RT5663_VREF_BIAS_REG |
3638
RT5663_CBJ_DET_EN | RT5663_DET_TYPE_QFN);
3639
/* Set GPIO4 and GPIO8 as input for combo jack */
3640
regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
3641
RT5663_GP4_PIN_CONF_MASK, RT5663_GP4_PIN_CONF_INPUT);
3642
regmap_update_bits(rt5663->regmap, RT5663_GPIO_3,
3643
RT5663_GP8_PIN_CONF_MASK, RT5663_GP8_PIN_CONF_INPUT);
3644
regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1,
3645
RT5663_LDO1_DVO_MASK | RT5663_AMP_HP_MASK,
3646
RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
3649
regmap_update_bits(rt5663->regmap, RT5663_DIG_MISC,
3650
RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
3651
regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
3652
RT5663_IRQ_MANUAL_MASK, RT5663_IRQ_MANUAL_EN);
3653
regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3654
RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
3655
regmap_update_bits(rt5663->regmap, RT5663_GPIO_1,
3656
RT5663_GPIO1_TYPE_MASK, RT5663_GPIO1_TYPE_EN);
3657
regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3658
regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
3659
RT5663_GP1_PIN_CONF_MASK | RT5663_SEL_GPIO1_MASK,
3660
RT5663_GP1_PIN_CONF_OUTPUT | RT5663_SEL_GPIO1_EN);
3661
regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3662
RT5663_RECMIX1_BST1_MASK, RT5663_RECMIX1_BST1_ON);
3663
regmap_update_bits(rt5663->regmap, RT5663_TDM_2,
3664
RT5663_DATA_SWAP_ADCDAT1_MASK,
3665
RT5663_DATA_SWAP_ADCDAT1_LL);
3668
dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3671
INIT_DELAYED_WORK(&rt5663->jack_detect_work, rt5663_jack_detect_work);
3672
INIT_DELAYED_WORK(&rt5663->jd_unplug_work, rt5663_jd_unplug_work);
3675
ret = request_irq(i2c->irq, rt5663_irq,
3676
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3677
| IRQF_ONESHOT, "rt5663", rt5663);
3679
dev_err(&i2c->dev, "%s Failed to reguest IRQ: %d\n",
3685
ret = devm_snd_soc_register_component(&i2c->dev,
3686
&soc_component_dev_rt5663,
3687
rt5663_dai, ARRAY_SIZE(rt5663_dai));
3696
* Error after enabling regulators should goto err_enable
3697
* to disable regulators.
3701
free_irq(i2c->irq, rt5663);
3703
regulator_bulk_disable(ARRAY_SIZE(rt5663->supplies), rt5663->supplies);
3707
static int rt5663_i2c_remove(struct i2c_client *i2c)
3709
struct rt5663_priv *rt5663 = i2c_get_clientdata(i2c);
3712
free_irq(i2c->irq, rt5663);
3714
regulator_bulk_disable(ARRAY_SIZE(rt5663->supplies), rt5663->supplies);
3719
static void rt5663_i2c_shutdown(struct i2c_client *client)
3721
struct rt5663_priv *rt5663 = i2c_get_clientdata(client);
3723
regmap_write(rt5663->regmap, RT5663_RESET, 0);
3726
static struct i2c_driver rt5663_i2c_driver = {
3729
.acpi_match_table = ACPI_PTR(rt5663_acpi_match),
3730
.of_match_table = of_match_ptr(rt5663_of_match),
3732
.probe = rt5663_i2c_probe,
3733
.remove = rt5663_i2c_remove,
3734
.shutdown = rt5663_i2c_shutdown,
3735
.id_table = rt5663_i2c_id,
3737
module_i2c_driver(rt5663_i2c_driver);
3739
MODULE_DESCRIPTION("ASoC RT5663 driver");
3740
MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
3741
MODULE_LICENSE("GPL v2");