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* QEMU PowerMac CUDA device support
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* Copyright (c) 2004-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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#include "qemu-timer.h"
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/* XXX: implement all timer modes */
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//#define DEBUG_CUDA_PACKET
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/* Bits in B data register: all active low */
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#define TREQ 0x08 /* Transfer request (input) */
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#define TACK 0x10 /* Transfer acknowledge (output) */
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#define TIP 0x20 /* Transfer in progress (output) */
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#define SR_CTRL 0x1c /* Shift register control bits */
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#define SR_EXT 0x0c /* Shift on external clock */
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#define SR_OUT 0x10 /* Shift out if 1 */
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/* Bits in IFR and IER */
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#define IER_SET 0x80 /* set bits in IER */
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#define IER_CLR 0 /* clear bits in IER */
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#define SR_INT 0x04 /* Shift register full/empty */
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#define T1_INT 0x40 /* Timer 1 interrupt */
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#define T2_INT 0x20 /* Timer 2 interrupt */
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#define T1MODE 0xc0 /* Timer 1 mode */
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#define T1MODE_CONT 0x40 /* continuous interrupts */
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/* commands (1st byte) */
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#define ERROR_PACKET 2
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#define TIMER_PACKET 3
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#define POWER_PACKET 4
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#define MACIIC_PACKET 5
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/* CUDA commands (2nd byte) */
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#define CUDA_WARM_START 0x0
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#define CUDA_AUTOPOLL 0x1
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#define CUDA_GET_6805_ADDR 0x2
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#define CUDA_GET_TIME 0x3
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#define CUDA_GET_PRAM 0x7
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#define CUDA_SET_6805_ADDR 0x8
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#define CUDA_SET_TIME 0x9
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#define CUDA_POWERDOWN 0xa
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#define CUDA_POWERUP_TIME 0xb
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#define CUDA_SET_PRAM 0xc
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#define CUDA_MS_RESET 0xd
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#define CUDA_SEND_DFAC 0xe
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#define CUDA_BATTERY_SWAP_SENSE 0x10
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#define CUDA_RESET_SYSTEM 0x11
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#define CUDA_SET_IPL 0x12
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#define CUDA_FILE_SERVER_FLAG 0x13
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#define CUDA_SET_AUTO_RATE 0x14
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#define CUDA_GET_AUTO_RATE 0x16
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#define CUDA_SET_DEVICE_LIST 0x19
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#define CUDA_GET_DEVICE_LIST 0x1a
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#define CUDA_SET_ONE_SECOND_MODE 0x1b
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#define CUDA_SET_POWER_MESSAGES 0x21
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#define CUDA_GET_SET_IIC 0x22
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#define CUDA_WAKEUP 0x23
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#define CUDA_TIMER_TICKLE 0x24
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#define CUDA_COMBINED_FORMAT_IIC 0x25
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#define CUDA_TIMER_FREQ (4700000 / 6)
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#define CUDA_ADB_POLL_FREQ 50
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/* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
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#define RTC_OFFSET 2082844800
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typedef struct CUDATimer {
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uint16_t counter_value; /* counter value at load time */
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int64_t next_irq_time;
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typedef struct CUDAState {
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uint8_t b; /* B-side data */
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uint8_t a; /* A-side data */
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uint8_t dirb; /* B-side direction (1=output) */
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uint8_t dira; /* A-side direction (1=output) */
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uint8_t sr; /* Shift register */
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uint8_t acr; /* Auxiliary control register */
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uint8_t pcr; /* Peripheral control register */
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uint8_t ifr; /* Interrupt flag register */
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uint8_t ier; /* Interrupt enable register */
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uint8_t anh; /* A-side data, no handshake */
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uint8_t last_b; /* last value of B register */
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uint8_t last_acr; /* last value of B register */
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uint8_t data_in[128];
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uint8_t data_out[16];
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QEMUTimer *adb_poll_timer;
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static CUDAState cuda_state;
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static void cuda_update(CUDAState *s);
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static void cuda_receive_packet_from_host(CUDAState *s,
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const uint8_t *data, int len);
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static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
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int64_t current_time);
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static void cuda_update_irq(CUDAState *s)
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if (s->ifr & s->ier & (SR_INT | T1_INT)) {
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qemu_irq_raise(s->irq);
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qemu_irq_lower(s->irq);
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static unsigned int get_counter(CUDATimer *s)
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unsigned int counter;
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d = muldiv64(qemu_get_clock(vm_clock) - s->load_time,
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CUDA_TIMER_FREQ, ticks_per_sec);
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/* the timer goes down from latch to -1 (period of latch + 2) */
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if (d <= (s->counter_value + 1)) {
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counter = (s->counter_value - d) & 0xffff;
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counter = (d - (s->counter_value + 1)) % (s->latch + 2);
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counter = (s->latch - counter) & 0xffff;
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counter = (s->counter_value - d) & 0xffff;
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static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val)
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printf("cuda: T%d.counter=%d\n",
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1 + (ti->timer == NULL), val);
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ti->load_time = qemu_get_clock(vm_clock);
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ti->counter_value = val;
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cuda_timer_update(s, ti, ti->load_time);
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static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
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int64_t d, next_time;
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unsigned int counter;
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/* current counter value */
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d = muldiv64(current_time - s->load_time,
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CUDA_TIMER_FREQ, ticks_per_sec);
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/* the timer goes down from latch to -1 (period of latch + 2) */
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if (d <= (s->counter_value + 1)) {
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counter = (s->counter_value - d) & 0xffff;
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counter = (d - (s->counter_value + 1)) % (s->latch + 2);
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counter = (s->latch - counter) & 0xffff;
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/* Note: we consider the irq is raised on 0 */
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if (counter == 0xffff) {
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next_time = d + s->latch + 1;
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} else if (counter == 0) {
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next_time = d + s->latch + 2;
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next_time = d + counter;
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printf("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n",
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s->latch, d, next_time - d);
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next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) +
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if (next_time <= current_time)
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next_time = current_time + 1;
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static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
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int64_t current_time)
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if ((s->acr & T1MODE) != T1MODE_CONT) {
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qemu_del_timer(ti->timer);
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ti->next_irq_time = get_next_irq_time(ti, current_time);
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qemu_mod_timer(ti->timer, ti->next_irq_time);
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static void cuda_timer1(void *opaque)
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CUDAState *s = opaque;
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CUDATimer *ti = &s->timers[0];
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cuda_timer_update(s, ti, ti->next_irq_time);
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static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
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CUDAState *s = opaque;
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addr = (addr >> 9) & 0xf;
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val = get_counter(&s->timers[0]) & 0xff;
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val = get_counter(&s->timers[0]) >> 8;
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val = s->timers[0].latch & 0xff;
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/* XXX: check this */
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val = (s->timers[0].latch >> 8) & 0xff;
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val = get_counter(&s->timers[1]) & 0xff;
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val = get_counter(&s->timers[1]) >> 8;
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if (addr != 13 || val != 0)
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printf("cuda: read: reg=0x%x val=%02x\n", addr, val);
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static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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CUDAState *s = opaque;
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addr = (addr >> 9) & 0xf;
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printf("cuda: write: reg=0x%x val=%02x\n", addr, val);
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s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
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cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
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s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
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set_counter(s, &s->timers[0], s->timers[0].latch);
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s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
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cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
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s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
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cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
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s->timers[1].latch = val;
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set_counter(s, &s->timers[1], val);
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set_counter(s, &s->timers[1], (val << 8) | s->timers[1].latch);
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cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
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s->ier |= val & 0x7f;
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/* NOTE: TIP and TREQ are negated */
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static void cuda_update(CUDAState *s)
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int packet_received, len;
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/* transfer requested from host */
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if (s->acr & SR_OUT) {
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if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
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if (s->data_out_index < sizeof(s->data_out)) {
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printf("cuda: send: %02x\n", s->sr);
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s->data_out[s->data_out_index++] = s->sr;
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if (s->data_in_index < s->data_in_size) {
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if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
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s->sr = s->data_in[s->data_in_index++];
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printf("cuda: recv: %02x\n", s->sr);
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/* indicate end of transfer */
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if (s->data_in_index >= s->data_in_size) {
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s->b = (s->b | TREQ);
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/* no transfer requested: handle sync case */
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if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) {
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/* update TREQ state each time TACK change state */
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s->b = (s->b | TREQ);
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s->b = (s->b & ~TREQ);
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if (!(s->last_b & TIP)) {
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/* handle end of host to cuda transfer */
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packet_received = (s->data_out_index > 0);
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/* always an IRQ at the end of transfer */
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/* signal if there is data to read */
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if (s->data_in_index < s->data_in_size) {
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s->b = (s->b & ~TREQ);
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s->last_acr = s->acr;
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/* NOTE: cuda_receive_packet_from_host() can call cuda_update()
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if (packet_received) {
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len = s->data_out_index;
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s->data_out_index = 0;
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cuda_receive_packet_from_host(s, s->data_out, len);
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static void cuda_send_packet_to_host(CUDAState *s,
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const uint8_t *data, int len)
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#ifdef DEBUG_CUDA_PACKET
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printf("cuda_send_packet_to_host:\n");
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for(i = 0; i < len; i++)
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printf(" %02x", data[i]);
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memcpy(s->data_in, data, len);
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s->data_in_size = len;
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s->data_in_index = 0;
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static void cuda_adb_poll(void *opaque)
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CUDAState *s = opaque;
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uint8_t obuf[ADB_MAX_OUT_LEN + 2];
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olen = adb_poll(&adb_bus, obuf + 2);
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obuf[0] = ADB_PACKET;
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obuf[1] = 0x40; /* polled data */
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cuda_send_packet_to_host(s, obuf, olen + 2);
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qemu_mod_timer(s->adb_poll_timer,
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qemu_get_clock(vm_clock) +
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(ticks_per_sec / CUDA_ADB_POLL_FREQ));
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static void cuda_receive_packet(CUDAState *s,
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const uint8_t *data, int len)
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autopoll = (data[1] != 0);
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if (autopoll != s->autopoll) {
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s->autopoll = autopoll;
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qemu_mod_timer(s->adb_poll_timer,
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qemu_get_clock(vm_clock) +
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(ticks_per_sec / CUDA_ADB_POLL_FREQ));
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qemu_del_timer(s->adb_poll_timer);
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obuf[0] = CUDA_PACKET;
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cuda_send_packet_to_host(s, obuf, 2);
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/* XXX: add time support ? */
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ti = time(NULL) + RTC_OFFSET;
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obuf[0] = CUDA_PACKET;
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cuda_send_packet_to_host(s, obuf, 7);
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case CUDA_FILE_SERVER_FLAG:
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case CUDA_SET_DEVICE_LIST:
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case CUDA_SET_AUTO_RATE:
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case CUDA_SET_POWER_MESSAGES:
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obuf[0] = CUDA_PACKET;
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cuda_send_packet_to_host(s, obuf, 2);
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obuf[0] = CUDA_PACKET;
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cuda_send_packet_to_host(s, obuf, 2);
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qemu_system_shutdown_request();
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case CUDA_RESET_SYSTEM:
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obuf[0] = CUDA_PACKET;
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cuda_send_packet_to_host(s, obuf, 2);
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qemu_system_reset_request();
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static void cuda_receive_packet_from_host(CUDAState *s,
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const uint8_t *data, int len)
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#ifdef DEBUG_CUDA_PACKET
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printf("cuda_receive_packet_from_host:\n");
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for(i = 0; i < len; i++)
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printf(" %02x", data[i]);
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uint8_t obuf[ADB_MAX_OUT_LEN + 2];
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olen = adb_request(&adb_bus, obuf + 2, data + 1, len - 1);
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obuf[0] = ADB_PACKET;
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obuf[0] = ADB_PACKET;
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cuda_send_packet_to_host(s, obuf, olen + 2);
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cuda_receive_packet(s, data + 1, len - 1);
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static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
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static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
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static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
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static CPUWriteMemoryFunc *cuda_write[] = {
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static CPUReadMemoryFunc *cuda_read[] = {
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void cuda_init (int *cuda_mem_index, qemu_irq irq)
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CUDAState *s = &cuda_state;
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s->timers[0].index = 0;
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s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s);
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s->timers[0].latch = 0xffff;
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set_counter(s, &s->timers[0], 0xffff);
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s->timers[1].index = 1;
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s->timers[1].latch = 0;
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// s->ier = T1_INT | SR_INT;
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set_counter(s, &s->timers[1], 0xffff);
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s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);
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*cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
added
removed
hw/cuda.c
