2
* Intel XScale PXA255/270 processor support.
4
* Copyright (c) 2006 Openedhand Ltd.
5
* Written by Andrzej Zaborowski <balrog@zabor.org>
7
* This code is licenced under the GPL.
15
#include "qemu-timer.h"
16
#include "qemu-char.h"
19
target_phys_addr_t io_base;
22
{ 0x40100000, PXA2XX_PIC_FFUART },
23
{ 0x40200000, PXA2XX_PIC_BTUART },
24
{ 0x40700000, PXA2XX_PIC_STUART },
25
{ 0x41600000, PXA25X_PIC_HWUART },
27
}, pxa270_serial[] = {
28
{ 0x40100000, PXA2XX_PIC_FFUART },
29
{ 0x40200000, PXA2XX_PIC_BTUART },
30
{ 0x40700000, PXA2XX_PIC_STUART },
34
typedef struct PXASSPDef {
35
target_phys_addr_t io_base;
40
static PXASSPDef pxa250_ssp[] = {
41
{ 0x41000000, PXA2XX_PIC_SSP },
46
static PXASSPDef pxa255_ssp[] = {
47
{ 0x41000000, PXA2XX_PIC_SSP },
48
{ 0x41400000, PXA25X_PIC_NSSP },
53
static PXASSPDef pxa26x_ssp[] = {
54
{ 0x41000000, PXA2XX_PIC_SSP },
55
{ 0x41400000, PXA25X_PIC_NSSP },
56
{ 0x41500000, PXA26X_PIC_ASSP },
61
static PXASSPDef pxa27x_ssp[] = {
62
{ 0x41000000, PXA2XX_PIC_SSP },
63
{ 0x41700000, PXA27X_PIC_SSP2 },
64
{ 0x41900000, PXA2XX_PIC_SSP3 },
68
#define PMCR 0x00 /* Power Manager Control register */
69
#define PSSR 0x04 /* Power Manager Sleep Status register */
70
#define PSPR 0x08 /* Power Manager Scratch-Pad register */
71
#define PWER 0x0c /* Power Manager Wake-Up Enable register */
72
#define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
73
#define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
74
#define PEDR 0x18 /* Power Manager Edge-Detect Status register */
75
#define PCFR 0x1c /* Power Manager General Configuration register */
76
#define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
77
#define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
78
#define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
79
#define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
80
#define RCSR 0x30 /* Reset Controller Status register */
81
#define PSLR 0x34 /* Power Manager Sleep Configuration register */
82
#define PTSR 0x38 /* Power Manager Standby Configuration register */
83
#define PVCR 0x40 /* Power Manager Voltage Change Control register */
84
#define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
85
#define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
86
#define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
87
#define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
88
#define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
90
static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
92
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
100
return s->pm_regs[addr >> 2];
103
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
109
static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
112
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
117
s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a);
118
s->pm_regs[addr >> 2] |= value & 0x15;
121
case PSSR: /* Read-clean registers */
124
s->pm_regs[addr >> 2] &= ~value;
127
default: /* Read-write registers */
128
if (addr >= PMCR && addr <= PCMD31 && !(addr & 3)) {
129
s->pm_regs[addr >> 2] = value;
133
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
138
static CPUReadMemoryFunc *pxa2xx_pm_readfn[] = {
144
static CPUWriteMemoryFunc *pxa2xx_pm_writefn[] = {
150
static void pxa2xx_pm_save(QEMUFile *f, void *opaque)
152
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
155
for (i = 0; i < 0x40; i ++)
156
qemu_put_be32s(f, &s->pm_regs[i]);
159
static int pxa2xx_pm_load(QEMUFile *f, void *opaque, int version_id)
161
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
164
for (i = 0; i < 0x40; i ++)
165
qemu_get_be32s(f, &s->pm_regs[i]);
170
#define CCCR 0x00 /* Core Clock Configuration register */
171
#define CKEN 0x04 /* Clock Enable register */
172
#define OSCC 0x08 /* Oscillator Configuration register */
173
#define CCSR 0x0c /* Core Clock Status register */
175
static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
177
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
184
return s->cm_regs[addr >> 2];
187
return s->cm_regs[CCCR >> 2] | (3 << 28);
190
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
196
static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
199
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
205
s->cm_regs[addr >> 2] = value;
209
s->cm_regs[addr >> 2] &= ~0x6c;
210
s->cm_regs[addr >> 2] |= value & 0x6e;
211
if ((value >> 1) & 1) /* OON */
212
s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
216
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
221
static CPUReadMemoryFunc *pxa2xx_cm_readfn[] = {
227
static CPUWriteMemoryFunc *pxa2xx_cm_writefn[] = {
233
static void pxa2xx_cm_save(QEMUFile *f, void *opaque)
235
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
238
for (i = 0; i < 4; i ++)
239
qemu_put_be32s(f, &s->cm_regs[i]);
240
qemu_put_be32s(f, &s->clkcfg);
241
qemu_put_be32s(f, &s->pmnc);
244
static int pxa2xx_cm_load(QEMUFile *f, void *opaque, int version_id)
246
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
249
for (i = 0; i < 4; i ++)
250
qemu_get_be32s(f, &s->cm_regs[i]);
251
qemu_get_be32s(f, &s->clkcfg);
252
qemu_get_be32s(f, &s->pmnc);
257
static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
259
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
262
case 6: /* Clock Configuration register */
265
case 7: /* Power Mode register */
269
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
275
static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
278
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
279
static const char *pwrmode[8] = {
280
"Normal", "Idle", "Deep-idle", "Standby",
281
"Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
285
case 6: /* Clock Configuration register */
286
s->clkcfg = value & 0xf;
288
printf("%s: CPU frequency change attempt\n", __FUNCTION__);
291
case 7: /* Power Mode register */
293
printf("%s: CPU voltage change attempt\n", __FUNCTION__);
301
if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
302
cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
309
cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
310
s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
314
s->env->uncached_cpsr =
315
ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
316
s->env->cp15.c1_sys = 0;
317
s->env->cp15.c1_coproc = 0;
318
s->env->cp15.c2_base0 = 0;
320
s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
321
s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
324
* The scratch-pad register is almost universally used
325
* for storing the return address on suspend. For the
326
* lack of a resuming bootloader, perform a jump
327
* directly to that address.
329
memset(s->env->regs, 0, 4 * 15);
330
s->env->regs[15] = s->pm_regs[PSPR >> 2];
333
buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
334
cpu_physical_memory_write(0, &buffer, 4);
335
buffer = s->pm_regs[PSPR >> 2];
336
cpu_physical_memory_write(8, &buffer, 4);
340
cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
346
printf("%s: machine entered %s mode\n", __FUNCTION__,
352
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
357
/* Performace Monitoring Registers */
358
#define CPPMNC 0 /* Performance Monitor Control register */
359
#define CPCCNT 1 /* Clock Counter register */
360
#define CPINTEN 4 /* Interrupt Enable register */
361
#define CPFLAG 5 /* Overflow Flag register */
362
#define CPEVTSEL 8 /* Event Selection register */
364
#define CPPMN0 0 /* Performance Count register 0 */
365
#define CPPMN1 1 /* Performance Count register 1 */
366
#define CPPMN2 2 /* Performance Count register 2 */
367
#define CPPMN3 3 /* Performance Count register 3 */
369
static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
371
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
378
return qemu_get_clock(vm_clock);
387
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
393
static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,
396
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
410
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
415
static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)
419
return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
421
return pxa2xx_perf_read(opaque, op2, reg, crm);
432
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
438
static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
443
pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);
446
pxa2xx_perf_write(opaque, op2, reg, crm, value);
458
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
463
#define MDCNFG 0x00 /* SDRAM Configuration register */
464
#define MDREFR 0x04 /* SDRAM Refresh Control register */
465
#define MSC0 0x08 /* Static Memory Control register 0 */
466
#define MSC1 0x0c /* Static Memory Control register 1 */
467
#define MSC2 0x10 /* Static Memory Control register 2 */
468
#define MECR 0x14 /* Expansion Memory Bus Config register */
469
#define SXCNFG 0x1c /* Synchronous Static Memory Config register */
470
#define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
471
#define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
472
#define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
473
#define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
474
#define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
475
#define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
476
#define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
477
#define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
478
#define ARB_CNTL 0x48 /* Arbiter Control register */
479
#define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
480
#define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
481
#define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
482
#define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
483
#define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
484
#define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
485
#define SA1110 0x64 /* SA-1110 Memory Compatibility register */
487
static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
489
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
493
case MDCNFG ... SA1110:
495
return s->mm_regs[addr >> 2];
498
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
504
static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
507
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
511
case MDCNFG ... SA1110:
512
if ((addr & 3) == 0) {
513
s->mm_regs[addr >> 2] = value;
518
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
523
static CPUReadMemoryFunc *pxa2xx_mm_readfn[] = {
529
static CPUWriteMemoryFunc *pxa2xx_mm_writefn[] = {
535
static void pxa2xx_mm_save(QEMUFile *f, void *opaque)
537
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
540
for (i = 0; i < 0x1a; i ++)
541
qemu_put_be32s(f, &s->mm_regs[i]);
544
static int pxa2xx_mm_load(QEMUFile *f, void *opaque, int version_id)
546
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
549
for (i = 0; i < 0x1a; i ++)
550
qemu_get_be32s(f, &s->mm_regs[i]);
555
/* Synchronous Serial Ports */
556
struct pxa2xx_ssp_s {
557
target_phys_addr_t base;
570
uint32_t rx_fifo[16];
574
uint32_t (*readfn)(void *opaque);
575
void (*writefn)(void *opaque, uint32_t value);
579
#define SSCR0 0x00 /* SSP Control register 0 */
580
#define SSCR1 0x04 /* SSP Control register 1 */
581
#define SSSR 0x08 /* SSP Status register */
582
#define SSITR 0x0c /* SSP Interrupt Test register */
583
#define SSDR 0x10 /* SSP Data register */
584
#define SSTO 0x28 /* SSP Time-Out register */
585
#define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
586
#define SSTSA 0x30 /* SSP TX Time Slot Active register */
587
#define SSRSA 0x34 /* SSP RX Time Slot Active register */
588
#define SSTSS 0x38 /* SSP Time Slot Status register */
589
#define SSACD 0x3c /* SSP Audio Clock Divider register */
591
/* Bitfields for above registers */
592
#define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
593
#define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
594
#define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
595
#define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
596
#define SSCR0_SSE (1 << 7)
597
#define SSCR0_RIM (1 << 22)
598
#define SSCR0_TIM (1 << 23)
599
#define SSCR0_MOD (1 << 31)
600
#define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
601
#define SSCR1_RIE (1 << 0)
602
#define SSCR1_TIE (1 << 1)
603
#define SSCR1_LBM (1 << 2)
604
#define SSCR1_MWDS (1 << 5)
605
#define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
606
#define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
607
#define SSCR1_EFWR (1 << 14)
608
#define SSCR1_PINTE (1 << 18)
609
#define SSCR1_TINTE (1 << 19)
610
#define SSCR1_RSRE (1 << 20)
611
#define SSCR1_TSRE (1 << 21)
612
#define SSCR1_EBCEI (1 << 29)
613
#define SSITR_INT (7 << 5)
614
#define SSSR_TNF (1 << 2)
615
#define SSSR_RNE (1 << 3)
616
#define SSSR_TFS (1 << 5)
617
#define SSSR_RFS (1 << 6)
618
#define SSSR_ROR (1 << 7)
619
#define SSSR_PINT (1 << 18)
620
#define SSSR_TINT (1 << 19)
621
#define SSSR_EOC (1 << 20)
622
#define SSSR_TUR (1 << 21)
623
#define SSSR_BCE (1 << 23)
624
#define SSSR_RW 0x00bc0080
626
static void pxa2xx_ssp_int_update(struct pxa2xx_ssp_s *s)
630
level |= s->ssitr & SSITR_INT;
631
level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
632
level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
633
level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
634
level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
635
level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
636
level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
637
level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
638
level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
639
qemu_set_irq(s->irq, !!level);
642
static void pxa2xx_ssp_fifo_update(struct pxa2xx_ssp_s *s)
644
s->sssr &= ~(0xf << 12); /* Clear RFL */
645
s->sssr &= ~(0xf << 8); /* Clear TFL */
646
s->sssr &= ~SSSR_TNF;
648
s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
649
if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
652
s->sssr &= ~SSSR_RFS;
653
if (0 <= SSCR1_TFT(s->sscr[1]))
656
s->sssr &= ~SSSR_TFS;
660
s->sssr &= ~SSSR_RNE;
664
pxa2xx_ssp_int_update(s);
667
static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)
669
struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
685
return s->sssr | s->ssitr;
689
if (s->rx_level < 1) {
690
printf("%s: SSP Rx Underrun\n", __FUNCTION__);
694
retval = s->rx_fifo[s->rx_start ++];
696
pxa2xx_ssp_fifo_update(s);
707
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
713
static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
716
struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
721
s->sscr[0] = value & 0xc7ffffff;
722
s->enable = value & SSCR0_SSE;
723
if (value & SSCR0_MOD)
724
printf("%s: Attempt to use network mode\n", __FUNCTION__);
725
if (s->enable && SSCR0_DSS(value) < 4)
726
printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
728
if (!(value & SSCR0_SSE)) {
733
pxa2xx_ssp_fifo_update(s);
738
if (value & (SSCR1_LBM | SSCR1_EFWR))
739
printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
740
pxa2xx_ssp_fifo_update(s);
752
s->ssitr = value & SSITR_INT;
753
pxa2xx_ssp_int_update(s);
757
s->sssr &= ~(value & SSSR_RW);
758
pxa2xx_ssp_int_update(s);
762
if (SSCR0_UWIRE(s->sscr[0])) {
763
if (s->sscr[1] & SSCR1_MWDS)
768
/* Note how 32bits overflow does no harm here */
769
value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
771
/* Data goes from here to the Tx FIFO and is shifted out from
772
* there directly to the slave, no need to buffer it.
776
s->writefn(s->opaque, value);
778
if (s->rx_level < 0x10) {
780
s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] =
781
s->readfn(s->opaque);
783
s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = 0x0;
787
pxa2xx_ssp_fifo_update(s);
803
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
808
void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port,
809
uint32_t (*readfn)(void *opaque),
810
void (*writefn)(void *opaque, uint32_t value), void *opaque)
813
printf("%s: no such SSP\n", __FUNCTION__);
817
port->opaque = opaque;
818
port->readfn = readfn;
819
port->writefn = writefn;
822
static CPUReadMemoryFunc *pxa2xx_ssp_readfn[] = {
828
static CPUWriteMemoryFunc *pxa2xx_ssp_writefn[] = {
834
static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
836
struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
839
qemu_put_be32(f, s->enable);
841
qemu_put_be32s(f, &s->sscr[0]);
842
qemu_put_be32s(f, &s->sscr[1]);
843
qemu_put_be32s(f, &s->sspsp);
844
qemu_put_be32s(f, &s->ssto);
845
qemu_put_be32s(f, &s->ssitr);
846
qemu_put_be32s(f, &s->sssr);
847
qemu_put_8s(f, &s->sstsa);
848
qemu_put_8s(f, &s->ssrsa);
849
qemu_put_8s(f, &s->ssacd);
851
qemu_put_byte(f, s->rx_level);
852
for (i = 0; i < s->rx_level; i ++)
853
qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);
856
static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
858
struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
861
s->enable = qemu_get_be32(f);
863
qemu_get_be32s(f, &s->sscr[0]);
864
qemu_get_be32s(f, &s->sscr[1]);
865
qemu_get_be32s(f, &s->sspsp);
866
qemu_get_be32s(f, &s->ssto);
867
qemu_get_be32s(f, &s->ssitr);
868
qemu_get_be32s(f, &s->sssr);
869
qemu_get_8s(f, &s->sstsa);
870
qemu_get_8s(f, &s->ssrsa);
871
qemu_get_8s(f, &s->ssacd);
873
s->rx_level = qemu_get_byte(f);
875
for (i = 0; i < s->rx_level; i ++)
876
s->rx_fifo[i] = qemu_get_byte(f);
881
/* Real-Time Clock */
882
#define RCNR 0x00 /* RTC Counter register */
883
#define RTAR 0x04 /* RTC Alarm register */
884
#define RTSR 0x08 /* RTC Status register */
885
#define RTTR 0x0c /* RTC Timer Trim register */
886
#define RDCR 0x10 /* RTC Day Counter register */
887
#define RYCR 0x14 /* RTC Year Counter register */
888
#define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
889
#define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
890
#define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
891
#define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
892
#define SWCR 0x28 /* RTC Stopwatch Counter register */
893
#define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
894
#define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
895
#define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
896
#define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
898
static inline void pxa2xx_rtc_int_update(struct pxa2xx_state_s *s)
900
qemu_set_irq(s->pic[PXA2XX_PIC_RTCALARM], !!(s->rtsr & 0x2553));
903
static void pxa2xx_rtc_hzupdate(struct pxa2xx_state_s *s)
905
int64_t rt = qemu_get_clock(rt_clock);
906
s->last_rcnr += ((rt - s->last_hz) << 15) /
907
(1000 * ((s->rttr & 0xffff) + 1));
908
s->last_rdcr += ((rt - s->last_hz) << 15) /
909
(1000 * ((s->rttr & 0xffff) + 1));
913
static void pxa2xx_rtc_swupdate(struct pxa2xx_state_s *s)
915
int64_t rt = qemu_get_clock(rt_clock);
916
if (s->rtsr & (1 << 12))
917
s->last_swcr += (rt - s->last_sw) / 10;
921
static void pxa2xx_rtc_piupdate(struct pxa2xx_state_s *s)
923
int64_t rt = qemu_get_clock(rt_clock);
924
if (s->rtsr & (1 << 15))
925
s->last_swcr += rt - s->last_pi;
929
static inline void pxa2xx_rtc_alarm_update(struct pxa2xx_state_s *s,
932
if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
933
qemu_mod_timer(s->rtc_hz, s->last_hz +
934
(((s->rtar - s->last_rcnr) * 1000 *
935
((s->rttr & 0xffff) + 1)) >> 15));
937
qemu_del_timer(s->rtc_hz);
939
if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
940
qemu_mod_timer(s->rtc_rdal1, s->last_hz +
941
(((s->rdar1 - s->last_rdcr) * 1000 *
942
((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
944
qemu_del_timer(s->rtc_rdal1);
946
if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
947
qemu_mod_timer(s->rtc_rdal2, s->last_hz +
948
(((s->rdar2 - s->last_rdcr) * 1000 *
949
((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
951
qemu_del_timer(s->rtc_rdal2);
953
if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
954
qemu_mod_timer(s->rtc_swal1, s->last_sw +
955
(s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
957
qemu_del_timer(s->rtc_swal1);
959
if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
960
qemu_mod_timer(s->rtc_swal2, s->last_sw +
961
(s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
963
qemu_del_timer(s->rtc_swal2);
965
if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
966
qemu_mod_timer(s->rtc_pi, s->last_pi +
967
(s->piar & 0xffff) - s->last_rtcpicr);
969
qemu_del_timer(s->rtc_pi);
972
static inline void pxa2xx_rtc_hz_tick(void *opaque)
974
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
976
pxa2xx_rtc_alarm_update(s, s->rtsr);
977
pxa2xx_rtc_int_update(s);
980
static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
982
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
984
pxa2xx_rtc_alarm_update(s, s->rtsr);
985
pxa2xx_rtc_int_update(s);
988
static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
990
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
992
pxa2xx_rtc_alarm_update(s, s->rtsr);
993
pxa2xx_rtc_int_update(s);
996
static inline void pxa2xx_rtc_swal1_tick(void *opaque)
998
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1000
pxa2xx_rtc_alarm_update(s, s->rtsr);
1001
pxa2xx_rtc_int_update(s);
1004
static inline void pxa2xx_rtc_swal2_tick(void *opaque)
1006
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1007
s->rtsr |= (1 << 10);
1008
pxa2xx_rtc_alarm_update(s, s->rtsr);
1009
pxa2xx_rtc_int_update(s);
1012
static inline void pxa2xx_rtc_pi_tick(void *opaque)
1014
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1015
s->rtsr |= (1 << 13);
1016
pxa2xx_rtc_piupdate(s);
1017
s->last_rtcpicr = 0;
1018
pxa2xx_rtc_alarm_update(s, s->rtsr);
1019
pxa2xx_rtc_int_update(s);
1022
static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
1024
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1025
addr -= s->rtc_base;
1049
return s->last_rcnr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
1050
(1000 * ((s->rttr & 0xffff) + 1));
1052
return s->last_rdcr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
1053
(1000 * ((s->rttr & 0xffff) + 1));
1055
return s->last_rycr;
1057
if (s->rtsr & (1 << 12))
1058
return s->last_swcr + (qemu_get_clock(rt_clock) - s->last_sw) / 10;
1060
return s->last_swcr;
1062
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1068
static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
1071
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1072
addr -= s->rtc_base;
1076
if (!(s->rttr & (1 << 31))) {
1077
pxa2xx_rtc_hzupdate(s);
1079
pxa2xx_rtc_alarm_update(s, s->rtsr);
1084
if ((s->rtsr ^ value) & (1 << 15))
1085
pxa2xx_rtc_piupdate(s);
1087
if ((s->rtsr ^ value) & (1 << 12))
1088
pxa2xx_rtc_swupdate(s);
1090
if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1091
pxa2xx_rtc_alarm_update(s, value);
1093
s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1094
pxa2xx_rtc_int_update(s);
1099
pxa2xx_rtc_alarm_update(s, s->rtsr);
1104
pxa2xx_rtc_alarm_update(s, s->rtsr);
1109
pxa2xx_rtc_alarm_update(s, s->rtsr);
1114
pxa2xx_rtc_alarm_update(s, s->rtsr);
1119
pxa2xx_rtc_alarm_update(s, s->rtsr);
1123
pxa2xx_rtc_swupdate(s);
1126
pxa2xx_rtc_alarm_update(s, s->rtsr);
1131
pxa2xx_rtc_alarm_update(s, s->rtsr);
1136
pxa2xx_rtc_alarm_update(s, s->rtsr);
1140
pxa2xx_rtc_hzupdate(s);
1141
s->last_rcnr = value;
1142
pxa2xx_rtc_alarm_update(s, s->rtsr);
1146
pxa2xx_rtc_hzupdate(s);
1147
s->last_rdcr = value;
1148
pxa2xx_rtc_alarm_update(s, s->rtsr);
1152
s->last_rycr = value;
1156
pxa2xx_rtc_swupdate(s);
1157
s->last_swcr = value;
1158
pxa2xx_rtc_alarm_update(s, s->rtsr);
1162
pxa2xx_rtc_piupdate(s);
1163
s->last_rtcpicr = value & 0xffff;
1164
pxa2xx_rtc_alarm_update(s, s->rtsr);
1168
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1172
static CPUReadMemoryFunc *pxa2xx_rtc_readfn[] = {
1178
static CPUWriteMemoryFunc *pxa2xx_rtc_writefn[] = {
1184
static void pxa2xx_rtc_init(struct pxa2xx_state_s *s)
1197
tm = localtime(&ti);
1198
wom = ((tm->tm_mday - 1) / 7) + 1;
1200
s->last_rcnr = (uint32_t) ti;
1201
s->last_rdcr = (wom << 20) | ((tm->tm_wday + 1) << 17) |
1202
(tm->tm_hour << 12) | (tm->tm_min << 6) | tm->tm_sec;
1203
s->last_rycr = ((tm->tm_year + 1900) << 9) |
1204
((tm->tm_mon + 1) << 5) | tm->tm_mday;
1205
s->last_swcr = (tm->tm_hour << 19) |
1206
(tm->tm_min << 13) | (tm->tm_sec << 7);
1207
s->last_rtcpicr = 0;
1208
s->last_hz = s->last_sw = s->last_pi = qemu_get_clock(rt_clock);
1210
s->rtc_hz = qemu_new_timer(rt_clock, pxa2xx_rtc_hz_tick, s);
1211
s->rtc_rdal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal1_tick, s);
1212
s->rtc_rdal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal2_tick, s);
1213
s->rtc_swal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal1_tick, s);
1214
s->rtc_swal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal2_tick, s);
1215
s->rtc_pi = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick, s);
1218
static void pxa2xx_rtc_save(QEMUFile *f, void *opaque)
1220
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1222
pxa2xx_rtc_hzupdate(s);
1223
pxa2xx_rtc_piupdate(s);
1224
pxa2xx_rtc_swupdate(s);
1226
qemu_put_be32s(f, &s->rttr);
1227
qemu_put_be32s(f, &s->rtsr);
1228
qemu_put_be32s(f, &s->rtar);
1229
qemu_put_be32s(f, &s->rdar1);
1230
qemu_put_be32s(f, &s->rdar2);
1231
qemu_put_be32s(f, &s->ryar1);
1232
qemu_put_be32s(f, &s->ryar2);
1233
qemu_put_be32s(f, &s->swar1);
1234
qemu_put_be32s(f, &s->swar2);
1235
qemu_put_be32s(f, &s->piar);
1236
qemu_put_be32s(f, &s->last_rcnr);
1237
qemu_put_be32s(f, &s->last_rdcr);
1238
qemu_put_be32s(f, &s->last_rycr);
1239
qemu_put_be32s(f, &s->last_swcr);
1240
qemu_put_be32s(f, &s->last_rtcpicr);
1241
qemu_put_be64s(f, &s->last_hz);
1242
qemu_put_be64s(f, &s->last_sw);
1243
qemu_put_be64s(f, &s->last_pi);
1246
static int pxa2xx_rtc_load(QEMUFile *f, void *opaque, int version_id)
1248
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1250
qemu_get_be32s(f, &s->rttr);
1251
qemu_get_be32s(f, &s->rtsr);
1252
qemu_get_be32s(f, &s->rtar);
1253
qemu_get_be32s(f, &s->rdar1);
1254
qemu_get_be32s(f, &s->rdar2);
1255
qemu_get_be32s(f, &s->ryar1);
1256
qemu_get_be32s(f, &s->ryar2);
1257
qemu_get_be32s(f, &s->swar1);
1258
qemu_get_be32s(f, &s->swar2);
1259
qemu_get_be32s(f, &s->piar);
1260
qemu_get_be32s(f, &s->last_rcnr);
1261
qemu_get_be32s(f, &s->last_rdcr);
1262
qemu_get_be32s(f, &s->last_rycr);
1263
qemu_get_be32s(f, &s->last_swcr);
1264
qemu_get_be32s(f, &s->last_rtcpicr);
1265
qemu_get_be64s(f, &s->last_hz);
1266
qemu_get_be64s(f, &s->last_sw);
1267
qemu_get_be64s(f, &s->last_pi);
1269
pxa2xx_rtc_alarm_update(s, s->rtsr);
1275
struct pxa2xx_i2c_s {
1278
target_phys_addr_t base;
1287
#define IBMR 0x80 /* I2C Bus Monitor register */
1288
#define IDBR 0x88 /* I2C Data Buffer register */
1289
#define ICR 0x90 /* I2C Control register */
1290
#define ISR 0x98 /* I2C Status register */
1291
#define ISAR 0xa0 /* I2C Slave Address register */
1293
static void pxa2xx_i2c_update(struct pxa2xx_i2c_s *s)
1296
level |= s->status & s->control & (1 << 10); /* BED */
1297
level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1298
level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1299
level |= s->status & (1 << 9); /* SAD */
1300
qemu_set_irq(s->irq, !!level);
1303
/* These are only stubs now. */
1304
static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event)
1306
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
1309
case I2C_START_SEND:
1310
s->status |= (1 << 9); /* set SAD */
1311
s->status &= ~(1 << 0); /* clear RWM */
1313
case I2C_START_RECV:
1314
s->status |= (1 << 9); /* set SAD */
1315
s->status |= 1 << 0; /* set RWM */
1318
s->status |= (1 << 4); /* set SSD */
1321
s->status |= 1 << 1; /* set ACKNAK */
1324
pxa2xx_i2c_update(s);
1327
static int pxa2xx_i2c_rx(i2c_slave *i2c)
1329
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
1330
if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1333
if (s->status & (1 << 0)) { /* RWM */
1334
s->status |= 1 << 6; /* set ITE */
1336
pxa2xx_i2c_update(s);
1341
static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data)
1343
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
1344
if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1347
if (!(s->status & (1 << 0))) { /* RWM */
1348
s->status |= 1 << 7; /* set IRF */
1351
pxa2xx_i2c_update(s);
1356
static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
1358
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
1365
return s->status | (i2c_bus_busy(s->bus) << 2);
1367
return s->slave.address;
1371
if (s->status & (1 << 2))
1372
s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
1377
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1383
static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
1386
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
1392
s->control = value & 0xfff7;
1393
if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1394
/* TODO: slave mode */
1395
if (value & (1 << 0)) { /* START condition */
1397
s->status |= 1 << 0; /* set RWM */
1399
s->status &= ~(1 << 0); /* clear RWM */
1400
ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1402
if (s->status & (1 << 0)) { /* RWM */
1403
s->data = i2c_recv(s->bus);
1404
if (value & (1 << 2)) /* ACKNAK */
1408
ack = !i2c_send(s->bus, s->data);
1411
if (value & (1 << 1)) /* STOP condition */
1412
i2c_end_transfer(s->bus);
1415
if (value & (1 << 0)) /* START condition */
1416
s->status |= 1 << 6; /* set ITE */
1418
if (s->status & (1 << 0)) /* RWM */
1419
s->status |= 1 << 7; /* set IRF */
1421
s->status |= 1 << 6; /* set ITE */
1422
s->status &= ~(1 << 1); /* clear ACKNAK */
1424
s->status |= 1 << 6; /* set ITE */
1425
s->status |= 1 << 10; /* set BED */
1426
s->status |= 1 << 1; /* set ACKNAK */
1429
if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
1430
if (value & (1 << 4)) /* MA */
1431
i2c_end_transfer(s->bus);
1432
pxa2xx_i2c_update(s);
1436
s->status &= ~(value & 0x07f0);
1437
pxa2xx_i2c_update(s);
1441
i2c_set_slave_address(&s->slave, value & 0x7f);
1445
s->data = value & 0xff;
1449
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1453
static CPUReadMemoryFunc *pxa2xx_i2c_readfn[] = {
1459
static CPUWriteMemoryFunc *pxa2xx_i2c_writefn[] = {
1465
static void pxa2xx_i2c_save(QEMUFile *f, void *opaque)
1467
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
1469
qemu_put_be16s(f, &s->control);
1470
qemu_put_be16s(f, &s->status);
1471
qemu_put_8s(f, &s->ibmr);
1472
qemu_put_8s(f, &s->data);
1474
i2c_bus_save(f, s->bus);
1475
i2c_slave_save(f, &s->slave);
1478
static int pxa2xx_i2c_load(QEMUFile *f, void *opaque, int version_id)
1480
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
1482
qemu_get_be16s(f, &s->control);
1483
qemu_get_be16s(f, &s->status);
1484
qemu_get_8s(f, &s->ibmr);
1485
qemu_get_8s(f, &s->data);
1487
i2c_bus_load(f, s->bus);
1488
i2c_slave_load(f, &s->slave);
1492
struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
1493
qemu_irq irq, uint32_t page_size)
1496
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *)
1497
i2c_slave_init(i2c_init_bus(), 0, sizeof(struct pxa2xx_i2c_s));
1501
s->slave.event = pxa2xx_i2c_event;
1502
s->slave.recv = pxa2xx_i2c_rx;
1503
s->slave.send = pxa2xx_i2c_tx;
1504
s->bus = i2c_init_bus();
1506
iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn,
1507
pxa2xx_i2c_writefn, s);
1508
cpu_register_physical_memory(s->base & ~page_size, page_size, iomemtype);
1510
register_savevm("pxa2xx_i2c", base, 0,
1511
pxa2xx_i2c_save, pxa2xx_i2c_load, s);
1516
i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2c_s *s)
1521
/* PXA Inter-IC Sound Controller */
1522
static void pxa2xx_i2s_reset(struct pxa2xx_i2s_s *i2s)
1528
i2s->control[0] = 0x00;
1529
i2s->control[1] = 0x00;
1534
#define SACR_TFTH(val) ((val >> 8) & 0xf)
1535
#define SACR_RFTH(val) ((val >> 12) & 0xf)
1536
#define SACR_DREC(val) (val & (1 << 3))
1537
#define SACR_DPRL(val) (val & (1 << 4))
1539
static inline void pxa2xx_i2s_update(struct pxa2xx_i2s_s *i2s)
1542
rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1543
!SACR_DREC(i2s->control[1]);
1544
tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1545
i2s->enable && !SACR_DPRL(i2s->control[1]);
1547
pxa2xx_dma_request(i2s->dma, PXA2XX_RX_RQ_I2S, rfs);
1548
pxa2xx_dma_request(i2s->dma, PXA2XX_TX_RQ_I2S, tfs);
1550
i2s->status &= 0xe0;
1551
if (i2s->fifo_len < 16 || !i2s->enable)
1552
i2s->status |= 1 << 0; /* TNF */
1554
i2s->status |= 1 << 1; /* RNE */
1556
i2s->status |= 1 << 2; /* BSY */
1558
i2s->status |= 1 << 3; /* TFS */
1560
i2s->status |= 1 << 4; /* RFS */
1561
if (!(i2s->tx_len && i2s->enable))
1562
i2s->status |= i2s->fifo_len << 8; /* TFL */
1563
i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1565
qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1568
#define SACR0 0x00 /* Serial Audio Global Control register */
1569
#define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1570
#define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1571
#define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1572
#define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1573
#define SADIV 0x60 /* Serial Audio Clock Divider register */
1574
#define SADR 0x80 /* Serial Audio Data register */
1576
static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
1578
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1583
return s->control[0];
1585
return s->control[1];
1595
if (s->rx_len > 0) {
1597
pxa2xx_i2s_update(s);
1598
return s->codec_in(s->opaque);
1602
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1608
static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
1611
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1617
if (value & (1 << 3)) /* RST */
1618
pxa2xx_i2s_reset(s);
1619
s->control[0] = value & 0xff3d;
1620
if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1621
for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1622
s->codec_out(s->opaque, *sample);
1623
s->status &= ~(1 << 7); /* I2SOFF */
1625
if (value & (1 << 4)) /* EFWR */
1626
printf("%s: Attempt to use special function\n", __FUNCTION__);
1627
s->enable = ((value ^ 4) & 5) == 5; /* ENB && !RST*/
1628
pxa2xx_i2s_update(s);
1631
s->control[1] = value & 0x0039;
1632
if (value & (1 << 5)) /* ENLBF */
1633
printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1634
if (value & (1 << 4)) /* DPRL */
1636
pxa2xx_i2s_update(s);
1639
s->mask = value & 0x0078;
1640
pxa2xx_i2s_update(s);
1643
s->status &= ~(value & (3 << 5));
1644
pxa2xx_i2s_update(s);
1647
s->clk = value & 0x007f;
1650
if (s->tx_len && s->enable) {
1652
pxa2xx_i2s_update(s);
1653
s->codec_out(s->opaque, value);
1654
} else if (s->fifo_len < 16) {
1655
s->fifo[s->fifo_len ++] = value;
1656
pxa2xx_i2s_update(s);
1660
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1664
static CPUReadMemoryFunc *pxa2xx_i2s_readfn[] = {
1670
static CPUWriteMemoryFunc *pxa2xx_i2s_writefn[] = {
1676
static void pxa2xx_i2s_save(QEMUFile *f, void *opaque)
1678
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1680
qemu_put_be32s(f, &s->control[0]);
1681
qemu_put_be32s(f, &s->control[1]);
1682
qemu_put_be32s(f, &s->status);
1683
qemu_put_be32s(f, &s->mask);
1684
qemu_put_be32s(f, &s->clk);
1686
qemu_put_be32(f, s->enable);
1687
qemu_put_be32(f, s->rx_len);
1688
qemu_put_be32(f, s->tx_len);
1689
qemu_put_be32(f, s->fifo_len);
1692
static int pxa2xx_i2s_load(QEMUFile *f, void *opaque, int version_id)
1694
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1696
qemu_get_be32s(f, &s->control[0]);
1697
qemu_get_be32s(f, &s->control[1]);
1698
qemu_get_be32s(f, &s->status);
1699
qemu_get_be32s(f, &s->mask);
1700
qemu_get_be32s(f, &s->clk);
1702
s->enable = qemu_get_be32(f);
1703
s->rx_len = qemu_get_be32(f);
1704
s->tx_len = qemu_get_be32(f);
1705
s->fifo_len = qemu_get_be32(f);
1710
static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1712
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1715
/* Signal FIFO errors */
1716
if (s->enable && s->tx_len)
1717
s->status |= 1 << 5; /* TUR */
1718
if (s->enable && s->rx_len)
1719
s->status |= 1 << 6; /* ROR */
1721
/* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1722
* handle the cases where it makes a difference. */
1723
s->tx_len = tx - s->fifo_len;
1725
/* Note that is s->codec_out wasn't set, we wouldn't get called. */
1727
for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1728
s->codec_out(s->opaque, *sample);
1729
pxa2xx_i2s_update(s);
1732
static struct pxa2xx_i2s_s *pxa2xx_i2s_init(target_phys_addr_t base,
1733
qemu_irq irq, struct pxa2xx_dma_state_s *dma)
1736
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *)
1737
qemu_mallocz(sizeof(struct pxa2xx_i2s_s));
1742
s->data_req = pxa2xx_i2s_data_req;
1744
pxa2xx_i2s_reset(s);
1746
iomemtype = cpu_register_io_memory(0, pxa2xx_i2s_readfn,
1747
pxa2xx_i2s_writefn, s);
1748
cpu_register_physical_memory(s->base & 0xfff00000, 0x100000, iomemtype);
1750
register_savevm("pxa2xx_i2s", base, 0,
1751
pxa2xx_i2s_save, pxa2xx_i2s_load, s);
1756
/* PXA Fast Infra-red Communications Port */
1757
struct pxa2xx_fir_s {
1758
target_phys_addr_t base;
1760
struct pxa2xx_dma_state_s *dma;
1762
CharDriverState *chr;
1769
uint8_t rx_fifo[64];
1772
static void pxa2xx_fir_reset(struct pxa2xx_fir_s *s)
1774
s->control[0] = 0x00;
1775
s->control[1] = 0x00;
1776
s->control[2] = 0x00;
1777
s->status[0] = 0x00;
1778
s->status[1] = 0x00;
1782
static inline void pxa2xx_fir_update(struct pxa2xx_fir_s *s)
1784
static const int tresh[4] = { 8, 16, 32, 0 };
1786
if ((s->control[0] & (1 << 4)) && /* RXE */
1787
s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1788
s->status[0] |= 1 << 4; /* RFS */
1790
s->status[0] &= ~(1 << 4); /* RFS */
1791
if (s->control[0] & (1 << 3)) /* TXE */
1792
s->status[0] |= 1 << 3; /* TFS */
1794
s->status[0] &= ~(1 << 3); /* TFS */
1796
s->status[1] |= 1 << 2; /* RNE */
1798
s->status[1] &= ~(1 << 2); /* RNE */
1799
if (s->control[0] & (1 << 4)) /* RXE */
1800
s->status[1] |= 1 << 0; /* RSY */
1802
s->status[1] &= ~(1 << 0); /* RSY */
1804
intr |= (s->control[0] & (1 << 5)) && /* RIE */
1805
(s->status[0] & (1 << 4)); /* RFS */
1806
intr |= (s->control[0] & (1 << 6)) && /* TIE */
1807
(s->status[0] & (1 << 3)); /* TFS */
1808
intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1809
(s->status[0] & (1 << 6)); /* EOC */
1810
intr |= (s->control[0] & (1 << 2)) && /* TUS */
1811
(s->status[0] & (1 << 1)); /* TUR */
1812
intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1814
pxa2xx_dma_request(s->dma, PXA2XX_RX_RQ_ICP, (s->status[0] >> 4) & 1);
1815
pxa2xx_dma_request(s->dma, PXA2XX_TX_RQ_ICP, (s->status[0] >> 3) & 1);
1817
qemu_set_irq(s->irq, intr && s->enable);
1820
#define ICCR0 0x00 /* FICP Control register 0 */
1821
#define ICCR1 0x04 /* FICP Control register 1 */
1822
#define ICCR2 0x08 /* FICP Control register 2 */
1823
#define ICDR 0x0c /* FICP Data register */
1824
#define ICSR0 0x14 /* FICP Status register 0 */
1825
#define ICSR1 0x18 /* FICP Status register 1 */
1826
#define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1828
static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr)
1830
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1836
return s->control[0];
1838
return s->control[1];
1840
return s->control[2];
1842
s->status[0] &= ~0x01;
1843
s->status[1] &= ~0x72;
1846
ret = s->rx_fifo[s->rx_start ++];
1848
pxa2xx_fir_update(s);
1851
printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1854
return s->status[0];
1856
return s->status[1] | (1 << 3); /* TNF */
1860
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1866
static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
1869
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1875
s->control[0] = value;
1876
if (!(value & (1 << 4))) /* RXE */
1877
s->rx_len = s->rx_start = 0;
1878
if (!(value & (1 << 3))) /* TXE */
1880
s->enable = value & 1; /* ITR */
1883
pxa2xx_fir_update(s);
1886
s->control[1] = value;
1889
s->control[2] = value & 0x3f;
1890
pxa2xx_fir_update(s);
1893
if (s->control[2] & (1 << 2)) /* TXP */
1897
if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
1898
qemu_chr_write(s->chr, &ch, 1);
1901
s->status[0] &= ~(value & 0x66);
1902
pxa2xx_fir_update(s);
1907
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1911
static CPUReadMemoryFunc *pxa2xx_fir_readfn[] = {
1917
static CPUWriteMemoryFunc *pxa2xx_fir_writefn[] = {
1923
static int pxa2xx_fir_is_empty(void *opaque)
1925
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1926
return (s->rx_len < 64);
1929
static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1931
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1932
if (!(s->control[0] & (1 << 4))) /* RXE */
1936
s->status[1] |= 1 << 4; /* EOF */
1937
if (s->rx_len >= 64) {
1938
s->status[1] |= 1 << 6; /* ROR */
1942
if (s->control[2] & (1 << 3)) /* RXP */
1943
s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1945
s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1948
pxa2xx_fir_update(s);
1951
static void pxa2xx_fir_event(void *opaque, int event)
1955
static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
1957
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1960
qemu_put_be32(f, s->enable);
1962
qemu_put_8s(f, &s->control[0]);
1963
qemu_put_8s(f, &s->control[1]);
1964
qemu_put_8s(f, &s->control[2]);
1965
qemu_put_8s(f, &s->status[0]);
1966
qemu_put_8s(f, &s->status[1]);
1968
qemu_put_byte(f, s->rx_len);
1969
for (i = 0; i < s->rx_len; i ++)
1970
qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]);
1973
static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
1975
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1978
s->enable = qemu_get_be32(f);
1980
qemu_get_8s(f, &s->control[0]);
1981
qemu_get_8s(f, &s->control[1]);
1982
qemu_get_8s(f, &s->control[2]);
1983
qemu_get_8s(f, &s->status[0]);
1984
qemu_get_8s(f, &s->status[1]);
1986
s->rx_len = qemu_get_byte(f);
1988
for (i = 0; i < s->rx_len; i ++)
1989
s->rx_fifo[i] = qemu_get_byte(f);
1994
static struct pxa2xx_fir_s *pxa2xx_fir_init(target_phys_addr_t base,
1995
qemu_irq irq, struct pxa2xx_dma_state_s *dma,
1996
CharDriverState *chr)
1999
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *)
2000
qemu_mallocz(sizeof(struct pxa2xx_fir_s));
2007
pxa2xx_fir_reset(s);
2009
iomemtype = cpu_register_io_memory(0, pxa2xx_fir_readfn,
2010
pxa2xx_fir_writefn, s);
2011
cpu_register_physical_memory(s->base, 0x1000, iomemtype);
2014
qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
2015
pxa2xx_fir_rx, pxa2xx_fir_event, s);
2017
register_savevm("pxa2xx_fir", 0, 0, pxa2xx_fir_save, pxa2xx_fir_load, s);
2022
static void pxa2xx_reset(void *opaque, int line, int level)
2024
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
2026
if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
2028
/* TODO: reset peripherals */
2032
/* Initialise a PXA270 integrated chip (ARM based core). */
2033
struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
2034
DisplayState *ds, const char *revision)
2036
struct pxa2xx_state_s *s;
2037
struct pxa2xx_ssp_s *ssp;
2040
s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s));
2042
if (revision && strncmp(revision, "pxa27", 5)) {
2043
fprintf(stderr, "Machine requires a PXA27x processor.\n");
2047
revision = "pxa270";
2049
s->env = cpu_init(revision);
2051
fprintf(stderr, "Unable to find CPU definition\n");
2054
register_savevm("cpu", 0, ARM_CPU_SAVE_VERSION, cpu_save, cpu_load,
2057
s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2059
/* SDRAM & Internal Memory Storage */
2060
cpu_register_physical_memory(PXA2XX_SDRAM_BASE,
2061
sdram_size, qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
2062
cpu_register_physical_memory(PXA2XX_INTERNAL_BASE,
2063
0x40000, qemu_ram_alloc(0x40000) | IO_MEM_RAM);
2065
s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2067
s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
2069
pxa27x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0],
2070
s->pic[PXA27X_PIC_OST_4_11]);
2072
s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
2074
index = drive_get_index(IF_SD, 0, 0);
2076
fprintf(stderr, "qemu: missing SecureDigital device\n");
2079
s->mmc = pxa2xx_mmci_init(0x41100000, drives_table[index].bdrv,
2080
s->pic[PXA2XX_PIC_MMC], s->dma);
2082
for (i = 0; pxa270_serial[i].io_base; i ++)
2084
serial_mm_init(pxa270_serial[i].io_base, 2,
2085
s->pic[pxa270_serial[i].irqn], serial_hds[i], 1);
2089
s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
2090
s->dma, serial_hds[i]);
2093
s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
2095
s->cm_base = 0x41300000;
2096
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2097
s->clkcfg = 0x00000009; /* Turbo mode active */
2098
iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
2099
pxa2xx_cm_writefn, s);
2100
cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
2101
register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
2103
cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2105
s->mm_base = 0x48000000;
2106
s->mm_regs[MDMRS >> 2] = 0x00020002;
2107
s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2108
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2109
iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
2110
pxa2xx_mm_writefn, s);
2111
cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
2112
register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
2114
s->pm_base = 0x40f00000;
2115
iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
2116
pxa2xx_pm_writefn, s);
2117
cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2118
register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2120
for (i = 0; pxa27x_ssp[i].io_base; i ++);
2121
s->ssp = (struct pxa2xx_ssp_s **)
2122
qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i);
2123
ssp = (struct pxa2xx_ssp_s *)
2124
qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
2125
for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2126
s->ssp[i] = &ssp[i];
2127
ssp[i].base = pxa27x_ssp[i].io_base;
2128
ssp[i].irq = s->pic[pxa27x_ssp[i].irqn];
2130
iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
2131
pxa2xx_ssp_writefn, &ssp[i]);
2132
cpu_register_physical_memory(ssp[i].base, 0x1000, iomemtype);
2133
register_savevm("pxa2xx_ssp", i, 0,
2134
pxa2xx_ssp_save, pxa2xx_ssp_load, s);
2138
usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
2141
s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2142
s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2144
s->rtc_base = 0x40900000;
2145
iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
2146
pxa2xx_rtc_writefn, s);
2147
cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
2149
register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
2151
s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
2152
s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
2154
s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
2156
s->kp = pxa27x_keypad_init(0x41500000, s->pic[PXA2XX_PIC_KEYPAD]);
2158
/* GPIO1 resets the processor */
2159
/* The handler can be overridden by board-specific code */
2160
pxa2xx_gpio_out_set(s->gpio, 1, s->reset);
2164
/* Initialise a PXA255 integrated chip (ARM based core). */
2165
struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
2168
struct pxa2xx_state_s *s;
2169
struct pxa2xx_ssp_s *ssp;
2173
s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s));
2175
s->env = cpu_init("pxa255");
2177
fprintf(stderr, "Unable to find CPU definition\n");
2180
register_savevm("cpu", 0, ARM_CPU_SAVE_VERSION, cpu_save, cpu_load,
2183
s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2185
/* SDRAM & Internal Memory Storage */
2186
cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size,
2187
qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
2188
cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, PXA2XX_INTERNAL_SIZE,
2189
qemu_ram_alloc(PXA2XX_INTERNAL_SIZE) | IO_MEM_RAM);
2191
s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2193
s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
2195
pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0]);
2197
s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85);
2199
index = drive_get_index(IF_SD, 0, 0);
2201
fprintf(stderr, "qemu: missing SecureDigital device\n");
2204
s->mmc = pxa2xx_mmci_init(0x41100000, drives_table[index].bdrv,
2205
s->pic[PXA2XX_PIC_MMC], s->dma);
2207
for (i = 0; pxa255_serial[i].io_base; i ++)
2209
serial_mm_init(pxa255_serial[i].io_base, 2,
2210
s->pic[pxa255_serial[i].irqn], serial_hds[i], 1);
2214
s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
2215
s->dma, serial_hds[i]);
2218
s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
2220
s->cm_base = 0x41300000;
2221
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2222
s->clkcfg = 0x00000009; /* Turbo mode active */
2223
iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
2224
pxa2xx_cm_writefn, s);
2225
cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
2226
register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
2228
cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2230
s->mm_base = 0x48000000;
2231
s->mm_regs[MDMRS >> 2] = 0x00020002;
2232
s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2233
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2234
iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
2235
pxa2xx_mm_writefn, s);
2236
cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
2237
register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
2239
s->pm_base = 0x40f00000;
2240
iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
2241
pxa2xx_pm_writefn, s);
2242
cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2243
register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2245
for (i = 0; pxa255_ssp[i].io_base; i ++);
2246
s->ssp = (struct pxa2xx_ssp_s **)
2247
qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i);
2248
ssp = (struct pxa2xx_ssp_s *)
2249
qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
2250
for (i = 0; pxa255_ssp[i].io_base; i ++) {
2251
s->ssp[i] = &ssp[i];
2252
ssp[i].base = pxa255_ssp[i].io_base;
2253
ssp[i].irq = s->pic[pxa255_ssp[i].irqn];
2255
iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
2256
pxa2xx_ssp_writefn, &ssp[i]);
2257
cpu_register_physical_memory(ssp[i].base, 0x1000, iomemtype);
2258
register_savevm("pxa2xx_ssp", i, 0,
2259
pxa2xx_ssp_save, pxa2xx_ssp_load, s);
2263
usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
2266
s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2267
s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2269
s->rtc_base = 0x40900000;
2270
iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
2271
pxa2xx_rtc_writefn, s);
2272
cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
2274
register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
2276
s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
2277
s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
2279
s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
2281
/* GPIO1 resets the processor */
2282
/* The handler can be overridden by board-specific code */
2283
pxa2xx_gpio_out_set(s->gpio, 1, s->reset);
added
removed
hw/pxa2xx.c
