23
23
#define TARGET_LONG_BITS 32
25
#define ELF_MACHINE EM_ARM
25
27
#include "cpu-defs.h"
27
#define EXCP_UDEF 1 /* undefined instruction */
28
#define EXCP_SWI 2 /* software interrupt */
29
#include "softfloat.h"
31
#define TARGET_HAS_ICE 1
33
#define EXCP_UDEF 1 /* undefined instruction */
34
#define EXCP_SWI 2 /* software interrupt */
35
#define EXCP_PREFETCH_ABORT 3
36
#define EXCP_DATA_ABORT 4
40
#define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
42
#define ARMV7M_EXCP_RESET 1
43
#define ARMV7M_EXCP_NMI 2
44
#define ARMV7M_EXCP_HARD 3
45
#define ARMV7M_EXCP_MEM 4
46
#define ARMV7M_EXCP_BUS 5
47
#define ARMV7M_EXCP_USAGE 6
48
#define ARMV7M_EXCP_SVC 11
49
#define ARMV7M_EXCP_DEBUG 12
50
#define ARMV7M_EXCP_PENDSV 14
51
#define ARMV7M_EXCP_SYSTICK 15
53
typedef void ARMWriteCPFunc(void *opaque, int cp_info,
54
int srcreg, int operand, uint32_t value);
55
typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
56
int dstreg, int operand);
58
#define NB_MMU_MODES 2
60
/* We currently assume float and double are IEEE single and double
61
precision respectively.
62
Doing runtime conversions is tricky because VFP registers may contain
63
integer values (eg. as the result of a FTOSI instruction).
64
s<2n> maps to the least significant half of d<n>
65
s<2n+1> maps to the most significant half of d<n>
30
68
typedef struct CPUARMState {
69
/* Regs for current mode. */
71
/* Frequently accessed CPSR bits are stored separately for efficiently.
72
This contains all the other bits. Use cpsr_{read,write} to access
74
uint32_t uncached_cpsr;
77
/* Banked registers. */
78
uint32_t banked_spsr[6];
79
uint32_t banked_r13[6];
80
uint32_t banked_r14[6];
82
/* These hold r8-r12. */
34
86
/* cpsr flag cache for faster execution */
35
87
uint32_t CF; /* 0 or 1 */
36
88
uint32_t VF; /* V is the bit 31. All other bits are undefined */
37
89
uint32_t NZF; /* N is bit 31. Z is computed from NZF */
90
uint32_t QF; /* 0 or 1 */
91
uint32_t GE; /* cpsr[19:16] */
92
int thumb; /* cprs[5]. 0 = arm mode, 1 = thumb mode. */
93
uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
95
/* System control coprocessor (cp15) */
98
uint32_t c0_cachetype;
99
uint32_t c0_c1[8]; /* Feature registers. */
100
uint32_t c0_c2[8]; /* Instruction set registers. */
101
uint32_t c1_sys; /* System control register. */
102
uint32_t c1_coproc; /* Coprocessor access register. */
103
uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
104
uint32_t c2_base0; /* MMU translation table base 0. */
105
uint32_t c2_base1; /* MMU translation table base 1. */
106
uint32_t c2_mask; /* MMU translation table base mask. */
107
uint32_t c2_data; /* MPU data cachable bits. */
108
uint32_t c2_insn; /* MPU instruction cachable bits. */
109
uint32_t c3; /* MMU domain access control register
110
MPU write buffer control. */
111
uint32_t c5_insn; /* Fault status registers. */
113
uint32_t c6_region[8]; /* MPU base/size registers. */
114
uint32_t c6_insn; /* Fault address registers. */
116
uint32_t c9_insn; /* Cache lockdown registers. */
118
uint32_t c13_fcse; /* FCSE PID. */
119
uint32_t c13_context; /* Context ID. */
120
uint32_t c13_tls1; /* User RW Thread register. */
121
uint32_t c13_tls2; /* User RO Thread register. */
122
uint32_t c13_tls3; /* Privileged Thread register. */
123
uint32_t c15_cpar; /* XScale Coprocessor Access Register */
124
uint32_t c15_ticonfig; /* TI925T configuration byte. */
125
uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
126
uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
127
uint32_t c15_threadid; /* TI debugger thread-ID. */
137
int pending_exception;
141
/* Coprocessor IO used by peripherals */
143
ARMReadCPFunc *cp_read;
144
ARMWriteCPFunc *cp_write;
148
/* Internal CPU feature flags. */
151
/* Callback for vectored interrupt controller. */
152
int (*get_irq_vector)(struct CPUARMState *);
39
155
/* exception/interrupt handling */
41
157
int exception_index;
42
158
int interrupt_request;
43
struct TranslationBlock *current_tb;
44
159
int user_mode_only;
46
/* in order to avoid passing too many arguments to the memory
47
write helpers, we store some rarely used information in the CPU
49
unsigned long mem_write_pc; /* host pc at which the memory was
51
unsigned long mem_write_vaddr; /* target virtual addr at which the
162
/* VFP coprocessor state. */
167
/* We store these fpcsr fields separately for convenience. */
171
/* Temporary variables if we don't have spare fp regs. */
172
float32 tmp0s, tmp1s;
173
float64 tmp0d, tmp1d;
174
/* scratch space when Tn are not sufficient. */
177
float_status fp_status;
179
#if defined(CONFIG_USER_ONLY)
180
struct mmon_state *mmon_entry;
185
/* iwMMXt coprocessor state. */
193
#if defined(CONFIG_USER_ONLY)
194
/* For usermode syscall translation. */
200
/* These fields after the common ones so they are preserved on reset. */
202
const char *kernel_filename;
203
const char *kernel_cmdline;
204
const char *initrd_filename;
206
target_phys_addr_t loader_start;
57
CPUARMState *cpu_arm_init(void);
209
CPUARMState *cpu_arm_init(const char *cpu_model);
58
210
int cpu_arm_exec(CPUARMState *s);
59
211
void cpu_arm_close(CPUARMState *s);
212
void do_interrupt(CPUARMState *);
213
void switch_mode(CPUARMState *, int);
214
uint32_t do_arm_semihosting(CPUARMState *env);
60
216
/* you can call this signal handler from your SIGBUS and SIGSEGV
61
217
signal handlers to inform the virtual CPU of exceptions. non zero
62
218
is returned if the signal was handled by the virtual CPU. */
64
int cpu_arm_signal_handler(int host_signum, struct siginfo *info,
219
int cpu_arm_signal_handler(int host_signum, void *pinfo,
67
void cpu_arm_dump_state(CPUARMState *env, FILE *f, int flags);
223
void cpu_unlock(void);
225
#define CPSR_M (0x1f)
226
#define CPSR_T (1 << 5)
227
#define CPSR_F (1 << 6)
228
#define CPSR_I (1 << 7)
229
#define CPSR_A (1 << 8)
230
#define CPSR_E (1 << 9)
231
#define CPSR_IT_2_7 (0xfc00)
232
#define CPSR_GE (0xf << 16)
233
#define CPSR_RESERVED (0xf << 20)
234
#define CPSR_J (1 << 24)
235
#define CPSR_IT_0_1 (3 << 25)
236
#define CPSR_Q (1 << 27)
237
#define CPSR_V (1 << 28)
238
#define CPSR_C (1 << 29)
239
#define CPSR_Z (1 << 30)
240
#define CPSR_N (1 << 31)
241
#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
243
#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
244
#define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
245
/* Bits writable in user mode. */
246
#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
247
/* Execution state bits. MRS read as zero, MSR writes ignored. */
248
#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
250
/* Return the current CPSR value. */
251
uint32_t cpsr_read(CPUARMState *env);
252
/* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
253
void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
255
/* Return the current xPSR value. */
256
static inline uint32_t xpsr_read(CPUARMState *env)
259
ZF = (env->NZF == 0);
260
return (env->NZF & 0x80000000) | (ZF << 30)
261
| (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
262
| (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
263
| ((env->condexec_bits & 0xfc) << 8)
264
| env->v7m.exception;
267
/* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
268
static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
270
/* NOTE: N = 1 and Z = 1 cannot be stored currently */
271
if (mask & CPSR_NZCV) {
272
env->NZF = (val & 0xc0000000) ^ 0x40000000;
273
env->CF = (val >> 29) & 1;
274
env->VF = (val << 3) & 0x80000000;
277
env->QF = ((val & CPSR_Q) != 0);
278
if (mask & (1 << 24))
279
env->thumb = ((val & (1 << 24)) != 0);
280
if (mask & CPSR_IT_0_1) {
281
env->condexec_bits &= ~3;
282
env->condexec_bits |= (val >> 25) & 3;
284
if (mask & CPSR_IT_2_7) {
285
env->condexec_bits &= 3;
286
env->condexec_bits |= (val >> 8) & 0xfc;
289
env->v7m.exception = val & 0x1ff;
294
ARM_CPU_MODE_USR = 0x10,
295
ARM_CPU_MODE_FIQ = 0x11,
296
ARM_CPU_MODE_IRQ = 0x12,
297
ARM_CPU_MODE_SVC = 0x13,
298
ARM_CPU_MODE_ABT = 0x17,
299
ARM_CPU_MODE_UND = 0x1b,
300
ARM_CPU_MODE_SYS = 0x1f
303
/* VFP system registers. */
304
#define ARM_VFP_FPSID 0
305
#define ARM_VFP_FPSCR 1
306
#define ARM_VFP_MVFR1 6
307
#define ARM_VFP_MVFR0 7
308
#define ARM_VFP_FPEXC 8
309
#define ARM_VFP_FPINST 9
310
#define ARM_VFP_FPINST2 10
312
/* iwMMXt coprocessor control registers. */
313
#define ARM_IWMMXT_wCID 0
314
#define ARM_IWMMXT_wCon 1
315
#define ARM_IWMMXT_wCSSF 2
316
#define ARM_IWMMXT_wCASF 3
317
#define ARM_IWMMXT_wCGR0 8
318
#define ARM_IWMMXT_wCGR1 9
319
#define ARM_IWMMXT_wCGR2 10
320
#define ARM_IWMMXT_wCGR3 11
324
ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
325
ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
326
ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
331
ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
335
ARM_FEATURE_M, /* Microcontroller profile. */
336
ARM_FEATURE_OMAPCP /* OMAP specific CP15 ops handling. */
339
static inline int arm_feature(CPUARMState *env, int feature)
341
return (env->features & (1u << feature)) != 0;
344
void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
346
/* Interface between CPU and Interrupt controller. */
347
void armv7m_nvic_set_pending(void *opaque, int irq);
348
int armv7m_nvic_acknowledge_irq(void *opaque);
349
void armv7m_nvic_complete_irq(void *opaque, int irq);
351
void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
352
ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
355
/* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
356
Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
357
conventional cores (ie. Application or Realtime profile). */
359
#define IS_M(env) arm_feature(env, ARM_FEATURE_M)
360
#define ARM_CPUID(env) (env->cp15.c0_cpuid)
362
#define ARM_CPUID_ARM1026 0x4106a262
363
#define ARM_CPUID_ARM926 0x41069265
364
#define ARM_CPUID_ARM946 0x41059461
365
#define ARM_CPUID_TI915T 0x54029152
366
#define ARM_CPUID_TI925T 0x54029252
367
#define ARM_CPUID_PXA250 0x69052100
368
#define ARM_CPUID_PXA255 0x69052d00
369
#define ARM_CPUID_PXA260 0x69052903
370
#define ARM_CPUID_PXA261 0x69052d05
371
#define ARM_CPUID_PXA262 0x69052d06
372
#define ARM_CPUID_PXA270 0x69054110
373
#define ARM_CPUID_PXA270_A0 0x69054110
374
#define ARM_CPUID_PXA270_A1 0x69054111
375
#define ARM_CPUID_PXA270_B0 0x69054112
376
#define ARM_CPUID_PXA270_B1 0x69054113
377
#define ARM_CPUID_PXA270_C0 0x69054114
378
#define ARM_CPUID_PXA270_C5 0x69054117
379
#define ARM_CPUID_ARM1136 0x4117b363
380
#define ARM_CPUID_ARM11MPCORE 0x410fb022
381
#define ARM_CPUID_CORTEXA8 0x410fc080
382
#define ARM_CPUID_CORTEXM3 0x410fc231
383
#define ARM_CPUID_ANY 0xffffffff
385
#if defined(CONFIG_USER_ONLY)
69
386
#define TARGET_PAGE_BITS 12
388
/* The ARM MMU allows 1k pages. */
389
/* ??? Linux doesn't actually use these, and they're deprecated in recent
390
architecture revisions. Maybe a configure option to disable them. */
391
#define TARGET_PAGE_BITS 10
394
#define CPUState CPUARMState
395
#define cpu_init cpu_arm_init
396
#define cpu_exec cpu_arm_exec
397
#define cpu_gen_code cpu_arm_gen_code
398
#define cpu_signal_handler cpu_arm_signal_handler
399
#define cpu_list arm_cpu_list
401
#define ARM_CPU_SAVE_VERSION 1
403
/* MMU modes definitions */
404
#define MMU_MODE0_SUFFIX _kernel
405
#define MMU_MODE1_SUFFIX _user
406
#define MMU_USER_IDX 1
407
static inline int cpu_mmu_index (CPUState *env)
409
return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
70
412
#include "cpu-all.h"
added
removed
target-arm/cpu.h
