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* Arm PrimeCell PL061 General Purpose IO with additional
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* Luminary Micro Stellaris bits.
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* Copyright (c) 2007 CodeSourcery.
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* Written by Paul Brook
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* This code is licenced under the GPL.
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#include "primecell.h"
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//#define DEBUG_PL061 1
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#define DPRINTF(fmt, args...) \
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do { printf("pl061: " fmt , ##args); } while (0)
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#define BADF(fmt, args...) \
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do { fprintf(stderr, "pl061: error: " fmt , ##args); exit(1);} while (0)
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#define DPRINTF(fmt, args...) do {} while(0)
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#define BADF(fmt, args...) \
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do { fprintf(stderr, "pl061: error: " fmt , ##args);} while (0)
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static const uint8_t pl061_id[12] =
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{ 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
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static void pl061_update(pl061_state *s)
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/* Outputs float high. */
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/* FIXME: This is board dependent. */
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out = (s->data & s->dir) | ~s->dir;
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changed = s->old_data ^ out;
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for (i = 0; i < 8; i++) {
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if ((changed & mask) && s->out) {
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DPRINTF("Set output %d = %d\n", i, (out & mask) != 0);
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qemu_set_irq(s->out[i], (out & mask) != 0);
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/* FIXME: Implement input interrupts. */
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static uint32_t pl061_read(void *opaque, target_phys_addr_t offset)
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pl061_state *s = (pl061_state *)opaque;
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if (offset >= 0xfd0 && offset < 0x1000) {
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return pl061_id[(offset - 0xfd0) >> 2];
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return s->data & (offset >> 2);
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case 0x400: /* Direction */
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case 0x404: /* Interrupt sense */
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case 0x408: /* Interrupt both edges */
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case 0x40c: /* Interupt event */
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case 0x410: /* Interrupt mask */
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case 0x414: /* Raw interrupt status */
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case 0x418: /* Masked interrupt status */
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return s->istate | s->im;
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case 0x420: /* Alternate function select */
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case 0x500: /* 2mA drive */
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case 0x504: /* 4mA drive */
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case 0x508: /* 8mA drive */
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case 0x50c: /* Open drain */
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case 0x510: /* Pull-up */
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case 0x514: /* Pull-down */
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case 0x518: /* Slew rate control */
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case 0x51c: /* Digital enable */
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case 0x520: /* Lock */
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case 0x524: /* Commit */
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cpu_abort (cpu_single_env, "pl061_read: Bad offset %x\n",
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static void pl061_write(void *opaque, target_phys_addr_t offset,
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pl061_state *s = (pl061_state *)opaque;
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if (offset < 0x400) {
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mask = (offset >> 2) & s->dir;
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s->data = (s->data & ~mask) | (value & mask);
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case 0x400: /* Direction */
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case 0x404: /* Interrupt sense */
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case 0x408: /* Interrupt both edges */
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case 0x40c: /* Interupt event */
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case 0x410: /* Interrupt mask */
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case 0x41c: /* Interrupt clear */
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case 0x420: /* Alternate function select */
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s->afsel = (s->afsel & ~mask) | (value & mask);
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case 0x500: /* 2mA drive */
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case 0x504: /* 4mA drive */
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case 0x508: /* 8mA drive */
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case 0x50c: /* Open drain */
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case 0x510: /* Pull-up */
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case 0x514: /* Pull-down */
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case 0x518: /* Slew rate control */
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case 0x51c: /* Digital enable */
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case 0x520: /* Lock */
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s->locked = (value != 0xacce551);
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case 0x524: /* Commit */
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cpu_abort (cpu_single_env, "pl061_write: Bad offset %x\n",
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static void pl061_reset(pl061_state *s)
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static void pl061_set_irq(void * opaque, int irq, int level)
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pl061_state *s = (pl061_state *)opaque;
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if ((s->dir & mask) == 0) {
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static CPUReadMemoryFunc *pl061_readfn[] = {
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static CPUWriteMemoryFunc *pl061_writefn[] = {
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/* Returns an array of inputs. */
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qemu_irq *pl061_init(uint32_t base, qemu_irq irq, qemu_irq **out)
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s = (pl061_state *)qemu_mallocz(sizeof(pl061_state));
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iomemtype = cpu_register_io_memory(0, pl061_readfn,
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cpu_register_physical_memory(base, 0x00001000, iomemtype);
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/* ??? Save/restore. */
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return qemu_allocate_irqs(pl061_set_irq, s, 8);