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// BLF LT1 driver layout using the Attiny1616
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// Copyright (C) 2021-2023 (gchart), Selene ToyKeeper
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// SPDX-License-Identifier: GPL-3.0-or-later
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* PWM cool: PB0 (TCA0 WO0)
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* PWM warm: PB1 (TCA0 WO1)
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#define HWDEF_C_FILE hwdef-blf-lt1-t1616.c
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// allow using aux LEDs as extra channel modes
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// * 2. both channels, tied together, max "200%" power
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// * 3. both channels, manual blend, max "100%" power
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// * 4. both channels, auto blend, reversible
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#define NUM_CHANNEL_MODES 6
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enum channel_modes_e {
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// right-most bit first, modes are in fedcba9876543210 order
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#define CHANNEL_MODES_ENABLED 0b00011000
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#define USE_CHANNEL_MODE_ARGS
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// _, _, _, 128=middle CCT, 0=warm-to-cool
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#define CHANNEL_MODE_ARGS 0,0,0,128,0,0
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// can use some of the common handlers
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#define USE_CALC_2CH_BLEND
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#define PWM_CHANNELS 1 // old, remove this
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#define PWM_BITS 16 // 0 to 32640 (0 to 255 PWM + 0 to 127 DSM) at constant kHz
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#define PWM_GET PWM_GET16
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#define PWM_DATATYPE uint16_t
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#define PWM_DATATYPE2 uint32_t // only needs 32-bit if ramp values go over 255
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#define PWM1_DATATYPE uint16_t // 15-bit PWM+DSM ramp
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// PWM parameters of both channels are tied together because they share a counter
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#define PWM_TOP TCA0.SINGLE.PERBUF // holds the TOP value for for variable-resolution PWM
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#define PWM_TOP_INIT 255
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#define PWM_CNT TCA0.SINGLE.CNT // for resetting phase after each TOP adjustment
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// (max is (255 << 7), because it's 8-bit PWM plus 7 bits of DSM)
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#define DSM_TOP (255<<7) // 15-bit resolution leaves 1 bit for carry
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// timer interrupt for DSM
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#define DSM_vect TCA0_OVF_vect
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#define DSM_INTCTRL TCA0.SINGLE.INTCTRL
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#define DSM_INTFLAGS TCA0.SINGLE.INTFLAGS
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#define DSM_OVF_bm TCA_SINGLE_OVF_bm
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#define DELAY_FACTOR 90 // less time in delay() because more time spent in interrupts
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uint8_t ch1_pwm, ch1_dsm;
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#define CH1_PWM TCA0.SINGLE.CMP1BUF // CMP1 is the output compare register for PB1
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uint8_t ch2_pwm, ch2_dsm;
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#define CH2_PWM TCA0.SINGLE.CMP0BUF // CMP0 is the output compare register for PB0
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#define AUXLED_PIN PIN5_bp
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#define AUXLED_PORT PORTB
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#define SWITCH_PIN PIN5_bp
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#define SWITCH_PORT VPORTA.IN
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#define SWITCH_ISC_REG PORTA.PIN2CTRL
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#define SWITCH_VECT PORTA_PORT_vect
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#define SWITCH_INTFLG VPORTA.INTFLAGS
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// average drop across diode on this hardware
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#ifndef VOLTAGE_FUDGE_FACTOR
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#define VOLTAGE_FUDGE_FACTOR 7 // add 0.35V
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inline void hwdef_setup() {
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// set up the system clock to run at 10 MHz instead of the default 3.33 MHz
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_PROTECTED_WRITE( CLKCTRL.MCLKCTRLB,
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CLKCTRL_PDIV_2X_gc | CLKCTRL_PEN_bm );
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VPORTB.DIR = PIN0_bm // cool white
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| PIN1_bm // warm white
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// | PIN2_bm // for testing on LT1S Pro, disable red channel
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| PIN5_bm; // aux LED
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// enable pullups on the unused pins to reduce power
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PORTA.PIN0CTRL = PORT_PULLUPEN_bm;
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PORTA.PIN1CTRL = PORT_PULLUPEN_bm;
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PORTA.PIN2CTRL = PORT_PULLUPEN_bm;
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PORTA.PIN3CTRL = PORT_PULLUPEN_bm;
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PORTA.PIN4CTRL = PORT_PULLUPEN_bm;
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PORTA.PIN5CTRL = PORT_PULLUPEN_bm | PORT_ISC_BOTHEDGES_gc; // eSwitch
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PORTA.PIN6CTRL = PORT_PULLUPEN_bm;
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PORTA.PIN7CTRL = PORT_PULLUPEN_bm;
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//PORTB.PIN0CTRL = PORT_PULLUPEN_bm; // cold tint channel
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//PORTB.PIN1CTRL = PORT_PULLUPEN_bm; // warm tint channel
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PORTB.PIN2CTRL = PORT_PULLUPEN_bm; // comment out for testing on LT1S Pro
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PORTB.PIN3CTRL = PORT_PULLUPEN_bm;
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PORTB.PIN4CTRL = PORT_PULLUPEN_bm;
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//PORTB.PIN5CTRL = PORT_PULLUPEN_bm; // Aux LED
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PORTC.PIN0CTRL = PORT_PULLUPEN_bm;
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PORTC.PIN1CTRL = PORT_PULLUPEN_bm;
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PORTC.PIN2CTRL = PORT_PULLUPEN_bm;
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PORTC.PIN3CTRL = PORT_PULLUPEN_bm;
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// https://ww1.microchip.com/downloads/en/DeviceDoc/ATtiny1614-16-17-DataSheet-DS40002204A.pdf
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// PB0 is TCA0:WO0, use TCA_SINGLE_CMP0EN_bm
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// PB1 is TCA0:WO1, use TCA_SINGLE_CMP1EN_bm
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// For Fast (Single Slope) PWM use TCA_SINGLE_WGMODE_SINGLESLOPE_gc
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// For Phase Correct (Dual Slope) PWM use TCA_SINGLE_WGMODE_DSBOTTOM_gc
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// TODO: add references to MCU documentation
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TCA0.SINGLE.CTRLB = TCA_SINGLE_CMP0EN_bm
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| TCA_SINGLE_CMP1EN_bm
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| TCA_SINGLE_WGMODE_DSBOTTOM_gc;
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TCA0.SINGLE.CTRLA = TCA_SINGLE_CLKSEL_DIV1_gc
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| TCA_SINGLE_ENABLE_bm;
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PWM_TOP = PWM_TOP_INIT;
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// set up interrupt for delta-sigma modulation
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// (moved to hwdef.c functions so it can be enabled/disabled based on ramp level)
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//DSM_INTCTRL |= DSM_OVF_bm; // interrupt once for each timer cycle
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#define LAYOUT_DEFINED