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// gChart's custom FET+1 driver layout
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// Copyright (C) 2020-2023 gchart, Selene ToyKeeper
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// SPDX-License-Identifier: GPL-3.0-or-later
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* PB0 - PWM for FET (TCA - WO0)
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* PB1 - PWM for 7135 (TCA - WO1)
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* PB2 - Switch pin, internal pullup
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* PB3 - Aux LED with 4700 Ohm series resistor
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* Read voltage from VCC pin, has diode with ~0.4v drop
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// nearly all t1616-based FET+1 drivers work pretty much the same
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// (this one has single-color aux like the TS10)
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#define HWDEF_C_FILE hwdef-wurkkos-ts10.c
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// allow using aux LEDs as extra channel modes
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// * 0. FET+7135 stacked
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#define NUM_CHANNEL_MODES 2
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#define DEFAULT_CHANNEL_MODE CM_MAIN
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// right-most bit first, modes are in fedcba9876543210 order
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#define CHANNEL_MODES_ENABLED 0b00000001
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#define PWM_CHANNELS 2 // old, remove this
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#define PWM_BITS 16 // dynamic 16-bit, but never goes over 255
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#define PWM_GET PWM_GET8
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#define PWM_DATATYPE uint16_t // is used for PWM_TOPS (which goes way over 255)
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#define PWM_DATATYPE2 uint16_t // only needs 32-bit if ramp values go over 255
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#define PWM1_DATATYPE uint8_t // 1x7135 ramp
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#define PWM2_DATATYPE uint8_t // DD FET ramp
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// PWM parameters of both channels are tied together because they share a counter
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#define PWM_TOP TCA0.SINGLE.PERBUF // holds the TOP value for for variable-resolution PWM
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#define PWM_TOP_INIT 255 // highest value used in top half of ramp
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// not necessary when double-buffered "BUF" registers are used
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#define PWM_CNT TCA0.SINGLE.CNT // for resetting phase after each TOP adjustment
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#define CH1_PWM TCA0.SINGLE.CMP1BUF // CMP1 is the output compare register for PB1
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#define CH2_PWM TCA0.SINGLE.CMP0BUF // CMP0 is the output compare register for PB0
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#define SWITCH_PIN PIN2_bp
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#define SWITCH_PORT VPORTB.IN
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#define SWITCH_ISC_REG PORTB.PIN2CTRL
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#define SWITCH_VECT PORTB_PORT_vect
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#define SWITCH_INTFLG VPORTB.INTFLAGS
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// average drop across diode on this hardware
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#ifndef VOLTAGE_FUDGE_FACTOR
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#define VOLTAGE_FUDGE_FACTOR 8 // 4 = add 0.20V
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#define AUXLED_PIN PIN3_bp
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#define AUXLED_PORT PORTB
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inline void hwdef_setup() {
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// set up the system clock to run at 10 MHz instead of the default 3.33 MHz
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_PROTECTED_WRITE( CLKCTRL.MCLKCTRLB,
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CLKCTRL_PDIV_2X_gc | CLKCTRL_PEN_bm );
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//VPORTA.DIR = 0b00000010;
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VPORTB.DIR = PIN0_bm // DD FET
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//VPORTC.DIR = 0b00000000;
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// enable pullups on the input pins to reduce power
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PORTA.PIN0CTRL = PORT_PULLUPEN_bm;
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PORTA.PIN1CTRL = PORT_PULLUPEN_bm;
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PORTA.PIN2CTRL = PORT_PULLUPEN_bm;
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PORTA.PIN3CTRL = PORT_PULLUPEN_bm;
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PORTA.PIN4CTRL = PORT_PULLUPEN_bm;
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PORTA.PIN5CTRL = PORT_PULLUPEN_bm;
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PORTA.PIN6CTRL = PORT_PULLUPEN_bm;
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PORTA.PIN7CTRL = PORT_PULLUPEN_bm;
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//PORTB.PIN0CTRL = PORT_PULLUPEN_bm; // FET channel
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//PORTB.PIN1CTRL = PORT_PULLUPEN_bm; // 7135 channel
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PORTB.PIN2CTRL = PORT_PULLUPEN_bm | PORT_ISC_BOTHEDGES_gc; // switch
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//PORTB.PIN3CTRL = PORT_PULLUPEN_bm; // Aux LED
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PORTB.PIN4CTRL = PORT_PULLUPEN_bm;
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PORTB.PIN5CTRL = PORT_PULLUPEN_bm;
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PORTC.PIN0CTRL = PORT_PULLUPEN_bm;
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PORTC.PIN1CTRL = PORT_PULLUPEN_bm;
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PORTC.PIN2CTRL = PORT_PULLUPEN_bm;
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PORTC.PIN3CTRL = PORT_PULLUPEN_bm;
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// https://ww1.microchip.com/downloads/en/DeviceDoc/ATtiny1614-16-17-DataSheet-DS40002204A.pdf
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// PB0 is TCA0:WO0, use TCA_SINGLE_CMP0EN_bm
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// PB1 is TCA0:WO1, use TCA_SINGLE_CMP1EN_bm
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// PB2 is TCA0:WO2, use TCA_SINGLE_CMP2EN_bm
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// For Fast (Single Slope) PWM use TCA_SINGLE_WGMODE_SINGLESLOPE_gc
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// For Phase Correct (Dual Slope) PWM use TCA_SINGLE_WGMODE_DSBOTTOM_gc
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// See the manual for other pins, clocks, configs, portmux, etc
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TCA0.SINGLE.CTRLB = TCA_SINGLE_CMP0EN_bm
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| TCA_SINGLE_CMP1EN_bm
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| TCA_SINGLE_WGMODE_DSBOTTOM_gc;
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TCA0.SINGLE.CTRLA = TCA_SINGLE_CLKSEL_DIV1_gc
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| TCA_SINGLE_ENABLE_bm;
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PWM_TOP = PWM_TOP_INIT;
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#define LAYOUT_DEFINED