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$Id: cgcpu.pas,v 1.27 2004/05/20 21:54:33 florian Exp $
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Copyright (c) 1998-2002 by the FPC team
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This unit implements the code generator for the 680x0
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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aasmbase,aasmtai,aasmcpu,
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cpubase,cpuinfo,cpupara,
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node,symconst,symtype,
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procedure init_register_allocators;override;
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procedure done_register_allocators;override;
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procedure a_call_name(list : taasmoutput;const s : string);override;
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procedure a_call_reg(list : taasmoutput;reg : tregister);override;
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procedure a_load_const_reg(list : taasmoutput;size : tcgsize;a : aword;register : tregister);override;
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procedure a_load_reg_ref(list : taasmoutput;fromsize,tosize : tcgsize;register : tregister;const ref : treference);override;
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procedure a_load_reg_reg(list : taasmoutput;fromsize,tosize : tcgsize;reg1,reg2 : tregister);override;
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procedure a_load_ref_reg(list : taasmoutput;fromsize,tosize : tcgsize;const ref : treference;register : tregister);override;
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procedure a_loadaddr_ref_reg(list : taasmoutput;const ref : treference;r : tregister);override;
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procedure a_loadfpu_reg_reg(list: taasmoutput; size: tcgsize; reg1, reg2: tregister); override;
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procedure a_loadfpu_ref_reg(list: taasmoutput; size: tcgsize; const ref: treference; reg: tregister); override;
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procedure a_loadfpu_reg_ref(list: taasmoutput; size: tcgsize; reg: tregister; const ref: treference); override;
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procedure a_loadmm_reg_reg(list: taasmoutput;fromsize,tosize : tcgsize; reg1, reg2: tregister;shuffle : pmmshuffle); override;
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procedure a_loadmm_ref_reg(list: taasmoutput;fromsize,tosize : tcgsize; const ref: treference; reg: tregister;shuffle : pmmshuffle); override;
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procedure a_loadmm_reg_ref(list: taasmoutput;fromsize,tosize : tcgsize; reg: tregister; const ref: treference;shuffle : pmmshuffle); override;
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procedure a_parammm_reg(list: taasmoutput; size: tcgsize; reg: tregister;const locpara : tparalocation;shuffle : pmmshuffle); override;
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procedure a_op_const_reg(list : taasmoutput; Op: TOpCG; size: tcgsize; a: AWord; reg: TRegister); override;
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procedure a_op_reg_reg(list : taasmoutput; Op: TOpCG; size: TCGSize; reg1, reg2: TRegister); override;
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procedure a_cmp_const_reg_label(list : taasmoutput;size : tcgsize;cmp_op : topcmp;a : aword;reg : tregister;
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l : tasmlabel);override;
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procedure a_cmp_reg_reg_label(list : taasmoutput;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel); override;
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procedure a_jmp_always(list : taasmoutput;l: tasmlabel); override;
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procedure a_jmp_flags(list : taasmoutput;const f : TResFlags;l: tasmlabel); override;
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procedure g_flags2reg(list: taasmoutput; size: TCgSize; const f: tresflags; reg: TRegister); override;
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procedure g_concatcopy(list : taasmoutput;const source,dest : treference;len : aword;delsource,loadref : boolean);override;
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{ generates overflow checking code for a node }
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procedure g_overflowcheck(list: taasmoutput; const l:tlocation; def:tdef); override;
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procedure g_copyvaluepara_openarray(list : taasmoutput;const ref, lenref:treference;elesize:aword); override;
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procedure g_stackframe_entry(list : taasmoutput;localsize : longint);override;
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procedure g_restore_frame_pointer(list : taasmoutput);override;
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procedure g_return_from_proc(list : taasmoutput;parasize : aword);override;
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procedure g_restore_standard_registers(list:Taasmoutput);override;
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procedure g_save_standard_registers(list:Taasmoutput);override;
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procedure g_save_all_registers(list : taasmoutput);override;
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procedure g_restore_all_registers(list : taasmoutput;const funcretparaloc:tparalocation);override;
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function fixref(list: taasmoutput; var ref: treference): boolean;
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{ # Sign or zero extend the register to a full 32-bit value.
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The new value is left in the same register.
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procedure sign_extend(list: taasmoutput;_oldsize : tcgsize; reg: tregister);
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procedure a_jmp_cond(list : taasmoutput;cond : TOpCmp;l: tasmlabel);
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tcg64f68k = class(tcg64f32)
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procedure a_op64_reg_reg(list : taasmoutput;op:TOpCG;regsrc,regdst : tregister64);override;
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procedure a_op64_const_reg(list : taasmoutput;op:TOpCG;value : qword;reg : tregister64);override;
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{ This function returns true if the reference+offset is valid.
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Otherwise extra code must be generated to solve the reference.
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On the m68k, this verifies that the reference is valid
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(e.g : if index register is used, then the max displacement
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is 256 bytes, if only base is used, then max displacement
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function isvalidrefoffset(const ref: treference): boolean;
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TCGSize2OpSize: Array[tcgsize] of topsize =
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(S_NO,S_B,S_W,S_L,S_L,S_NO,S_B,S_W,S_L,S_L,S_NO,
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S_FS,S_FD,S_FX,S_NO,S_NO,
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S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO);
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globtype,globals,verbose,systems,cutils,
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symdef,symsym,defutil,paramgr,procinfo,
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{ opcode table lookup }
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topcg2tasmop: Array[topcg] of tasmop =
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TOpCmp2AsmCond: Array[topcmp] of TAsmCond =
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function isvalidrefoffset(const ref: treference): boolean;
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isvalidrefoffset := true;
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if ref.index <> NR_NO then
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if ref.base <> NR_NO then
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internalerror(20020814);
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if (ref.offset < low(shortint)) or (ref.offset > high(shortint)) then
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isvalidrefoffset := false
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if (ref.offset < low(smallint)) or (ref.offset > high(smallint)) then
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isvalidrefoffset := false;
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{****************************************************************************}
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{****************************************************************************}
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procedure tcg68k.init_register_allocators;
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inherited init_register_allocators;
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rg[R_INTREGISTER]:=trgcpu.create(R_INTREGISTER,R_SUBWHOLE,
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[RS_D0,RS_D1,RS_D2,RS_D3,RS_D4,RS_D5,RS_D6,RS_D7],
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rg[R_ADDRESSREGISTER]:=trgcpu.create(R_ADDRESSREGISTER,R_SUBWHOLE,
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[RS_A0,RS_A1,RS_A2,RS_A3,RS_A4,RS_A5,RS_A6],
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first_addr_imreg,[]);
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rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBNONE,
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[RS_FP0,RS_FP1,RS_FP2,RS_FP3,RS_FP4,RS_FP5,RS_FP6,RS_FP7],
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procedure tcg68k.done_register_allocators;
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rg[R_INTREGISTER].free;
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rg[R_FPUREGISTER].free;
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rg[R_ADDRESSREGISTER].free;
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inherited done_register_allocators;
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function tcg68k.fixref(list: taasmoutput; var ref: treference): boolean;
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{ The Coldfire and MC68020+ have extended
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addressing capabilities with a 32-bit
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if (aktoptprocessor<>MC68000) then
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if (ref.base<>NR_NO) then
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if (ref.index <> NR_NO) and assigned(ref.symbol) then
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internalerror(20020814);
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if ref.index <> NR_NO then
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{ base + reg + offset }
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if (ref.offset < low(shortint)) or (ref.offset > high(shortint)) then
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list.concat(taicpu.op_const_reg(A_ADD,S_L,ref.offset,ref.base));
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if (ref.offset < low(smallint)) or (ref.offset > high(smallint)) then
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list.concat(taicpu.op_const_reg(A_ADD,S_L,ref.offset,ref.base));
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procedure tcg68k.a_call_name(list : taasmoutput;const s : string);
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list.concat(taicpu.op_sym(A_JSR,S_NO,objectlibrary.newasmsymbol(s,AB_EXTERNAL,AT_FUNCTION)));
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procedure tcg68k.a_call_reg(list : taasmoutput;reg : tregister);
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reference_reset_base(href, reg, 0);
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//!!! a_call_ref(list,href);
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procedure tcg68k.a_load_const_reg(list : taasmoutput;size : tcgsize;a : aword;register : tregister);
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if getregtype(register)=R_ADDRESSREGISTER then
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list.concat(taicpu.op_const_reg(A_MOVE,S_L,longint(a),register))
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list.concat(taicpu.op_reg(A_CLR,S_L,register))
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if (longint(a) >= low(shortint)) and (longint(a) <= high(shortint)) then
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list.concat(taicpu.op_const_reg(A_MOVEQ,S_L,longint(a),register))
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list.concat(taicpu.op_const_reg(A_MOVE,S_L,longint(a),register))
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procedure tcg68k.a_load_reg_ref(list : taasmoutput;fromsize,tosize : tcgsize;register : tregister;const ref : treference);
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{ move to destination reference }
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list.concat(taicpu.op_reg_ref(A_MOVE,TCGSize2OpSize[fromsize],register,href));
286
procedure tcg68k.a_load_reg_reg(list : taasmoutput;fromsize,tosize : tcgsize;reg1,reg2 : tregister);
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{ move to destination register }
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list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg1,reg2));
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{ zero/sign extend register to 32-bit }
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sign_extend(list, fromsize, reg2);
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procedure tcg68k.a_load_ref_reg(list : taasmoutput;fromsize,tosize : tcgsize;const ref : treference;register : tregister);
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list.concat(taicpu.op_ref_reg(A_MOVE,TCGSize2OpSize[fromsize],href,register));
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{ extend the value in the register }
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sign_extend(list, tosize, register);
307
procedure tcg68k.a_loadaddr_ref_reg(list : taasmoutput;const ref : treference;r : tregister);
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if getregtype(r)=R_ADDRESSREGISTER then
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internalerror(2002072901);
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list.concat(taicpu.op_ref_reg(A_LEA,S_L,href,r));
321
procedure tcg68k.a_loadfpu_reg_reg(list: taasmoutput; size: tcgsize; reg1, reg2: tregister);
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{ in emulation mode, only 32-bit single is supported }
324
if cs_fp_emulation in aktmoduleswitches then
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list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg1,reg2))
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list.concat(taicpu.op_reg_reg(A_FMOVE,S_FD,reg1,reg2));
331
procedure tcg68k.a_loadfpu_ref_reg(list: taasmoutput; size: tcgsize; const ref: treference; reg: tregister);
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opsize := tcgsize2opsize[size];
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{ extended is not supported, since it is not available on Coldfire }
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if opsize = S_FX then
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internalerror(20020729);
342
{ in emulation mode, only 32-bit single is supported }
343
if cs_fp_emulation in aktmoduleswitches then
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list.concat(taicpu.op_ref_reg(A_MOVE,S_L,href,reg))
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list.concat(taicpu.op_ref_reg(A_FMOVE,opsize,href,reg));
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procedure tcg68k.a_loadfpu_reg_ref(list: taasmoutput; size: tcgsize; reg: tregister; const ref: treference);
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opsize := tcgsize2opsize[size];
354
{ extended is not supported, since it is not available on Coldfire }
355
if opsize = S_FX then
356
internalerror(20020729);
357
{ in emulation mode, only 32-bit single is supported }
358
if cs_fp_emulation in aktmoduleswitches then
359
list.concat(taicpu.op_reg_ref(A_MOVE,S_L,reg, ref))
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list.concat(taicpu.op_reg_ref(A_FMOVE,opsize,reg, ref));
365
procedure tcg68k.a_loadmm_reg_reg(list: taasmoutput;fromsize,tosize : tcgsize; reg1, reg2: tregister;shuffle : pmmshuffle);
367
internalerror(20020729);
371
procedure tcg68k.a_loadmm_ref_reg(list: taasmoutput;fromsize,tosize : tcgsize; const ref: treference; reg: tregister;shuffle : pmmshuffle);
373
internalerror(20020729);
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procedure tcg68k.a_loadmm_reg_ref(list: taasmoutput;fromsize,tosize : tcgsize; reg: tregister; const ref: treference;shuffle : pmmshuffle);
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internalerror(20020729);
383
procedure tcg68k.a_parammm_reg(list: taasmoutput; size: tcgsize; reg: tregister;const locpara : tparalocation;shuffle : pmmshuffle);
385
internalerror(20020729);
389
procedure tcg68k.a_op_const_reg(list : taasmoutput; Op: TOpCG; size: tcgsize; a: AWord; reg: TRegister);
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scratch_reg : tregister;
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scratch_reg2: tregister;
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{ need to emit opcode? }
397
if optimize_op_const_reg(list, op, a, reg) then
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opcode := topcg2tasmop[op];
403
if (a >= 1) and (a <= 8) then
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list.concat(taicpu.op_const_reg(A_ADDQ,S_L,a, reg))
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{ all others, including coldfire }
408
list.concat(taicpu.op_const_reg(A_ADD,S_L,a, reg));
414
list.concat(taicpu.op_const_reg(topcg2tasmop[op],S_L,longint(a), reg));
418
internalerror(20020816);
422
internalerror(20020816);
426
if aktoptprocessor = MC68000 then
430
getexplicitregister(list,NR_D0);
431
getexplicitregister(list,NR_D1);
432
list.concat(taicpu.op_const_reg(A_MOVE,S_L,a, r));
433
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg, r2));
434
cg.a_call_name(list,'FPC_MUL_LONGINT');
435
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,r, reg));
436
ungetregister(list,r);
437
ungetregister(list,r2);
441
if (isaddressregister(reg)) then
443
scratch_reg := cg.getintregister(list,OS_INT);
444
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg, scratch_reg));
445
list.concat(taicpu.op_const_reg(A_MULS,S_L,a,scratch_reg));
446
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,scratch_reg,reg));
447
cg.ungetregister(list,scratch_reg);
450
list.concat(taicpu.op_const_reg(A_MULS,S_L,a,reg));
455
if aktoptprocessor = MC68000 then
459
getexplicitregister(list,NR_D0);
460
getexplicitregister(list,NR_D1);
461
list.concat(taicpu.op_const_reg(A_MOVE,S_L,a, r));
462
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg, r2));
463
cg.a_call_name(list,'FPC_MUL_LONGWORD');
464
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,r, reg));
465
ungetregister(list,r);
466
ungetregister(list,r2);
470
if (isaddressregister(reg)) then
472
scratch_reg := cg.getintregister(list,OS_INT);
473
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg, scratch_reg));
474
list.concat(taicpu.op_const_reg(A_MULU,S_L,a,scratch_reg));
475
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,scratch_reg,reg));
476
cg.ungetregister(list,scratch_reg);
479
list.concat(taicpu.op_const_reg(A_MULU,S_L,a,reg));
486
if (a >= 1) and (a <= 8) then
488
{ now allowed to shift an address register }
489
if (isaddressregister(reg)) then
491
scratch_reg := cg.getintregister(list,OS_INT);
492
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg, scratch_reg));
493
list.concat(taicpu.op_const_reg(opcode,S_L,a, scratch_reg));
494
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,scratch_reg,reg));
495
cg.ungetregister(list,scratch_reg);
498
list.concat(taicpu.op_const_reg(opcode,S_L,a, reg));
502
{ we must load the data into a register ... :() }
503
scratch_reg := cg.getintregister(list,OS_INT);
504
list.concat(taicpu.op_const_reg(A_MOVE,S_L,a, scratch_reg));
505
{ again... since shifting with address register is not allowed }
506
if (isaddressregister(reg)) then
508
scratch_reg2 := cg.getintregister(list,OS_INT);
509
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg, scratch_reg2));
510
list.concat(taicpu.op_reg_reg(opcode,S_L,scratch_reg, scratch_reg2));
511
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,scratch_reg2,reg));
512
cg.ungetregister(list,scratch_reg2);
515
list.concat(taicpu.op_reg_reg(opcode,S_L,scratch_reg, reg));
516
cg.ungetregister(list,scratch_reg);
521
if (a >= 1) and (a <= 8) then
522
list.concat(taicpu.op_const_reg(A_SUBQ,S_L,a,reg))
525
{ all others, including coldfire }
526
list.concat(taicpu.op_const_reg(A_SUB,S_L,a, reg));
531
list.concat(taicpu.op_const_reg(A_EORI,S_L,a, reg));
534
internalerror(20020729);
539
procedure tcg68k.a_op_reg_reg(list : taasmoutput; Op: TOpCG; size: TCGSize; reg1, reg2: TRegister);
541
hreg1,hreg2,r,r2: tregister;
546
if aktoptprocessor = ColdFire then
548
{ operation only allowed only a longword }
549
sign_extend(list, size, reg1);
550
sign_extend(list, size, reg2);
551
list.concat(taicpu.op_reg_reg(A_ADD,S_L,reg1, reg2));
555
list.concat(taicpu.op_reg_reg(A_ADD,TCGSize2OpSize[size],reg1, reg2));
560
OP_SHR,OP_SUB,OP_XOR :
562
{ load to data registers }
563
if (isaddressregister(reg1)) then
565
hreg1 := cg.getintregister(list,OS_INT);
566
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg1,hreg1));
571
if (isaddressregister(reg2)) then
573
hreg2:= cg.getintregister(list,OS_INT);
574
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg2,hreg2));
579
if aktoptprocessor = ColdFire then
581
{ operation only allowed only a longword }
582
{!***************************************
583
in the case of shifts, the value to
584
shift by, should already be valid, so
585
no need to sign extend the value
588
if op in [OP_AND,OP_OR,OP_SUB,OP_XOR] then
589
sign_extend(list, size, hreg1);
590
sign_extend(list, size, hreg2);
591
list.concat(taicpu.op_reg_reg(topcg2tasmop[op],S_L,hreg1, hreg2));
595
list.concat(taicpu.op_reg_reg(topcg2tasmop[op],TCGSize2OpSize[size],hreg1, hreg2));
598
if reg1 <> hreg1 then
599
cg.ungetregister(list,hreg1);
600
{ move back result into destination register }
601
if reg2 <> hreg2 then
603
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,hreg2,reg2));
604
cg.ungetregister(list,hreg2);
609
internalerror(20020816);
613
internalerror(20020816);
617
sign_extend(list, size,reg1);
618
sign_extend(list, size,reg2);
619
if aktoptprocessor = MC68000 then
623
getexplicitregister(list,NR_D0);
624
getexplicitregister(list,NR_D1);
625
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg1, r));
626
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg2, r2));
627
cg.a_call_name(list,'FPC_MUL_LONGINT');
628
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,r, reg2));
629
ungetregister(list,r);
630
ungetregister(list,r2);
634
if (isaddressregister(reg1)) then
635
hreg1 := cg.getintregister(list,OS_INT)
638
if (isaddressregister(reg2)) then
639
hreg2:= cg.getintregister(list,OS_INT)
643
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg1,hreg1));
644
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg2,hreg2));
646
list.concat(taicpu.op_reg_reg(A_MULS,S_L,reg1,reg2));
648
if reg1 <> hreg1 then
649
cg.ungetregister(list,hreg1);
650
{ move back result into destination register }
651
if reg2 <> hreg2 then
653
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,hreg2,reg2));
654
cg.ungetregister(list,hreg2);
660
sign_extend(list, size,reg1);
661
sign_extend(list, size,reg2);
662
if aktoptprocessor = MC68000 then
666
getexplicitregister(list,NR_D0);
667
getexplicitregister(list,NR_D1);
668
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg1, r));
669
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg2, r2));
670
cg.a_call_name(list,'FPC_MUL_LONGWORD');
671
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,r, reg2));
672
ungetregister(list,r);
673
ungetregister(list,r2);
677
if (isaddressregister(reg1)) then
679
hreg1 := cg.getintregister(list,OS_INT);
680
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg1,hreg1));
685
if (isaddressregister(reg2)) then
687
hreg2:= cg.getintregister(list,OS_INT);
688
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg2,hreg2));
694
list.concat(taicpu.op_reg_reg(A_MULU,S_L,reg1,reg2));
697
cg.ungetregister(list,hreg1);
698
{ move back result into destination register }
701
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,hreg2,reg2));
702
cg.ungetregister(list,hreg2);
709
{ if there are two operands, move the register,
710
since the operation will only be done on the result
713
if reg1 <> NR_NO then
714
cg.a_load_reg_reg(exprasmlist,OS_INT,OS_INT,reg1,reg2);
716
if (isaddressregister(reg2)) then
718
hreg2 := cg.getintregister(list,OS_INT);
719
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg2,hreg2));
724
{ coldfire only supports long version }
725
if aktoptprocessor = ColdFire then
727
sign_extend(list, size,hreg2);
728
list.concat(taicpu.op_reg(topcg2tasmop[op],S_L,hreg2));
732
list.concat(taicpu.op_reg(topcg2tasmop[op],TCGSize2OpSize[size],hreg2));
735
if reg2 <> hreg2 then
737
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,hreg2,reg2));
738
cg.ungetregister(list,hreg2);
743
internalerror(20020729);
749
procedure tcg68k.a_cmp_const_reg_label(list : taasmoutput;size : tcgsize;cmp_op : topcmp;a : aword;reg : tregister;
752
hregister : tregister;
756
list.concat(taicpu.op_reg(A_TST,TCGSize2OpSize[size],reg));
760
if (aktoptprocessor = ColdFire) then
763
only longword comparison is supported,
764
and only on data registers.
766
hregister := cg.getintregister(list,OS_INT);
767
{ always move to a data register }
768
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg,hregister));
769
{ sign/zero extend the register }
770
sign_extend(list, size,hregister);
771
list.concat(taicpu.op_const_reg(A_CMPI,S_L,a,hregister));
772
cg.ungetregister(list,hregister);
776
list.concat(taicpu.op_const_reg(A_CMPI,TCGSize2OpSize[size],a,reg));
779
{ emit the actual jump to the label }
780
a_jmp_cond(list,cmp_op,l);
783
procedure tcg68k.a_cmp_reg_reg_label(list : taasmoutput;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel);
785
list.concat(taicpu.op_reg_reg(A_CMP,tcgsize2opsize[size],reg1,reg2));
786
{ emit the actual jump to the label }
787
a_jmp_cond(list,cmp_op,l);
790
procedure tcg68k.a_jmp_always(list : taasmoutput;l: tasmlabel);
794
ai := Taicpu.op_sym(A_JMP,S_NO,l);
799
procedure tcg68k.a_jmp_flags(list : taasmoutput;const f : TResFlags;l: tasmlabel);
803
ai := Taicpu.op_sym(A_BXX,S_NO,l);
804
ai.SetCondition(flags_to_cond(f));
809
procedure tcg68k.g_flags2reg(list: taasmoutput; size: TCgSize; const f: tresflags; reg: TRegister);
814
{ move to a Dx register? }
815
if (isaddressregister(reg)) then
817
hreg := getintregister(list,OS_INT);
818
a_load_const_reg(list,size,0,hreg);
819
ai:=Taicpu.Op_reg(A_Sxx,S_B,hreg);
820
ai.SetCondition(flags_to_cond(f));
823
if (aktoptprocessor = ColdFire) then
825
{ neg.b does not exist on the Coldfire
826
so we need to sign extend the value
829
list.concat(taicpu.op_reg(A_EXTB,S_L,hreg));
830
list.concat(taicpu.op_reg(A_NEG,S_L,hreg));
834
list.concat(taicpu.op_reg(A_NEG,S_B,hreg));
836
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,hreg,reg));
837
ungetregister(list,hreg);
841
a_load_const_reg(list,size,0,reg);
842
ai:=Taicpu.Op_reg(A_Sxx,S_B,reg);
843
ai.SetCondition(flags_to_cond(f));
846
if (aktoptprocessor = ColdFire) then
848
{ neg.b does not exist on the Coldfire
849
so we need to sign extend the value
852
list.concat(taicpu.op_reg(A_EXTB,S_L,reg));
853
list.concat(taicpu.op_reg(A_NEG,S_L,reg));
857
list.concat(taicpu.op_reg(A_NEG,S_B,reg));
864
procedure tcg68k.g_concatcopy(list : taasmoutput;const source,dest : treference;len : aword;delsource,loadref : boolean);
868
reg8,reg32 : tregister;
870
hregister : tregister;
871
iregister : tregister;
872
jregister : tregister;
877
popaddress : boolean;
878
srcref,dstref : treference;
883
{ this should never occur }
886
hregister := getintregister(list,OS_INT);
888
reference_release(list,source);
891
{ from 12 bytes movs is being used }
892
if (not loadref) and ((len<=8) or (not(cs_littlesize in aktglobalswitches) and (len<=12))) then
897
{ move a dword x times }
898
for i:=1 to helpsize do
900
a_load_ref_reg(list,OS_INT,OS_INT,srcref,hregister);
901
a_load_reg_ref(list,OS_INT,OS_INT,hregister,dstref);
902
inc(srcref.offset,4);
903
inc(dstref.offset,4);
909
a_load_ref_reg(list,OS_16,OS_16,srcref,hregister);
910
a_load_reg_ref(list,OS_16,OS_16,hregister,dstref);
911
inc(srcref.offset,2);
912
inc(dstref.offset,2);
915
{ move a single byte }
918
a_load_ref_reg(list,OS_8,OS_8,srcref,hregister);
919
a_load_reg_ref(list,OS_8,OS_8,hregister,dstref);
924
iregister:=getaddressregister(list);
925
jregister:=getaddressregister(list);
926
{ reference for move (An)+,(An)+ }
927
reference_reset(hp1);
928
hp1.base := iregister; { source register }
929
hp1.direction := dir_inc;
930
reference_reset(hp2);
931
hp2.base := jregister;
932
hp2.direction := dir_inc;
933
{ iregister = source }
934
{ jregister = destination }
937
a_load_ref_reg(list,OS_INT,OS_INT,source,iregister)
939
a_loadaddr_ref_reg(list,source,iregister);
941
a_loadaddr_ref_reg(list,dest,jregister);
943
{ double word move only on 68020+ machines }
944
{ because of possible alignment problems }
945
{ use fast loop mode }
946
if (aktoptprocessor=MC68020) then
948
helpsize := len - len mod 4;
950
list.concat(taicpu.op_const_reg(A_MOVE,S_L,helpsize div 4,hregister));
951
objectlibrary.getlabel(hl2);
952
a_jmp_always(list,hl2);
953
objectlibrary.getlabel(hl);
955
list.concat(taicpu.op_ref_ref(A_MOVE,S_L,hp1,hp2));
956
cg.a_label(list,hl2);
957
list.concat(taicpu.op_reg_sym(A_DBRA,S_L,hregister,hl));
961
list.concat(taicpu.op_ref_ref(A_MOVE,S_W,hp1,hp2));
964
list.concat(taicpu.op_ref_ref(A_MOVE,S_B,hp1,hp2));
968
{ Fast 68010 loop mode with no possible alignment problems }
970
list.concat(taicpu.op_const_reg(A_MOVE,S_L,helpsize,hregister));
971
objectlibrary.getlabel(hl2);
972
a_jmp_always(list,hl2);
973
objectlibrary.getlabel(hl);
975
list.concat(taicpu.op_ref_ref(A_MOVE,S_B,hp1,hp2));
977
list.concat(taicpu.op_reg_sym(A_DBRA,S_L,hregister,hl));
980
{ restore the registers that we have just used olny if they are used! }
981
ungetregister(list, iregister);
982
ungetregister(list, jregister);
983
if jregister = NR_A1 then
985
if iregister = NR_A0 then
987
reference_release(list,hp1);
988
reference_release(list,hp2);
992
tg.ungetiftemp(list,source);
994
ungetregister(list,hregister);
997
procedure tcg68k.g_overflowcheck(list: taasmoutput; const l:tlocation; def:tdef);
1001
procedure tcg68k.g_copyvaluepara_openarray(list : taasmoutput;const ref, lenref:treference;elesize:aword);
1006
procedure tcg68k.g_stackframe_entry(list : taasmoutput;localsize : longint);
1011
r:=NR_FRAME_POINTER_REG;
1012
rsp:=NR_STACK_POINTER_REG;
1013
if localsize<>0 then
1015
{ Not to complicate the code generator too much, and since some }
1016
{ of the systems only support this format, the localsize cannot }
1017
{ exceed 32K in size. }
1018
if (localsize < low(smallint)) or (localsize > high(smallint)) then
1019
CGMessage(cg_e_localsize_too_big);
1020
list.concat(taicpu.op_reg_const(A_LINK,S_W,r,-localsize));
1021
end { endif localsize <> 0 }
1024
reference_reset_base(ref,NR_STACK_POINTER_REG,0);
1025
ref.direction:=dir_dec;
1026
list.concat(taicpu.op_reg_ref(A_MOVE,S_L,r,ref));
1027
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,rsp,r));
1032
procedure tcg68k.g_restore_frame_pointer(list : taasmoutput);
1036
r:=NR_FRAME_POINTER_REG;
1037
list.concat(taicpu.op_reg(A_UNLK,S_NO,r));
1041
procedure tcg68k.g_return_from_proc(list : taasmoutput;parasize : aword);
1043
r,hregister : tregister;
1046
{ Routines with the poclearstack flag set use only a ret.
1047
also routines with parasize=0 }
1048
if current_procinfo.procdef.proccalloption in clearstack_pocalls then
1050
{ complex return values are removed from stack in C code PM }
1051
if paramanager.ret_in_param(current_procinfo.procdef.rettype.def,current_procinfo.procdef.proccalloption) then
1052
list.concat(taicpu.op_const(A_RTD,S_NO,4))
1054
list.concat(taicpu.op_none(A_RTS,S_NO));
1056
else if (parasize=0) then
1058
list.concat(taicpu.op_none(A_RTS,S_NO));
1062
{ return with immediate size possible here
1064
RTD is not supported on the coldfire }
1065
if (aktoptprocessor=MC68020) and (parasize<$7FFF) then
1066
list.concat(taicpu.op_const(A_RTD,S_NO,parasize))
1067
{ manually restore the stack }
1070
{ We must pull the PC Counter from the stack, before }
1071
{ restoring the stack pointer, otherwise the PC would }
1072
{ point to nowhere! }
1074
{ save the PC counter (pop it from the stack) }
1076
a_reg_alloc(list,hregister);
1077
reference_reset_base(ref,NR_STACK_POINTER_REG,0);
1078
ref.direction:=dir_inc;
1079
list.concat(taicpu.op_ref_reg(A_MOVE,S_L,ref,hregister));
1080
{ can we do a quick addition ... }
1082
if (parasize > 0) and (parasize < 9) then
1083
list.concat(taicpu.op_const_reg(A_ADDQ,S_L,parasize,r))
1085
list.concat(taicpu.op_const_reg(A_ADD,S_L,parasize,r));
1087
{ restore the PC counter (push it on the stack) }
1088
reference_reset_base(ref,NR_STACK_POINTER_REG,0);
1089
ref.direction:=dir_dec;
1090
list.concat(taicpu.op_reg_ref(A_MOVE,S_L,hregister,ref));
1091
a_reg_alloc(list,hregister);
1092
list.concat(taicpu.op_none(A_RTS,S_NO));
1098
procedure Tcg68k.g_save_standard_registers(list:Taasmoutput);
1100
tosave : tcpuregisterset;
1104
tosave:=std_saved_registers;
1105
{ only save the registers which are not used and must be saved }
1106
tosave:=tosave*(rg[R_INTREGISTER].used_in_proc+rg[R_ADDRESSREGISTER].used_in_proc);
1107
reference_reset_base(ref,NR_STACK_POINTER_REG,0);
1108
ref.direction:=dir_dec;
1110
list.concat(taicpu.op_regset_ref(A_MOVEM,S_L,tosave,ref));
1115
procedure Tcg68k.g_restore_standard_registers(list:Taasmoutput);
1117
torestore : tcpuregisterset;
1122
torestore:=std_saved_registers;
1123
{ should be intersected with used regs, no ? }
1124
torestore:=torestore*(rg[R_INTREGISTER].used_in_proc+rg[R_ADDRESSREGISTER].used_in_proc);
1125
reference_reset_base(ref,NR_STACK_POINTER_REG,0);
1126
ref.direction:=dir_inc;
1127
if torestore<>[] then
1128
list.concat(taicpu.op_ref_regset(A_MOVEM,S_L,ref,torestore));
1133
procedure tcg68k.g_save_all_registers(list : taasmoutput);
1137
procedure tcg68k.g_restore_all_registers(list : taasmoutput;const funcretparaloc:tparalocation);
1141
procedure tcg68k.sign_extend(list: taasmoutput;_oldsize : tcgsize; reg: tregister);
1147
if (isaddressregister(reg)) then
1148
internalerror(20020729);
1149
if (aktoptprocessor = MC68000) then
1151
list.concat(taicpu.op_reg(A_EXT,S_W,reg));
1152
list.concat(taicpu.op_reg(A_EXT,S_L,reg));
1156
list.concat(taicpu.op_reg(A_EXTB,S_L,reg));
1161
if (isaddressregister(reg)) then
1162
internalerror(20020729);
1163
list.concat(taicpu.op_reg(A_EXT,S_L,reg));
1168
list.concat(taicpu.op_const_reg(A_AND,S_L,$FF,reg));
1172
list.concat(taicpu.op_const_reg(A_AND,S_L,$FFFF,reg));
1174
end; { otherwise the size is already correct }
1177
procedure tcg68k.a_jmp_cond(list : taasmoutput;cond : TOpCmp;l: tasmlabel);
1183
if cond=OC_None then
1184
ai := Taicpu.Op_sym(A_JMP,S_NO,l)
1187
ai:=Taicpu.Op_sym(A_Bxx,S_NO,l);
1188
ai.SetCondition(TOpCmp2AsmCond[cond]);
1194
{****************************************************************************}
1196
{****************************************************************************}
1197
procedure tcg64f68k.a_op64_reg_reg(list : taasmoutput;op:TOpCG;regsrc,regdst : tregister64);
1199
hreg1, hreg2 : tregister;
1202
opcode := topcg2tasmop[op];
1206
{ if one of these three registers is an address
1207
register, we'll really get into problems!
1209
if isaddressregister(regdst.reglo) or
1210
isaddressregister(regdst.reghi) or
1211
isaddressregister(regsrc.reghi) then
1212
internalerror(20020817);
1213
list.concat(taicpu.op_reg_reg(A_ADD,S_L,regsrc.reglo,regdst.reglo));
1214
list.concat(taicpu.op_reg_reg(A_ADDX,S_L,regsrc.reghi,regdst.reghi));
1218
{ at least one of the registers must be a data register }
1219
if (isaddressregister(regdst.reglo) and
1220
isaddressregister(regsrc.reglo)) or
1221
(isaddressregister(regsrc.reghi) and
1222
isaddressregister(regdst.reghi))
1224
internalerror(20020817);
1225
cg.a_op_reg_reg(list,op,OS_32,regsrc.reglo,regdst.reglo);
1226
cg.a_op_reg_reg(list,op,OS_32,regsrc.reghi,regdst.reghi);
1228
{ this is handled in 1st pass for 32-bit cpu's (helper call) }
1230
OP_IMUL,OP_MUL: internalerror(2002081701);
1231
{ this is also handled in 1st pass for 32-bit cpu's (helper call) }
1232
OP_SAR,OP_SHL,OP_SHR: internalerror(2002081702);
1235
{ if one of these three registers is an address
1236
register, we'll really get into problems!
1238
if isaddressregister(regdst.reglo) or
1239
isaddressregister(regdst.reghi) or
1240
isaddressregister(regsrc.reghi) then
1241
internalerror(20020817);
1242
list.concat(taicpu.op_reg_reg(A_SUB,S_L,regsrc.reglo,regdst.reglo));
1243
list.concat(taicpu.op_reg_reg(A_SUBX,S_L,regsrc.reghi,regdst.reghi));
1247
if isaddressregister(regdst.reglo) or
1248
isaddressregister(regsrc.reglo) or
1249
isaddressregister(regsrc.reghi) or
1250
isaddressregister(regdst.reghi) then
1251
internalerror(20020817);
1252
list.concat(taicpu.op_reg_reg(A_EOR,S_L,regsrc.reglo,regdst.reglo));
1253
list.concat(taicpu.op_reg_reg(A_EOR,S_L,regsrc.reghi,regdst.reghi));
1259
procedure tcg64f68k.a_op64_const_reg(list : taasmoutput;op:TOpCG;value : qword;reg : tregister64);
1261
lowvalue : cardinal;
1262
highvalue : cardinal;
1264
{ is it optimized out ? }
1265
if optimize64_op_const_reg(list,op,value,reg) then
1268
lowvalue := cardinal(value);
1269
highvalue:= value shr 32;
1271
{ the destination registers must be data registers }
1272
if isaddressregister(reg.reglo) or
1273
isaddressregister(reg.reghi) then
1274
internalerror(20020817);
1278
list.concat(taicpu.op_const_reg(A_ADD,S_L,lowvalue,reg.reglo));
1279
list.concat(taicpu.op_const_reg(A_ADDX,S_L,highvalue,reg.reglo));
1283
{ should already be optimized out }
1284
internalerror(2002081801);
1288
{ should already be optimized out }
1289
internalerror(2002081802);
1291
{ this is handled in 1st pass for 32-bit cpu's (helper call) }
1293
OP_IMUL,OP_MUL: internalerror(2002081701);
1294
{ this is also handled in 1st pass for 32-bit cpu's (helper call) }
1295
OP_SAR,OP_SHL,OP_SHR: internalerror(2002081702);
1298
list.concat(taicpu.op_const_reg(A_SUB,S_L,lowvalue,reg.reglo));
1299
list.concat(taicpu.op_const_reg(A_SUBX,S_L,highvalue,reg.reglo));
1303
list.concat(taicpu.op_const_reg(A_EOR,S_L,lowvalue,reg.reglo));
1304
list.concat(taicpu.op_const_reg(A_EOR,S_L,highvalue,reg.reglo));
1310
cg := tcg68k.create;
1311
cg64 :=tcg64f68k.create;
1316
Revision 1.27 2004/05/20 21:54:33 florian
1317
+ <pointer> - <pointer> result is divided by the pointer element size now
1318
this is delphi compatible as well as resulting in the expected result for p1+(p2-p1)
1320
Revision 1.26 2004/05/06 22:01:54 florian
1321
* register numbers for address registers fixed
1323
Revision 1.25 2004/05/06 20:30:51 florian
1324
* m68k compiler compilation fixed
1326
Revision 1.24 2004/04/19 21:15:12 florian
1329
Revision 1.23 2004/04/18 21:13:59 florian
1330
* more adaptions for m68k
1332
Revision 1.22 2004/03/02 00:36:33 olle
1333
* big transformation of Tai_[const_]Symbol.Create[data]name*
1335
Revision 1.21 2004/01/30 12:17:18 florian
1336
* fixed some m68k compilation problems
1338
Revision 1.20 2003/04/27 11:21:36 peter
1339
* aktprocdef renamed to current_procdef
1340
* procinfo renamed to current_procinfo
1341
* procinfo will now be stored in current_module so it can be
1343
* gen_main_procsym changed to create_main_proc and release_main_proc
1344
to also generate a tprocinfo structure
1345
* fixed unit implicit initfinal
1347
Revision 1.19 2003/04/23 13:40:33 peter
1350
Revision 1.18 2003/02/19 22:00:16 daniel
1351
* Code generator converted to new register notation
1352
- Horribily outdated todo.txt removed
1354
Revision 1.17 2003/02/12 22:11:13 carl
1355
* some small m68k bugfixes
1357
Revision 1.16 2003/02/02 19:25:54 carl
1358
* Several bugfixes for m68k target (register alloc., opcode emission)
1360
+ Generic add more complete (still not verified)
1362
Revision 1.15 2003/01/08 18:43:57 daniel
1363
* Tregister changed into a record
1365
Revision 1.14 2003/01/05 13:36:53 florian
1367
+ very basic support for float128 type (x86-64 only)
1369
Revision 1.13 2002/12/01 22:12:36 carl
1370
* rename an error message
1372
Revision 1.12 2002/11/25 17:43:27 peter
1373
* splitted defbase in defutil,symutil,defcmp
1374
* merged isconvertable and is_equal into compare_defs(_ext)
1375
* made operator search faster by walking the list only once
1377
Revision 1.11 2002/11/18 17:32:00 peter
1378
* pass proccalloption to ret_in_xxx and push_xxx functions
1380
Revision 1.10 2002/09/22 14:15:31 carl
1383
Revision 1.9 2002/09/17 18:54:05 jonas
1384
* a_load_reg_reg() now has two size parameters: source and dest. This
1385
allows some optimizations on architectures that don't encode the
1386
register size in the register name.
1388
Revision 1.8 2002/09/08 15:12:45 carl
1391
Revision 1.7 2002/09/07 20:53:28 carl
1392
* cardinal -> longword
1394
Revision 1.6 2002/09/07 15:25:12 peter
1395
* old logs removed and tabs fixed
1397
Revision 1.5 2002/08/19 18:17:48 carl
1398
+ optimize64_op_const_reg implemented (optimizes 64-bit constant opcodes)
1399
* more fixes to m68k for 64-bit operations
1401
Revision 1.4 2002/08/16 14:24:59 carl
1402
* issameref() to test if two references are the same (then emit no opcodes)
1403
+ ret_in_reg to replace ret_in_acc
1404
(fix some register allocation bugs at the same time)
1405
+ save_std_register now has an extra parameter which is the
1406
usedinproc registers
1408
Revision 1.3 2002/08/15 08:13:54 carl
1409
- a_load_sym_ofs_reg removed
1410
* loadvmt now calls loadaddr_ref_reg instead
1412
Revision 1.2 2002/08/14 19:16:34 carl
1413
+ m68k type conversion nodes
1414
+ started some mathematical nodes
1415
* out of bound references should now be handled correctly
1417
Revision 1.1 2002/08/13 18:30:22 carl
1418
* rename swatoperands to swapoperands
1419
+ m68k first compilable version (still needs a lot of testing):
1420
assembler generator, system information , inline
1423
Revision 1.5 2002/08/12 15:08:43 carl
1424
+ stab register indexes for powerpc (moved from gdb to cpubase)
1425
+ tprocessor enumeration moved to cpuinfo
1426
+ linker in target_info is now a class
1427
* many many updates for m68k (will soon start to compile)
1428
- removed some ifdef or correct them for correct cpu
1430
Revision 1.2 2002/08/05 17:27:52 carl
1433
Revision 1.1 2002/07/29 17:51:32 carl
1434
+ restart m68k support