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  • Committer: Bazaar Package Importer
  • Author(s): Matthew Garrett
  • Date: 2006-02-13 14:21:43 UTC
  • Revision ID: james.westby@ubuntu.com-20060213142143-mad6z9xzem7hzxz9
Tags: upstream-7.0.0
Import upstream version 7.0.0

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hw/kdrive/sis530/sis.h
 
1
/*
 
2
 * Id: sis.h,v 1.1 1999/11/02 08:17:24 keithp Exp $
 
3
 *
 
4
 * Copyright � 1999 Keith Packard
 
5
 *
 
6
 * Permission to use, copy, modify, distribute, and sell this software and its
 
7
 * documentation for any purpose is hereby granted without fee, provided that
 
8
 * the above copyright notice appear in all copies and that both that
 
9
 * copyright notice and this permission notice appear in supporting
 
10
 * documentation, and that the name of Keith Packard not be used in
 
11
 * advertising or publicity pertaining to distribution of the software without
 
12
 * specific, written prior permission.  Keith Packard makes no
 
13
 * representations about the suitability of this software for any purpose.  It
 
14
 * is provided "as is" without express or implied warranty.
 
15
 *
 
16
 * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
 
17
 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
 
18
 * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR
 
19
 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
 
20
 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
 
21
 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
 
22
 * PERFORMANCE OF THIS SOFTWARE.
 
23
 */
 
24
/* $RCSId: xc/programs/Xserver/hw/kdrive/sis530/sis.h,v 1.4 2000/05/06 22:17:49 keithp Exp $ */
 
25
 
 
26
#ifndef _SIS_H_
 
27
#define _SIS_H_
 
28
#include "kdrive.h"
 
29
#include <stdio.h>
 
30
#include <unistd.h>
 
31
#include <sys/mman.h>
 
32
#include <asm/io.h>
 
33
#include <stdio.h>
 
34
 
 
35
/*
 
36
 *  Linear Addressing           000 0000 - 0ff ffff (16m)
 
37
 *  Image data transfer         100 0000 - 100 7fff (32k)
 
38
 *  Empty                       100 8000 - 100 81ff
 
39
 *  MMIO registers              100 8200 - 100 8480
 
40
 *
 
41
 * We don't care about the image transfer or PCI regs, so
 
42
 * this structure starts at the MMIO regs
 
43
 */
 
44
    
 
45
typedef volatile CARD32 VOL32;
 
46
typedef volatile CARD16 VOL16;
 
47
typedef volatile CARD8 VOL8;
 
48
 
 
49
#define SIS_MMIO_OFFSET 0x8200
 
50
 
 
51
typedef struct _sis530General {
 
52
    VOL32       src_base;               /* 8200 */
 
53
    VOL16       src_pitch;              /* 8204 */
 
54
    VOL16       _pad0;                  /* 8206 */
 
55
    VOL16       src_y;                  /* 8208 */
 
56
    VOL16       src_x;                  /* 820a */
 
57
    VOL16       dst_y;                  /* 820c */
 
58
    VOL16       dst_x;                  /* 820e */
 
59
    VOL32       dst_base;               /* 8210 */
 
60
    VOL16       dst_pitch;              /* 8214 */
 
61
    VOL16       dst_height;             /* 8216 */
 
62
    VOL16       rect_width;             /* 8218 */
 
63
    VOL16       rect_height;            /* 821a */
 
64
    VOL32       pattern_fg;             /* 821c */
 
65
    VOL32       pattern_bg;             /* 8220 */
 
66
    VOL32       src_fg;                 /* 8224 */
 
67
    VOL32       src_bg;                 /* 8228 */
 
68
    VOL8        mask[8];                /* 822c */
 
69
    VOL16       clip_left;              /* 8234 */
 
70
    VOL16       clip_top;               /* 8236 */
 
71
    VOL16       clip_right;             /* 8238 */
 
72
    VOL16       clip_bottom;            /* 823a */
 
73
    VOL32       command;                /* 823c */
 
74
    VOL32       status;                 /* 8240 */
 
75
    VOL8        _pad1[0xbc];            /* 8244 */
 
76
    VOL8        pattern[256];           /* 8300 */
 
77
                                        /* 8400 */
 
78
} SisGeneral;
 
79
 
 
80
typedef struct _sis530Line {
 
81
    VOL8        _pad0[8];               /* 8200 */
 
82
    VOL16       x0;                     /* 8208 */
 
83
    VOL16       y0;                     /* 820a */
 
84
    VOL16       x1;                     /* 820c */
 
85
    VOL16       y1;                     /* 820e */
 
86
    VOL32       dst_base;               /* 8210 */
 
87
    VOL16       dst_pitch;              /* 8214 */
 
88
    VOL16       dst_height;             /* 8216 */
 
89
    VOL16       count;                  /* 8218 */
 
90
    VOL16       style_period;           /* 821a */
 
91
    VOL32       fg;                     /* 821c */
 
92
    VOL32       bg;                     /* 8220 */
 
93
    VOL8        _pad1[8];               /* 8224 */
 
94
    VOL32       style0;                 /* 822c */
 
95
    VOL32       style1;                 /* 8228 */
 
96
    VOL16       clip_left;              /* 8234 */
 
97
    VOL16       clip_top;               /* 8236 */
 
98
    VOL16       clip_right;             /* 8238 */
 
99
    VOL16       clip_bottom;            /* 823a */
 
100
    VOL32       command;                /* 823c */
 
101
    VOL32       status;                 /* 8240 */
 
102
    VOL8        _pad2[0xbc];            /* 8244 */
 
103
    struct {
 
104
        VOL16   x;
 
105
        VOL16   y;
 
106
    }           data[96];               /* 8300 */
 
107
                                        /* 8480 */
 
108
} SisLine;
 
109
 
 
110
typedef struct _sis530Transparent {
 
111
    VOL32       src_base;               /* 8200 */
 
112
    VOL16       src_pitch;              /* 8204 */
 
113
    VOL16       _pad0;                  /* 8206 */
 
114
    VOL16       src_y;                  /* 8208 */
 
115
    VOL16       src_x;                  /* 820a */
 
116
    VOL16       dst_y;                  /* 820c */
 
117
    VOL16       dst_x;                  /* 820e */
 
118
    VOL32       dst_base;               /* 8210 */
 
119
    VOL16       dst_pitch;              /* 8214 */
 
120
    VOL16       dst_height;             /* 8216 */
 
121
    VOL16       rect_width;             /* 8218 */
 
122
    VOL16       rect_height;            /* 821a */
 
123
    VOL32       dst_key_high;           /* 821c */
 
124
    VOL32       dst_key_low;            /* 8220 */
 
125
    VOL32       src_key_high;           /* 8224 */
 
126
    VOL32       src_key_low;            /* 8228 */
 
127
    VOL8        _pad1[8];               /* 822c */
 
128
    VOL16       clip_left;              /* 8234 */
 
129
    VOL16       clip_top;               /* 8236 */
 
130
    VOL16       clip_right;             /* 8238 */
 
131
    VOL16       clip_bottom;            /* 823a */
 
132
    VOL32       command;                /* 823c */
 
133
    VOL32       status;                 /* 8240 */
 
134
                                        /* 8244 */
 
135
} SisTransparent;
 
136
 
 
137
typedef struct _sis530Multiple {
 
138
    VOL8        _pad0[8];               /* 8200 */
 
139
    VOL16       count;                  /* 8208 */
 
140
    VOL16       y;                      /* 820a */
 
141
    VOL16       x0_start;               /* 820c */
 
142
    VOL16       x0_end;                 /* 820e */
 
143
    VOL32       dst_base;               /* 8210 */
 
144
    VOL16       dst_pitch;              /* 8214 */
 
145
    VOL16       dst_height;             /* 8216 */
 
146
    VOL8        _pad1[4];               /* 8218 */
 
147
    VOL32       fg;                     /* 821c */
 
148
    VOL32       bg;                     /* 8220 */
 
149
    VOL8        _pad2[8];               /* 8224 */
 
150
    VOL8        mask[8];                /* 822c */
 
151
    VOL16       clip_left;              /* 8234 */
 
152
    VOL16       clip_top;               /* 8236 */
 
153
    VOL16       clip_right;             /* 8238 */
 
154
    VOL16       clip_bottom;            /* 823a */
 
155
    VOL32       command;                /* 823c */
 
156
    VOL32       status;                 /* 8240 */
 
157
    VOL16       x1_start;               /* 8244 */
 
158
    VOL16       x1_end;                 /* 8246 */
 
159
    VOL8        _pad3[0xb8];            /* 8248 */
 
160
    VOL8        pattern[64];            /* 8300 */
 
161
    struct {
 
162
        VOL16   x_start;
 
163
        VOL16   y_end;
 
164
    }           data[80];               /* 8340 */
 
165
                                        /* 8480 */
 
166
} SisMultiple;
 
167
 
 
168
typedef struct _sis530Trapezoid {
 
169
    VOL8        _pad0[8];               /* 8200 */
 
170
    VOL16       height;                 /* 8208 */
 
171
    VOL16       y;                      /* 820a */
 
172
    VOL16       left_x;                 /* 820c */
 
173
    VOL16       right_x;                /* 820e */
 
174
    VOL32       dst_base;               /* 8210 */
 
175
    VOL16       dst_pitch;              /* 8214 */
 
176
    VOL16       dst_height;             /* 8216 */
 
177
    VOL8        _pad1[4];               /* 8218 */
 
178
    VOL32       fg;                     /* 821c */
 
179
    VOL32       bg;                     /* 8220 */
 
180
    VOL8        _pad2[8];               /* 8224 */
 
181
    VOL8        mask[8];                /* 822c */
 
182
    VOL16       clip_left;              /* 8234 */
 
183
    VOL16       clip_top;               /* 8236 */
 
184
    VOL16       clip_right;             /* 8238 */
 
185
    VOL16       clip_bottom;            /* 823a */
 
186
    VOL32       command;                /* 823c */
 
187
    VOL32       status;                 /* 8240 */
 
188
    VOL16       left_dx;                /* 8244 */
 
189
    VOL16       left_dy;                /* 8246 */
 
190
    VOL16       right_dx;               /* 8248 */
 
191
    VOL16       right_dy;               /* 824a */
 
192
    VOL32       left_error;             /* 824c */
 
193
    VOL32       right_error;            /* 8250 */
 
194
                                        /* 8254 */
 
195
} SisTrapezoid;
 
196
 
 
197
typedef struct _sisAccel {
 
198
    VOL8        pad[0x80];              /* 8200 */
 
199
    VOL32       src_addr;               /* 8280 */
 
200
    VOL32       dst_addr;               /* 8284 */
 
201
    VOL32       pitch;                  /* 8288 */
 
202
    VOL32       dimension;              /* 828c */
 
203
    VOL32       fg;                     /* 8290 */
 
204
    VOL32       bg;                     /* 8294 */
 
205
    
 
206
 
 
207
    VOL32       clip_ul;                /* 82a0 */
 
208
    VOL32       clip_br;                /* 82a4 */
 
209
 
 
210
    VOL16       cmd;                    /* 82aa */
 
211
 
 
212
    VOL8        pattern[256];           /* 82ac */
 
213
    
 
214
} SisAccel;
 
215
 
 
216
typedef struct _sis530 {
 
217
    union {
 
218
        SisGeneral      general;
 
219
        SisLine         line;
 
220
        SisTransparent  transparent;
 
221
        SisMultiple     multiple;
 
222
        SisTrapezoid    trapezoid;
 
223
        SisAccel        accel;
 
224
    } u;
 
225
} SisRec, *SisPtr;
 
226
 
 
227
typedef struct _sisCursor {
 
228
    int         width, height;
 
229
    int         xhot, yhot;
 
230
    Bool        has_cursor;
 
231
    CursorPtr   pCursor;
 
232
} SisCursor;
 
233
 
 
234
#define SIS_CURSOR_WIDTH    64
 
235
#define SIS_CURSOR_HEIGHT   64
 
236
 
 
237
typedef struct _sisClock {
 
238
    CARD32      vclk_numerator;
 
239
    BOOL        vclk_divide_by_2;
 
240
    CARD32      vclk_denominator;
 
241
    CARD32      vclk_post_scale;
 
242
    BOOL        vclk_post_scale_2;
 
243
    BOOL        high_speed_dac;
 
244
} SisClockRec, *SisClockPtr;
 
245
 
 
246
typedef struct _crtc {
 
247
 
 
248
    union {
 
249
        struct {
 
250
            CARD8   _io_address_select      : 1;
 
251
            CARD8   _display_ram_enable     : 1;
 
252
            CARD8   _clock_select           : 2;
 
253
            CARD8                           : 1;
 
254
            CARD8   _odd_even_page          : 1;
 
255
            CARD8   _h_sync_polarity        : 1;
 
256
            CARD8   _v_sync_polarity        : 1;
 
257
        } _misc_output_s;
 
258
        CARD8   _misc_output;
 
259
    } _misc_output_u;                               /* 3CC/3C2 */
 
260
 
 
261
#define misc_output         _misc_output_u._misc_output
 
262
#define io_address_select   _misc_output_u._misc_output_s._io_address_select
 
263
#define display_ram_enable  _misc_output_u._misc_output_s._display_ram_enable
 
264
#define clock_select        _misc_output_u._misc_output_s._clock_select
 
265
#define odd_even_page       _misc_output_u._misc_output_s._odd_even_page
 
266
#define h_sync_polarity     _misc_output_u._misc_output_s._h_sync_polarity
 
267
#define v_sync_polarity     _misc_output_u._misc_output_s._v_sync_polarity
 
268
    
 
269
    CARD8   h_total_0_7;                            /* CR0 */
 
270
    CARD8   h_display_end_0_7;                      /* CR1 */
 
271
    CARD8   h_blank_start_0_7;                      /* CR2 */
 
272
    union {
 
273
        struct {
 
274
            CARD8   _h_blank_end_0_4        : 5;
 
275
            CARD8   _display_skew           : 2;
 
276
            CARD8                           : 1;
 
277
        } _h_blank_end_s;
 
278
        CARD8   __h_blank_end;                      /* CR3 */
 
279
    } _h_blank_end_u;
 
280
#define h_blank_end_0_4 _h_blank_end_u._h_blank_end_s._h_blank_end_0_4
 
281
#define display_skew    _h_blank_end_u._h_blank_end_s._display_skew
 
282
#define _h_blank_end    _h_blank_end_u.__h_blank_end
 
283
    
 
284
    CARD8   h_sync_start_0_7;                       /* CR4 */
 
285
    
 
286
    union {
 
287
        struct {
 
288
            CARD8   _h_sync_end_0_4         : 5;
 
289
            CARD8   _horizontal_skew        : 2;
 
290
            CARD8   _h_blank_end_5          : 1;
 
291
        } _h_sync_end_s;
 
292
        CARD8   __h_sync_end;                       /* CR5 */
 
293
    } _h_sync_end_u;
 
294
 
 
295
#define h_sync_end_0_4  _h_sync_end_u._h_sync_end_s._h_sync_end_0_4
 
296
#define horizontal_skew _h_sync_end_u._h_sync_end_s._horizontal_skew
 
297
#define h_blank_end_5   _h_sync_end_u._h_sync_end_s._h_blank_end_5
 
298
#define _h_sync_end     _h_sync_end_u.__h_sync_end
 
299
    
 
300
    CARD8   v_total_0_7;                            /* CR6 */
 
301
    
 
302
    union {
 
303
        struct {
 
304
            CARD8   _v_total_8              : 1;
 
305
            CARD8   _v_display_end_8        : 1;
 
306
            CARD8   _v_retrace_start_8      : 1;
 
307
            CARD8   _v_blank_start_8        : 1;
 
308
            CARD8   _line_compare_8         : 1;
 
309
            CARD8   _v_total_9              : 1;
 
310
            CARD8   _v_display_end_9        : 1;
 
311
            CARD8   _v_retrace_start_9      : 1;
 
312
        } _crtc_overflow_s;
 
313
        CARD8   _crtc_overflow;                     /* CR7 */
 
314
    } _crtc_overflow_u;
 
315
 
 
316
#define v_total_8           _crtc_overflow_u._crtc_overflow_s._v_total_8
 
317
#define v_display_end_8     _crtc_overflow_u._crtc_overflow_s._v_display_end_8
 
318
#define v_retrace_start_8   _crtc_overflow_u._crtc_overflow_s._v_retrace_start_8
 
319
#define v_blank_start_8     _crtc_overflow_u._crtc_overflow_s._v_blank_start_8
 
320
#define line_compare_8      _crtc_overflow_u._crtc_overflow_s._line_compare_8
 
321
#define v_total_9           _crtc_overflow_u._crtc_overflow_s._v_total_9
 
322
#define v_display_end_9     _crtc_overflow_u._crtc_overflow_s._v_display_end_9
 
323
#define v_retrace_start_9   _crtc_overflow_u._crtc_overflow_s._v_retrace_start_9
 
324
#define crtc_overflow       _crtc_overflow_u._crtc_overflow
 
325
 
 
326
    CARD8   preset_row_scan;                        /* CR8 (unused) */
 
327
 
 
328
    union {
 
329
        struct {
 
330
            CARD8   ___max_scan_line        : 5;
 
331
            CARD8   _v_blank_start_9        : 1;
 
332
            CARD8   _line_compare_9         : 1;
 
333
            CARD8   _double_scan            : 1;
 
334
        } _max_scan_line_s;
 
335
        CARD8   __max_scan_line;                    /* CR9 */
 
336
    } _max_scan_line_u;
 
337
 
 
338
#define max_scan_line   _max_scan_line_u._max_scan_line_s.___max_scan_line
 
339
#define v_blank_start_9 _max_scan_line_u._max_scan_line_s._v_blank_start_9
 
340
#define line_compare_9  _max_scan_line_u._max_scan_line_s._line_compare_9
 
341
#define double_scan     _max_scan_line_u._max_scan_line_s._double_scan
 
342
#define _max_scan_line  _max_scan_line_u.__max_scan_line
 
343
    
 
344
    CARD8   cursor_start;                           /* CRA */
 
345
    CARD8   cursor_end;                             /* CRB */
 
346
 
 
347
    CARD8   start_address_8_15;                     /* CRC */
 
348
    CARD8   start_address_0_7;                      /* CRD */
 
349
 
 
350
    CARD8   text_cursor_15_8;                       /* CRE */
 
351
    CARD8   text_cursor_7_0;                        /* CRF */
 
352
 
 
353
    CARD8   cursor_loc_high;
 
354
    CARD8   cursor_loc_low;
 
355
 
 
356
    CARD8   v_retrace_start_0_7;                    /* CR10 */
 
357
    union {
 
358
        struct {
 
359
            CARD8   _v_retrace_end_0_3      : 4;
 
360
            CARD8   _clear_v_retrace_int            : 1;
 
361
            CARD8   _disable_v_retrace_int   : 1;
 
362
            CARD8   _refresh_cycle_select    : 1;
 
363
            CARD8   _lock_crtc              : 1;
 
364
        } _v_retrace_end_s;
 
365
        CARD8   __v_retrace_end;                    /* CR11 */
 
366
    } _v_retrace_end_u;
 
367
    
 
368
#define v_retrace_end_0_3       _v_retrace_end_u._v_retrace_end_s._v_retrace_end_0_3
 
369
#define clear_v_retrace_int     _v_retrace_end_u._v_retrace_end_s._clear_v_retrace_int
 
370
#define disable_v_retrace_int   _v_retrace_end_u._v_retrace_end_s._disable_v_retrace_int
 
371
#define refresh_cycle_select    _v_retrace_end_u._v_retrace_end_s._refresh_cycle_select
 
372
#define lock_crtc               _v_retrace_end_u._v_retrace_end_s._lock_crtc
 
373
#define _v_retrace_end          _v_retrace_end_u.__v_retrace_end
 
374
    
 
375
    CARD8   v_display_end_0_7;                      /* CR12 */
 
376
    
 
377
    CARD8   screen_off_0_7;                         /* CR13 */
 
378
    
 
379
    union {
 
380
        struct {
 
381
            CARD8   ___underline_location   : 5;
 
382
            CARD8   _count_by_four          : 1;
 
383
            CARD8   _doubleword_mode        : 1;
 
384
            CARD8                           : 1;
 
385
        } _underline_location_s;
 
386
        CARD8   __underline_location;               /* CR14 */
 
387
    } _underline_location_u;
 
388
 
 
389
#define underline_location  _underline_location_u._underline_location_s.___underline_location
 
390
#define count_by_four       _underline_location_u._underline_location_s._count_by_four
 
391
#define doubleword_mode     _underline_location_u._underline_location_s._doubleword_mode
 
392
#define _underline_location _underline_location_u.__underline_location
 
393
    
 
394
    CARD8   v_blank_start_0_7;                      /* CR15 */
 
395
    CARD8   v_blank_end_0_7;                        /* CR16 */
 
396
 
 
397
    union {
 
398
        struct {
 
399
            CARD8   _two_bk_cga             : 1;
 
400
            CARD8   _four_bk_cga            : 1;
 
401
            CARD8   _v_total_double         : 1;
 
402
            CARD8   _count_by_two           : 1;
 
403
            CARD8                           : 1;
 
404
            CARD8   _address_wrap           : 1;
 
405
            CARD8   _byte_mode              : 1;
 
406
            CARD8   _hardware_reset         : 1;
 
407
        } _crtc_mode_s;
 
408
        CARD8   _crtc_mode;                         /* CR17 */
 
409
    } _crtc_mode_u;
 
410
 
 
411
#define crtc_mode       _crtc_mode_u._crtc_mode
 
412
#define two_bk_cga      _crtc_mode_u._crtc_mode_s._two_bk_cga
 
413
#define four_bk_cga     _crtc_mode_u._crtc_mode_s._four_bk_cga
 
414
#define v_total_double  _crtc_mode_u._crtc_mode_s._v_total_double
 
415
#define count_by_two    _crtc_mode_u._crtc_mode_s._count_by_two
 
416
#define address_wrap    _crtc_mode_u._crtc_mode_s._address_wrap
 
417
#define byte_mode       _crtc_mode_u._crtc_mode_s._byte_mode
 
418
#define hardware_reset  _crtc_mode_u._crtc_mode_s._hardware_reset
 
419
 
 
420
    CARD8   line_compare_0_7;                       /* CR18 (unused) */
 
421
 
 
422
    union {
 
423
        struct {
 
424
            CARD8       _graphics_mode_enable   : 1;
 
425
            CARD8       _attribute_byte_mda     : 1;
 
426
            CARD8       _line_graphics_enable   : 1;
 
427
            CARD8       _background_blink       : 1;
 
428
            CARD8                               : 1;
 
429
            CARD8       _pel_panning_compat     : 1;
 
430
            CARD8       _pixel_clock_double     : 1;
 
431
            CARD8       p4_p5_source_select     : 1;
 
432
        } _mode_control_s;
 
433
        CARD8   _mode_control;
 
434
    } _mode_control_u;                              /* AR10 */
 
435
 
 
436
#define mode_control            _mode_control_u._mode_control
 
437
#define graphics_mode_enable    _mode_control_u._mode_control_s._graphics_mode_enable
 
438
#define pixel_clock_double      _mode_control_u._mode_control_s._pixel_clock_double
 
439
    
 
440
    CARD8   screen_border_color;                    /* AR11 */
 
441
    CARD8   enable_color_plane;                     /* AR12 */
 
442
    CARD8   horizontal_pixel_pan;                   /* AR13 */
 
443
    
 
444
    union {
 
445
        struct {
 
446
            CARD8   _write_mode             : 2;
 
447
            CARD8                           : 1;
 
448
            CARD8   _read_mode              : 1;
 
449
            CARD8   _odd_even_addressing    : 1;
 
450
            CARD8   _shift_register_mode    : 1;
 
451
            CARD8   _color_mode_256         : 1;
 
452
            CARD8                           : 1;
 
453
        } _mode_register_s;
 
454
        CARD8   _mode_register;
 
455
    } _mode_register_u;                             /* GR5 */
 
456
    
 
457
#define mode_register       _mode_register_u._mode_register
 
458
#define color_mode_256      _mode_register_u._mode_register_s._color_mode_256
 
459
#define odd_even_addressing _mode_register_u._mode_register_s._odd_even_addressing
 
460
 
 
461
    union {
 
462
        struct {
 
463
            CARD8   _graphics_enable        : 1;
 
464
            CARD8   _chain_odd_even         : 1;
 
465
            CARD8   _memory_address_select  : 2;
 
466
            CARD8                           : 4;
 
467
        } _misc_register_s;
 
468
        CARD8   _misc_register;
 
469
    } _misc_register_u;                             /* GR6 */
 
470
 
 
471
#define misc_register       _misc_register_u._misc_register
 
472
#define graphics_enable     _misc_register_u._misc_register_s._graphics_enable
 
473
#define chain_odd_even      _misc_register_u._misc_register_s._chain_odd_even
 
474
#define memory_address_select _misc_register_u._misc_register_s._memory_address_select
 
475
    
 
476
    CARD8       color_dont_care;                    /* GR7 */
 
477
    
 
478
    union {
 
479
        struct {
 
480
            CARD8   _dot_clock_8_9          : 1;
 
481
            CARD8                           : 1;
 
482
            CARD8   _shifter_load_16        : 1;
 
483
            CARD8   _dot_clock_divide_2     : 1;
 
484
            CARD8   _shifter_load_32        : 1;
 
485
            CARD8   _display_off            : 1;
 
486
            CARD8                           : 2;
 
487
        } _clock_mode_s;
 
488
        CARD8   _clock_mode;
 
489
    } _clock_mode_u;                                /* SR1 */
 
490
 
 
491
#define clock_mode          _clock_mode_u._clock_mode
 
492
#define dot_clock_8_9       _clock_mode_u._clock_mode_s._dot_clock_8_9
 
493
#define shifter_load_16     _clock_mode_u._clock_mode_s._shifter_load_16
 
494
#define dot_clock_divide_2  _clock_mode_u._clock_mode_s._dot_clock_divide_2
 
495
#define shifter_load_32     _clock_mode_u._clock_mode_s._shifter_load_32
 
496
#define display_off         _clock_mode_u._clock_mode_s._display_off
 
497
 
 
498
    CARD8   color_plane_w_enable;                   /* SR2 */
 
499
    
 
500
    union {
 
501
        struct {
 
502
            CARD8                           : 1;
 
503
            CARD8   _extended_memory_size   : 1;
 
504
            CARD8   _odd_even_disable       : 1;
 
505
            CARD8   _chain_4_enable         : 1;
 
506
            CARD8                           : 4;
 
507
        } _memory_mode_s;
 
508
        CARD8   _memory_mode;
 
509
    } _memory_mode_u;                               /* SR4 */
 
510
 
 
511
#define memory_mode         _memory_mode_u._memory_mode
 
512
#define extended_memory_sz  _memory_mode_u._memory_mode_s._extended_memory_size
 
513
#define odd_even_disable    _memory_mode_u._memory_mode_s._odd_even_disable
 
514
#define chain_4_enable      _memory_mode_u._memory_mode_s._chain_4_enable
 
515
    
 
516
    union {
 
517
        struct {
 
518
            CARD8   _enhanced_text_mode     : 1;
 
519
            CARD8   _enhanced_graphics_mode : 1;
 
520
            CARD8   _graphics_mode_32k      : 1;
 
521
            CARD8   _graphics_mode_64k      : 1;
 
522
            CARD8   _graphics_mode_true     : 1;
 
523
            CARD8   _graphics_mode_interlaced: 1;
 
524
            CARD8   _graphics_mode_hw_cursor: 1;
 
525
            CARD8   _graphics_mode_linear   : 1;
 
526
        } _graphics_mode_s;
 
527
        CARD8   _graphics_mode;
 
528
    } _graphics_mode_u;                         /* SR6 */
 
529
 
 
530
#define graphics_mode           _graphics_mode_u._graphics_mode
 
531
#define enhanced_text_mode      _graphics_mode_u._graphics_mode_s._enhanced_text_mode
 
532
#define enhanced_graphics_mode  _graphics_mode_u._graphics_mode_s._enhanced_graphics_mode
 
533
#define graphics_mode_32k       _graphics_mode_u._graphics_mode_s._graphics_mode_32k
 
534
#define graphics_mode_64k       _graphics_mode_u._graphics_mode_s._graphics_mode_64k
 
535
#define graphics_mode_true      _graphics_mode_u._graphics_mode_s._graphics_mode_true
 
536
#define graphics_mode_interlaced        _graphics_mode_u._graphics_mode_s._graphics_mode_interlaced
 
537
#define graphics_mode_hw_cursor _graphics_mode_u._graphics_mode_s._graphics_mode_hw_cursor
 
538
#define graphics_mode_linear    _graphics_mode_u._graphics_mode_s._graphics_mode_linear
 
539
 
 
540
    union {
 
541
        struct {
 
542
            CARD8   _external_dac_reference : 1;
 
543
            CARD8   _high_speed_dac_0       : 1;
 
544
            CARD8   _direct_color_24bit     : 1;
 
545
            CARD8   _multi_line_prefetch    : 1;
 
546
            CARD8   _extended_video_div_2   : 1;
 
547
            CARD8   _ramdac_power_save      : 1;
 
548
            CARD8                           : 1;
 
549
            CARD8   _merge_video_fifo       : 1;
 
550
        } _misc_control_0_s;
 
551
        CARD8   _misc_control_0;
 
552
    } _misc_control_0_u;                        /* SR7 */
 
553
 
 
554
#define misc_control_0      _misc_control_0_u._misc_control_0
 
555
#define external_dac_reference  _misc_control_0_u._misc_control_0_s._external_dac_reference
 
556
#define high_speed_dac_0            _misc_control_0_u._misc_control_0_s._high_speed_dac_0
 
557
#define direct_color_24bit          _misc_control_0_u._misc_control_0_s._direct_color_24bit
 
558
#define multi_line_prefetch         _misc_control_0_u._misc_control_0_s._multi_line_prefetch
 
559
#define extended_video_div_2        _misc_control_0_u._misc_control_0_s._extended_video_div_2
 
560
#define ramdac_power_save           _misc_control_0_u._misc_control_0_s._ramdac_power_save
 
561
#define merge_video_fifo            _misc_control_0_u._misc_control_0_s._merge_video_fifo
 
562
 
 
563
    union {
 
564
        struct {
 
565
            CARD8   _crt_engine_threshold_high_0_3  : 4;
 
566
            CARD8   _crt_cpu_threshold_low_0_3      : 4;
 
567
        } _crt_cpu_threshold_control_0_s;
 
568
        CARD8   _crt_cpu_threshold_control_0;
 
569
    } _crt_cpu_threshold_control_0_u;           /* SR8 */
 
570
    
 
571
#define crt_cpu_threshold_control_0     _crt_cpu_threshold_control_0_u._crt_cpu_threshold_control_0
 
572
#define crt_engine_threshold_high_0_3   _crt_cpu_threshold_control_0_u._crt_cpu_threshold_control_0_s._crt_engine_threshold_high_0_3
 
573
#define crt_cpu_threshold_low_0_3       _crt_cpu_threshold_control_0_u._crt_cpu_threshold_control_0_s._crt_cpu_threshold_low_0_3
 
574
 
 
575
    union {
 
576
        struct {
 
577
            CARD8   _crt_cpu_threshold_high_0_3 : 4;
 
578
            CARD8   _ascii_attribute_threshold_0_2 : 3;
 
579
            CARD8   _true_color_32bpp       : 1;
 
580
        } _crt_cpu_threshold_control_1_s;
 
581
        CARD8   _crt_cpu_threshold_control_1;
 
582
    } _crt_cpu_threshold_control_1_u;           /* SR9 */
 
583
 
 
584
#define crt_cpu_threshold_control_1 _crt_cpu_threshold_control_1_u._crt_cpu_threshold_control_1
 
585
#define crt_cpu_threshold_high_0_3  _crt_cpu_threshold_control_1_u._crt_cpu_threshold_control_1_s._crt_cpu_threshold_high_0_3
 
586
#define ascii_attribute_threshold_0_2   _crt_cpu_threshold_control_1_u._crt_cpu_threshold_control_1_s._ascii_attribute_threshold_0_2
 
587
#define true_color_32bpp            _crt_cpu_threshold_control_1_u._crt_cpu_threshold_control_1_s._true_color_32bpp
 
588
 
 
589
    union {
 
590
        struct {
 
591
            CARD8   _v_total_10             : 1;
 
592
            CARD8   _v_display_end_10       : 1;
 
593
            CARD8   _v_blank_start_10       : 1;
 
594
            CARD8   _v_retrace_start_10     : 1;
 
595
            CARD8   _screen_off_8_11        : 4;
 
596
        } _extended_crt_overflow_s;
 
597
        CARD8   _extended_crt_overflow;
 
598
    } _extended_crt_overflow_u;                     /* SRA */
 
599
 
 
600
#define extended_crt_overflow       _extended_crt_overflow_u._extended_crt_overflow
 
601
#define v_total_10                  _extended_crt_overflow_u._extended_crt_overflow_s._v_total_10
 
602
#define v_display_end_10            _extended_crt_overflow_u._extended_crt_overflow_s._v_display_end_10
 
603
#define v_blank_start_10            _extended_crt_overflow_u._extended_crt_overflow_s._v_blank_start_10
 
604
#define v_retrace_start_10          _extended_crt_overflow_u._extended_crt_overflow_s._v_retrace_start_10
 
605
#define screen_off_8_11             _extended_crt_overflow_u._extended_crt_overflow_s._screen_off_8_11
 
606
 
 
607
    union {
 
608
        struct {
 
609
            CARD8   _cpu_bitblt_enable      : 1;    /* enable CPU bitblt */
 
610
            CARD8   _packed_16_color_enable : 1;    /* 2 pixels per byte? */
 
611
            CARD8   _io_gating              : 1;    /* when write buffer not empty */
 
612
            CARD8   _dual_segment_enable    : 1;    /* ? */
 
613
            CARD8   _true_color_modulation  : 1;    /* ? */
 
614
            CARD8   _memory_mapped_mode     : 2;    /* mmio enable */
 
615
            CARD8   _true_color_order       : 1;    /* 0: RGB 1: BGR */
 
616
        } _misc_control_1_s;
 
617
        CARD8   _misc_control_1;            /* SRB */
 
618
    } _misc_control_1_u;
 
619
    
 
620
#define misc_control_1  _misc_control_1_u._misc_control_1
 
621
#define cpu_bitblt_enable   _misc_control_1_u._misc_control_1_s._cpu_bitblt_enable
 
622
#define memory_mapped_mode  _misc_control_1_u._misc_control_1_s._memory_mapped_mode
 
623
#define true_color_modulation   _misc_control_1_u._misc_control_1_s._true_color_modulation
 
624
#define true_color_order    _misc_control_1_u._misc_control_1_s._true_color_order
 
625
    
 
626
    union {
 
627
        struct {
 
628
            CARD8   _sync_reset_enable      : 1;
 
629
            CARD8   _memory_configuration   : 3;
 
630
#define SIS_MEMORY_CONFIG_1M_1BANK  0
 
631
#define SIS_MEMORY_CONFIG_2M_2BANK  1
 
632
#define SIS_MEMORY_CONFIG_4M_2BANK  2
 
633
#define SIS_MEMORY_CONFIG_2M_1BANK  5
 
634
#define SIS_MEMORY_CONFIG_4M_1BANK  6
 
635
#define SIS_MEMORY_CONFIG_8M_2BANK  7
 
636
            CARD8   _test_mode_enable       : 1;
 
637
            CARD8   _read_ahead_enable      : 1;
 
638
            CARD8   _text_mode_16bit_enable : 1;
 
639
            CARD8   _graphics_mode_32bit_enable : 1;
 
640
        } _misc_control_2_s;
 
641
        CARD8   _misc_control_2;
 
642
    } _misc_control_2_u;                    /* SRC */
 
643
 
 
644
#define misc_control_2          _misc_control_2_u._misc_control_2
 
645
#define sync_reset_enable       _misc_control_2_u._misc_control_2_s._sync_reset_enable
 
646
#define memory_configuration    _misc_control_2_u._misc_control_2_s._memory_configuration
 
647
#define test_mode_enable        _misc_control_2_u._misc_control_2_s._test_mode_enable
 
648
#define read_ahead_enable       _misc_control_2_u._misc_control_2_s._read_ahead_enable
 
649
#define text_mode_16bit_enable  _misc_control_2_u._misc_control_2_s._text_mode_16bit_enable
 
650
#define graphics_mode_32bit_enable  _misc_control_2_u._misc_control_2_s._graphics_mode_32bit_enable
 
651
 
 
652
    union ddc_and_power_control_u {
 
653
        struct {
 
654
            CARD8   _ddc_clk_programming    : 1;
 
655
            CARD8   _ddc_data_programming   : 1;
 
656
            CARD8                           : 1;
 
657
            CARD8   _acpi_enable            : 1;
 
658
            CARD8   _kbd_cursor_activate    : 1;
 
659
            CARD8   _video_memory_activate  : 1;
 
660
            CARD8   _vga_standby            : 1;
 
661
            CARD8   _vga_suspend            : 1;
 
662
        } _ddc_and_power_control_s;
 
663
        CARD8   _ddc_and_power_control;
 
664
    } _ddc_and_power_control_u;             /* SR11 */
 
665
    
 
666
#define ddc_and_power_control       _ddc_and_power_control_u._ddc_and_power_control
 
667
#define ddc_clk_programming         _ddc_and_power_control_u._ddc_and_power_control_s._ddc_clk_programming
 
668
#define ddc_data_programming        _ddc_and_power_control_u._ddc_and_power_control_s._ddc_data_programming
 
669
#define acpi_enable                 _ddc_and_power_control_u._ddc_and_power_control_s._acpi_enable
 
670
#define kbd_cursor_activate         _ddc_and_power_control_u._ddc_and_power_control_s._kbd_cursor_activate
 
671
#define video_memory_activate       _ddc_and_power_control_u._ddc_and_power_control_s._video_memory_activate
 
672
#define vga_standby                 _ddc_and_power_control_u._ddc_and_power_control_s._vga_standby
 
673
#define vga_suspend                 _ddc_and_power_control_u._ddc_and_power_control_s._vga_suspend
 
674
    
 
675
    union {
 
676
        struct {
 
677
            CARD8   _h_total_8              : 1;
 
678
            CARD8   _h_display_end_8        : 1;
 
679
            CARD8   _h_blank_start_8        : 1;
 
680
            CARD8   _h_sync_start_8         : 1;
 
681
            CARD8   _h_blank_end_6          : 1;
 
682
            CARD8   _h_retrace_skew         : 3;
 
683
        } _extended_horizontal_overflow_s;
 
684
        CARD8   _extended_horizontal_overflow;
 
685
    } _extended_horizontal_overflow_u;              /* SR12 */
 
686
#define extended_horizontal_overflow    _extended_horizontal_overflow_u._extended_horizontal_overflow
 
687
#define h_total_8                       _extended_horizontal_overflow_u._extended_horizontal_overflow_s._h_total_8
 
688
#define h_display_end_8                 _extended_horizontal_overflow_u._extended_horizontal_overflow_s._h_display_end_8
 
689
#define h_blank_start_8                 _extended_horizontal_overflow_u._extended_horizontal_overflow_s._h_blank_start_8
 
690
#define h_sync_start_8          _extended_horizontal_overflow_u._extended_horizontal_overflow_s._h_sync_start_8
 
691
#define h_blank_end_6                   _extended_horizontal_overflow_u._extended_horizontal_overflow_s._h_blank_end_6
 
692
#define h_retrace_skew                  _extended_horizontal_overflow_u._extended_horizontal_overflow_s._h_retrace_skew
 
693
 
 
694
    union {
 
695
        struct {
 
696
            CARD8                           : 6;
 
697
            CARD8   _vclk_post_scale_2      : 1;
 
698
            CARD8   _mclk_post_scale_2      : 1;
 
699
        } _extended_clock_generator_s;
 
700
        CARD8   _extended_clock_generator;
 
701
    } _extended_clock_generator_u;                  /* SR13 */
 
702
 
 
703
#define extended_clock_generator         _extended_clock_generator_u._extended_clock_generator
 
704
#define vclk_post_scale_2                _extended_clock_generator_u._extended_clock_generator_s._vclk_post_scale_2
 
705
#define mclk_post_scale_2                _extended_clock_generator_u._extended_clock_generator_s._mclk_post_scale_2
 
706
 
 
707
    CARD8   cursor_0_red;                           /* SR14 */
 
708
    CARD8   cursor_0_green;                         /* SR15 */
 
709
    CARD8   cursor_0_blue;                          /* SR16 */
 
710
    
 
711
    CARD8   cursor_1_red;                           /* SR17 */
 
712
    CARD8   cursor_1_green;                         /* SR18 */
 
713
    CARD8   cursor_1_blue;                          /* SR19 */
 
714
    
 
715
    CARD8   cursor_h_start_0_7;                     /* SR1A */
 
716
    union {
 
717
        struct {
 
718
            CARD8   _cursor_h_start_8_11    : 4;
 
719
            CARD8                           : 3;
 
720
            CARD8   _cursor_mmio_enable     : 1;
 
721
        } _cusor_h_start_1_s;
 
722
        CARD8   _cursor_h_start_1;
 
723
    } _cursor_h_start_1_u;                          /* SR1B */
 
724
 
 
725
#define cursor_h_start_1                _cursor_h_start_1_u._cursor_h_start_1
 
726
#define cursor_h_start_8_11             _cursor_h_start_1_u._cursor_h_start_1_s._cursor_h_start_8_11
 
727
    
 
728
    CARD8   cursor_h_preset_0_5;                    /* SR1C */
 
729
    
 
730
    CARD8   cursor_v_start_0_7;                     /* SR1D */
 
731
    
 
732
    union {
 
733
        struct {
 
734
            CARD8   _cursor_v_start_8_10    : 3;
 
735
            CARD8   _cursor_side_pattern    : 1;
 
736
            CARD8   _cursor_pattern         : 4;
 
737
        } _cusor_v_start_1_s;
 
738
        CARD8   _cursor_v_start_1;
 
739
    } _cursor_v_start_1_u;                          /* SR1E */
 
740
 
 
741
#define cursor_v_start_1                _cursor_v_start_1_u._cursor_v_start_1
 
742
    
 
743
    CARD8   cursor_v_preset_0_5;                    /* SR1F */
 
744
 
 
745
    CARD8   linear_base_19_26;                      /* SR20 */
 
746
 
 
747
    union {
 
748
        struct {
 
749
            CARD8   _linear_base_27_31      : 5;
 
750
            CARD8   _linear_aperture        : 3;
 
751
#define SIS_LINEAR_APERTURE_512K        0
 
752
#define SIS_LINEAR_APERTURE_1M  1
 
753
#define SIS_LINEAR_APERTURE_2M  2
 
754
#define SIS_LINEAR_APERTURE_4M  3
 
755
#define SIS_LINEAR_APERTURE_8M  4
 
756
        } _linear_base_1_s;
 
757
        CARD8   _linear_base_1;
 
758
    } _linear_base_1_u;                             /* SR21 */
 
759
    
 
760
#define linear_base_1       _linear_base_1_u._linear_base_1
 
761
#define linear_base_27_31   _linear_base_1_u._linear_base_1_s._linear_base_27_31
 
762
#define linear_aperture     _linear_base_1_u._linear_base_1_s._linear_aperture
 
763
 
 
764
    union {
 
765
        struct {
 
766
            CARD8   _screen_start_addr_20   : 1;
 
767
            CARD8                           : 3;
 
768
            CARD8   _continuous_mem_access  : 1;
 
769
            CARD8                           : 1;
 
770
            CARD8   _power_down_dac         : 1;
 
771
            CARD8                           : 1;
 
772
        } _graphics_engine_0_s;
 
773
        CARD8   _graphics_engine_0;
 
774
    } _graphics_engine_0_u;                         /* SR26 */
 
775
 
 
776
#define graphics_engine_0       _graphics_engine_0_u._graphics_engine_0
 
777
 
 
778
    
 
779
    union {
 
780
        struct {
 
781
            CARD8   _screen_start_addr_16_19: 4;
 
782
            CARD8   _logical_screen_width   : 2;
 
783
#define SIS_LOG_SCREEN_WIDTH_1024       0
 
784
#define SIS_LOG_SCREEN_WIDTH_2048       1
 
785
#define SIS_LOG_SCREEN_WIDTH_4096       2
 
786
            CARD8   _graphics_prog_enable   : 1;
 
787
            CARD8   _turbo_queue_enable     : 1;
 
788
        } _graphics_engine_1_s;
 
789
        CARD8   _graphics_engine_1;
 
790
    } _graphics_engine_1_u;                         /* SR27 */
 
791
 
 
792
#define graphics_engine_1       _graphics_engine_1_u._graphics_engine_1
 
793
#define screen_start_addr_16_19 _graphics_engine_1_u._graphics_engine_1_s._screen_start_addr_16_19
 
794
#define logical_screen_width    _graphics_engine_1_u._graphics_engine_1_s._logical_screen_width
 
795
#define graphics_prog_enable    _graphics_engine_1_u._graphics_engine_1_s._graphics_prog_enable
 
796
#define turbo_queue_enable      _graphics_engine_1_u._graphics_engine_1_s._turbo_queue_enable
 
797
 
 
798
 
 
799
    union {
 
800
        struct {
 
801
            CARD8   _mclk_numerator         : 7;
 
802
            CARD8   _mclk_divide_by_2       : 1;
 
803
        } _internal_mclk_0_s;
 
804
        CARD8   _internal_mclk_0;
 
805
    } _internal_mclk_0_u;                           /* SR28 */
 
806
 
 
807
#define internal_mclk_0     _internal_mclk_0_u._internal_mclk_0
 
808
#define mclk_numerator      _internal_mclk_0_u._internal_mclk_0_s._mclk_numerator
 
809
#define mclk_divide_by_2    _internal_mclk_0_u._internal_mclk_0_s._mclk_divide_by_2
 
810
    
 
811
    union {
 
812
        struct {
 
813
            CARD8   _mclk_denominator       : 5;
 
814
            CARD8   _mclk_post_scale        : 2;
 
815
#define SIS_MCLK_POST_SCALE_1       0
 
816
#define SIS_MCLK_POST_SCALE_2       1
 
817
#define SIS_MCLK_POST_SCALE_3       2
 
818
#define SIS_MCLK_POST_SCALE_4       3
 
819
            CARD8   _mclk_vco_gain          : 1;
 
820
        } _internal_mclk_1_s;
 
821
        CARD8   _internal_mclk_1;
 
822
    } _internal_mclk_1_u;                   /* SR29 */
 
823
 
 
824
#define internal_mclk_1     _internal_mclk_1_u._internal_mclk_1
 
825
#define mclk_denominator    _internal_mclk_1_u._internal_mclk_1_s._mclk_denominator
 
826
#define mclk_post_scale     _internal_mclk_1_u._internal_mclk_1_s._mclk_post_scale
 
827
#define mclk_vco_gain       _internal_mclk_1_u._internal_mclk_1_s._mclk_vco_gain
 
828
    
 
829
    union {
 
830
        struct {
 
831
            CARD8   _vclk_numerator         : 7;
 
832
            CARD8   _vclk_divide_by_2       : 1;
 
833
        } _internal_vclk_0_s;
 
834
        CARD8   _internal_vclk_0;
 
835
    } _internal_vclk_0_u;                   /* SR2A */
 
836
 
 
837
#define internal_vclk_0     _internal_vclk_0_u._internal_vclk_0
 
838
#define vclk_numerator      _internal_vclk_0_u._internal_vclk_0_s._vclk_numerator
 
839
#define vclk_divide_by_2    _internal_vclk_0_u._internal_vclk_0_s._vclk_divide_by_2
 
840
    
 
841
    union {
 
842
        struct {
 
843
            CARD8   _vclk_denominator       : 5;
 
844
            CARD8   _vclk_post_scale        : 2;
 
845
#define SIS_VCLK_POST_SCALE_1       0
 
846
#define SIS_VCLK_POST_SCALE_2       1
 
847
#define SIS_VCLK_POST_SCALE_3       2
 
848
#define SIS_VCLK_POST_SCALE_4       3
 
849
            CARD8   _vclk_vco_gain          : 1;
 
850
        } _internal_vclk_1_s;
 
851
        CARD8   _internal_vclk_1;
 
852
    } _internal_vclk_1_u;                   /* SR2B */
 
853
 
 
854
#define internal_vclk_1     _internal_vclk_1_u._internal_vclk_1
 
855
#define vclk_denominator    _internal_vclk_1_u._internal_vclk_1_s._vclk_denominator
 
856
#define vclk_post_scale     _internal_vclk_1_u._internal_vclk_1_s._vclk_post_scale
 
857
#define vclk_vco_gain       _internal_vclk_1_u._internal_vclk_1_s._vclk_vco_gain
 
858
    
 
859
    union {
 
860
        struct {
 
861
            CARD8   _extended_clock_select  : 2;
 
862
#define SIS_CLOCK_SELECT_INTERNAL   0
 
863
#define SIS_CLOCK_SELECT_25MHZ      1
 
864
#define SIS_CLOCK_SELECT_28MHZ      2
 
865
            CARD8   _disable_line_compare   : 1;
 
866
            CARD8   _disable_pci_read_t_o   : 1;
 
867
            CARD8   _cursor_start_addr_18_21: 4;
 
868
        } _misc_control_7_s;
 
869
        CARD8   _misc_control_7;
 
870
    } _misc_control_7_u;                            /* SR38 */
 
871
 
 
872
#define misc_control_7          _misc_control_7_u._misc_control_7
 
873
#define extended_clock_select   _misc_control_7_u._misc_control_7_s._extended_clock_select
 
874
#define disable_line_compare    _misc_control_7_u._misc_control_7_s._disable_line_compare
 
875
#define disable_pci_read_t_o    _misc_control_7_u._misc_control_7_s._disable_pci_read_t_o
 
876
#define cursor_start_addr_18_21 _misc_control_7_u._misc_control_7_s._cursor_start_addr_18_21
 
877
 
 
878
    union {
 
879
        struct {
 
880
            CARD8   _high_speed_dclk        : 1;
 
881
            CARD8   _sgram_block_write      : 1;
 
882
            CARD8   _cursor_start_addr_22   : 1;
 
883
            CARD8   _dram_texture_read      : 1;
 
884
            CARD8   _sgram_16mb             : 1;
 
885
            CARD8   _agp_signal_delay       : 2;
 
886
            CARD8   _dclk_off               : 1;
 
887
        } _misc_control_11_s;
 
888
        CARD8   _misc_control_11;
 
889
    } _misc_control_11_u;                           /* SR3E */
 
890
 
 
891
#define misc_control_11         _misc_control_11_u._misc_control_11
 
892
#define high_speed_dclk         _misc_control_11_u._misc_control_11_s._high_speed_dclk
 
893
#define sgram_block_write       _misc_control_11_u._misc_control_11_s.__sgram_block_write
 
894
#define cursor_start_addr_22    _misc_control_11_u._misc_control_11_s._cursor_start_addr_22
 
895
#define dram_texture_read       _misc_control_11_u._misc_control_11_s._dram_texture_read
 
896
#define sgram_16mb              _misc_control_11_u._misc_control_11_s._sgram_16mb
 
897
#define agp_signal_delay        _misc_control_11_u._misc_control_11_s._agp_signal_delay
 
898
#define dclk_off                _misc_control_11_u._misc_control_11_s._dclk_off
 
899
    
 
900
    union {
 
901
        struct {
 
902
            CARD8                           : 1;
 
903
            CARD8   _flat_panel_low_enable  : 1;
 
904
            CARD8   _crt_cpu_threshold_low_4: 1;
 
905
            CARD8   _crt_engine_threshold_high_4: 1;
 
906
            CARD8   _crt_cpu_threshold_high_4   : 1;
 
907
            CARD8   _crt_threshold_full_control : 2;
 
908
#define SIS_CRT_32_STAGE_THRESHOLD  0
 
909
#define SIS_CRT_64_STAGE_THRESHOLD  1
 
910
#define SIS_CRT_63_STAGE_THRESHOLD  2
 
911
#define SIS_CRT_256_STAGE_THRESHOLD 3
 
912
            CARD8   _high_speed_dac_1       : 1;
 
913
        } _misc_control_12_s;
 
914
        CARD8   _misc_control_12;
 
915
    } _misc_control_12_u;                           /* SR3F */
 
916
#define misc_control_12         _misc_control_12_u._misc_control_12
 
917
#define flat_panel_low_enable   _misc_control_12_u._misc_control_12_s._flat_panel_low_enable
 
918
#define crt_cpu_threshold_low_4 _misc_control_12_u._misc_control_12_s._crt_cpu_threshold_low_4
 
919
#define crt_engine_threshold_high_4 _misc_control_12_u._misc_control_12_s._crt_engine_threshold_high_4
 
920
#define crt_cpu_threshold_high_4    _misc_control_12_u._misc_control_12_s._crt_cpu_threshold_high_4
 
921
#define crt_threshold_full_control  _misc_control_12_u._misc_control_12_s._crt_threshold_full_control
 
922
#define high_speed_dac_1            _misc_control_12_u._misc_control_12_s._high_speed_dac_1
 
923
    
 
924
    /* computed values */
 
925
    CARD16          ge_screen_pitch;
 
926
    CARD8           bits_per_pixel;
 
927
    CARD8           depth;
 
928
    CARD8           double_pixel_mode;
 
929
    CARD16          pixel_width;
 
930
} SisCrtc;
 
931
 
 
932
#define crtc_v_total(crtc)    ((crtc)->v_total_0_7 | \
 
933
                               ((crtc)->v_total_8 << 8) | \
 
934
                               ((crtc)->v_total_9 << 9) | \
 
935
                               ((crtc)->v_total_10 << 10))
 
936
    
 
937
#define crtc_set_v_total(crtc,v) { \
 
938
    ((crtc))->v_total_0_7 = (v); \
 
939
    ((crtc))->v_total_8 = (v) >> 8; \
 
940
    ((crtc))->v_total_9 = (v) >> 9; \
 
941
    ((crtc))->v_total_10 = (v) >> 10; \
 
942
}
 
943
    
 
944
#define crtc_v_display_end(crtc) ((crtc)->v_display_end_0_7 | \
 
945
                                  ((crtc)->v_display_end_8 << 8) | \
 
946
                                  ((crtc)->v_display_end_9 << 9) | \
 
947
                                  ((crtc)->v_display_end_10 << 10))
 
948
 
 
949
#define crtc_set_v_display_end(crtc,v) {\
 
950
    ((crtc))->v_display_end_0_7 = (v); \
 
951
    ((crtc))->v_display_end_8 = (v) >> 8; \
 
952
    ((crtc))->v_display_end_9 = (v) >> 9; \
 
953
    ((crtc))->v_display_end_10 = (v) >> 10; \
 
954
}
 
955
 
 
956
#define crtc_v_retrace_start(crtc)  ((crtc)->v_retrace_start_0_7 | \
 
957
                                     ((crtc)->v_retrace_start_8 << 8) | \
 
958
                                     ((crtc)->v_retrace_start_9 << 9) | \
 
959
                                     ((crtc)->v_retrace_start_10 << 10))
 
960
 
 
961
#define crtc_set_v_retrace_start(crtc,v) {\
 
962
    ((crtc))->v_retrace_start_0_7 = (v); \
 
963
    ((crtc))->v_retrace_start_8 = (v) >> 8; \
 
964
    ((crtc))->v_retrace_start_9 = (v) >> 9; \
 
965
    ((crtc))->v_retrace_start_10 = (v) >> 10; \
 
966
}
 
967
 
 
968
#define crtc_v_blank_start(crtc)  ((crtc)->v_blank_start_0_7 | \
 
969
                                   ((crtc)->v_blank_start_8 << 8) | \
 
970
                                   ((crtc)->v_blank_start_9 << 9) | \
 
971
                                   ((crtc)->v_blank_start_10 << 10))
 
972
 
 
973
#define crtc_set_v_blank_start(crtc,v) {\
 
974
    ((crtc))->v_blank_start_0_7 = (v); \
 
975
    ((crtc))->v_blank_start_8 = (v) >> 8; \
 
976
    ((crtc))->v_blank_start_9 = (v) >> 9; \
 
977
    ((crtc))->v_blank_start_10 = (v) >> 10; \
 
978
}
 
979
 
 
980
#define crtc_h_total(crtc) ((crtc)->h_total_0_7 | \
 
981
                            ((crtc)->h_total_8 << 8))
 
982
 
 
983
#define crtc_set_h_total(crtc,v) {\
 
984
    ((crtc))->h_total_0_7 = (v); \
 
985
    ((crtc))->h_total_8 = (v) >> 8; \
 
986
}
 
987
 
 
988
#define crtc_h_display_end(crtc) ((crtc)->h_display_end_0_7 | \
 
989
                                  ((crtc)->h_display_end_8 << 8))
 
990
 
 
991
#define crtc_set_h_display_end(crtc,v) {\
 
992
    ((crtc))->h_display_end_0_7 = (v); \
 
993
    ((crtc))->h_display_end_8 = (v) >> 8; \
 
994
}
 
995
 
 
996
#define crtc_h_blank_start(crtc) ((crtc)->h_blank_start_0_7 | \
 
997
                                  ((crtc)->h_blank_start_8 << 8))
 
998
 
 
999
#define crtc_set_h_blank_start(crtc,v) {\
 
1000
    ((crtc))->h_blank_start_0_7 = (v); \
 
1001
    ((crtc))->h_blank_start_8 = (v) >> 8; \
 
1002
}
 
1003
 
 
1004
#define crtc_h_blank_end(crtc)  ((crtc)->h_blank_end_0_4 | \
 
1005
                                 ((crtc)->h_blank_end_5 << 5))
 
1006
 
 
1007
#define crtc_set_h_blank_end(crtc,v) {\
 
1008
    ((crtc))->h_blank_end_0_4 = (v); \
 
1009
    ((crtc))->h_blank_end_5 = (v) >> 5; \
 
1010
}
 
1011
 
 
1012
#define crtc_h_sync_start(crtc) ((crtc)->h_sync_start_0_7 | \
 
1013
                                 ((crtc)->h_sync_start_8 << 8))
 
1014
 
 
1015
#define crtc_set_h_sync_start(crtc,v) {\
 
1016
    ((crtc))->h_sync_start_0_7 = (v); \
 
1017
    ((crtc))->h_sync_start_8 = (v) >> 8; \
 
1018
}
 
1019
 
 
1020
#define crtc_h_sync_end(crtc) ((crtc)->h_sync_end_0_4)
 
1021
 
 
1022
#define crtc_set_h_sync_end(crtc,v) {\
 
1023
    ((crtc))->h_sync_end_0_4 = (v); \
 
1024
}
 
1025
 
 
1026
#define crtc_screen_off(crtc)    ((crtc)->screen_off_0_7 | \
 
1027
                                  ((crtc)->screen_off_8_11 << 8))
 
1028
 
 
1029
#define crtc_set_screen_off(crtc,v) {\
 
1030
    ((crtc))->screen_off_0_7 = (v); \
 
1031
    ((crtc))->screen_off_8_11 = (v) >> 8; \
 
1032
}
 
1033
 
 
1034
#define crtc_ge_screen_width(crtc) ((crtc)->ge_screen_width_0_1 | \
 
1035
                                    ((crtc)->ge_screen_width_2 << 2))
 
1036
 
 
1037
#define crtc_set_ge_screen_width(crtc,v) { \
 
1038
    (crtc)->ge_screen_width_0_1 = (v); \
 
1039
    (crtc)->ge_screen_width_2 = (v) >> 2; \
 
1040
}
 
1041
 
 
1042
#define crtc_h_start_fifo_fetch(crtc) ((crtc)->h_start_fifo_fetch_0_7 | \
 
1043
                                       ((crtc)->h_start_fifo_fetch_8 << 8))
 
1044
 
 
1045
#define crtc_set_h_start_fifo_fetch(crtc,v) {\
 
1046
    (crtc)->h_start_fifo_fetch_0_7 = (v); \
 
1047
    (crtc)->h_start_fifo_fetch_8 = (v) >> 8; \
 
1048
}
 
1049
 
 
1050
#define crtc_start_address(crtc)    ((crtc)->start_address_0_7 | \
 
1051
                                     ((crtc)->start_address_8_15 << 8) | \
 
1052
                                     ((crtc)->start_address_16_19 << 16))
 
1053
 
 
1054
#define crtc_set_start_address(crtc,v) {\
 
1055
    (crtc)->start_address_0_7 = (v); \
 
1056
    (crtc)->start_address_8_15 = (v) >> 8; \
 
1057
    (crtc)->start_address_16_19 = (v) >> 16; \
 
1058
}
 
1059
 
 
1060
#define crtc_line_compare(crtc)    ((crtc)->line_compare_0_7 | \
 
1061
                                    ((crtc)->line_compare_8 << 8) | \
 
1062
                                    ((crtc)->line_compare_9 << 9) | \
 
1063
                                    ((crtc)->line_compare_10 << 10))
 
1064
 
 
1065
#define crtc_set_line_compare(crtc,v) { \
 
1066
    ((crtc))->line_compare_0_7 = (v); \
 
1067
    ((crtc))->line_compare_8 = (v) >> 8; \
 
1068
    ((crtc))->line_compare_9 = (v) >> 9; \
 
1069
    ((crtc))->line_compare_10 = (v) >> 10; \
 
1070
}
 
1071
 
 
1072
#define crtc_set_cursor_start_addr(crtc,v) { \
 
1073
    (crtc)->cursor_start_addr_18_21 = (v) >> 18; \
 
1074
    (crtc)->cursor_start_addr_22 = (v) >> 22; \
 
1075
}
 
1076
 
 
1077
#define _sisOutb(v,r)       outb(v,r)
 
1078
#define _sisInb(r)          inb(r)
 
1079
 
 
1080
#define SIS_DAC_INDEX_READ  0x47
 
1081
#define SIS_DAC_INDEX_WRITE 0x48
 
1082
#define SIS_DAC_DATA        0x49
 
1083
 
 
1084
#define GetCrtc(sisc,i)     _sisReadIndexRegister ((sisc)->io_base+0x54,i)
 
1085
#define PutCrtc(sisc,i,v)   _sisWriteIndexRegister ((sisc)->io_base+0x54,i,v)
 
1086
 
 
1087
#define GetSrtc(sisc,i)     _sisReadIndexRegister ((sisc)->io_base+0x44,i)
 
1088
#define PutSrtc(sisc,i,v)   _sisWriteIndexRegister ((sisc)->io_base+0x44,i,v)
 
1089
 
 
1090
#define GetArtc(sisc,i)     _sisReadArtc ((sisc)->io_base+0x40,i)
 
1091
#define PutArtc(sisc,i,v)   _sisWriteArtc ((sisc)->io_base+0x40,i,v)
 
1092
 
 
1093
#define GetGrtc(sisc,i)     _sisReadIndexRegister ((sisc)->io_base+0x4e,i)
 
1094
#define PutGrtc(sisc,i,v)   _sisWriteIndexRegister ((sisc)->io_base+0x4e,i,v)
 
1095
 
 
1096
#define _sisWaitVRetrace(sisc)
 
1097
 
 
1098
#define LockSis(sisc)
 
1099
#define UnlockSis(sisc)
 
1100
 
 
1101
typedef struct _sisTiming {
 
1102
    /* label */
 
1103
    int         horizontal;
 
1104
    int         vertical;
 
1105
    int         rate;
 
1106
    /* horizontal timing */
 
1107
    int         hfp;        /* front porch */
 
1108
    int         hbp;        /* back porch */
 
1109
    int         hblank;     /* blanking */
 
1110
    /* vertical timing */
 
1111
    int         vfp;        /* front porch */
 
1112
    int         vbp;        /* back porch */
 
1113
    int         vblank;     /* blanking */
 
1114
} SisTiming;
 
1115
 
 
1116
#define SIS_TEXT_SAVE   (64*1024)
 
1117
 
 
1118
typedef struct _sisSave {
 
1119
    CARD8       srb;
 
1120
    CARD8       sr5;
 
1121
    SisCrtc     crtc;
 
1122
    CARD8       text_save[SIS_TEXT_SAVE];
 
1123
} SisSave;
 
1124
 
 
1125
typedef struct _sisCardInfo {
 
1126
    SisPtr  sis;
 
1127
    int     memory;
 
1128
    CARD8   *frameBuffer;
 
1129
    CARD8   *registers;
 
1130
    VOL32   *cpu_bitblt;
 
1131
    CARD32  io_base;
 
1132
    SisSave save;
 
1133
} SisCardInfo;
 
1134
 
 
1135
typedef struct _sisScreenInfo {
 
1136
    CARD8       *cursor_base;
 
1137
    CARD32      cursor_off;
 
1138
    CARD8       *expand;
 
1139
    CARD32      expand_off;
 
1140
    int         expand_len;
 
1141
    SisCursor   cursor;
 
1142
} SisScreenInfo;
 
1143
 
 
1144
#define getSisCardInfo(kd)      ((SisCardInfo *) ((kd)->card->driver))
 
1145
#define sisCardInfo(kd)         SisCardInfo *sisc = getSisCardInfo(kd)
 
1146
 
 
1147
#define getSisScreenInfo(kd)    ((SisScreenInfo *) ((kd)->screen->driver))
 
1148
#define sisScreenInfo(kd)       SisScreenInfo *siss = getSisScreenInfo(kd)
 
1149
 
 
1150
Bool    sisCardInit (KdCardInfo *);
 
1151
Bool    sisScreenInit (KdScreenInfo *);
 
1152
Bool    sisEnable (ScreenPtr pScreen);
 
1153
void    sisDisable (ScreenPtr pScreen);
 
1154
void    sisFini (ScreenPtr pScreen);
 
1155
 
 
1156
Bool    sisCursorInit (ScreenPtr pScreen);
 
1157
void    sisCursorEnable (ScreenPtr pScreen);
 
1158
void    sisCursorDisable (ScreenPtr pScreen);
 
1159
void    sisCursorFini (ScreenPtr pScreen);
 
1160
void    sisRecolorCursor (ScreenPtr pScreen, int ndef, xColorItem *pdefs);
 
1161
 
 
1162
Bool    sisDrawInit (ScreenPtr pScreen);
 
1163
void    sisDrawEnable (ScreenPtr pScreen);
 
1164
void    sisDrawSync (ScreenPtr pScreen);
 
1165
void    sisDrawDisable (ScreenPtr pScreen);
 
1166
void    sisDrawFini (ScreenPtr pScreen);
 
1167
 
 
1168
void    sisGetColors (ScreenPtr pScreen, int fb, int ndef, xColorItem *pdefs);
 
1169
void    sisPutColors (ScreenPtr pScreen, int fb, int ndef, xColorItem *pdefs);
 
1170
 
 
1171
void    SISInitCard (KdCardAttr *attr);
 
1172
 
 
1173
CARD8   _sisReadIndexRegister (CARD32 base, CARD8 index);
 
1174
void    _sisWriteIndexRegister (CARD32 base, CARD8 index, CARD8 value);
 
1175
CARD8   _sisReadArtc (CARD32 base, CARD8 index);
 
1176
void    _sisWriteArtc (CARD32 base, CARD8 index, CARD8 value);
 
1177
 
 
1178
extern KdCardFuncs  sisFuncs;
 
1179
 
 
1180
/*
 
1181
 * sisclock.c
 
1182
 */
 
1183
void 
 
1184
sisGetClock (unsigned long clock, SisCrtc *crtc);
 
1185
 
 
1186
void
 
1187
sisEngThresh (SisCrtc *crtc, unsigned long vclk, int bpp);
 
1188
    
 
1189
/*
 
1190
 * siscurs.c
 
1191
 */
 
1192
 
 
1193
Bool
 
1194
sisCursorInit (ScreenPtr pScreen);
 
1195
 
 
1196
void
 
1197
sisCursorEnable (ScreenPtr pScreen);
 
1198
 
 
1199
void
 
1200
sisCursorDisable (ScreenPtr pScreen);
 
1201
 
 
1202
void
 
1203
sisCursorFini (ScreenPtr pScreen);
 
1204
 
 
1205
/* sisdraw.c */
 
1206
Bool
 
1207
sisDrawInit (ScreenPtr pScreen);
 
1208
 
 
1209
void
 
1210
sisDrawEnable (ScreenPtr pScreen);
 
1211
 
 
1212
void
 
1213
sisDrawDisable (ScreenPtr pScreen);
 
1214
 
 
1215
void
 
1216
sisDrawFini (ScreenPtr pScreen);
 
1217
 
 
1218
#endif /* _SIS_H_ */