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* ALSA modem driver for Intel ICH (i8x0) chipsets
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* Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
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* This is modified (by Sasha Khapyorsky <sashak@alsa-project.org>) version
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* of ALSA ICH sound driver intel8x0.c .
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/moduleparam.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/ac97_codec.h>
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#include <sound/info.h>
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#include <sound/initval.h>
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MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
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MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; "
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"SiS 7013; NVidia MCP/2/2S/3 modems");
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MODULE_LICENSE("GPL");
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MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
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"{Intel,82901AB-ICH0},"
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"{Intel,82801BA-ICH2},"
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"{Intel,82801CA-ICH3},"
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"{Intel,82801DB-ICH4},"
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"{NVidia,NForce Modem},"
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"{NVidia,NForce2 Modem},"
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"{NVidia,NForce2s Modem},"
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"{NVidia,NForce3 Modem},"
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static int index = -2; /* Exclude the first card */
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static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
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static int ac97_clock;
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module_param(index, int, 0444);
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MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard.");
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module_param(id, charp, 0444);
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MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard.");
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module_param(ac97_clock, int, 0444);
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MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
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/* just for backward compatibility */
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module_param(enable, bool, 0444);
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enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
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#define ICHREG(x) ICH_REG_##x
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#define DEFINE_REGSET(name,base) \
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ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
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ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
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ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
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ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
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ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
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ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
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ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
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/* busmaster blocks */
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DEFINE_REGSET(OFF, 0); /* offset */
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/* values for each busmaster block */
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#define ICH_REG_LVI_MASK 0x1f
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#define ICH_FIFOE 0x10 /* FIFO error */
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#define ICH_BCIS 0x08 /* buffer completion interrupt status */
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#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
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#define ICH_CELV 0x02 /* current equals last valid */
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#define ICH_DCH 0x01 /* DMA controller halted */
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#define ICH_REG_PIV_MASK 0x1f /* mask */
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#define ICH_IOCE 0x10 /* interrupt on completion enable */
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#define ICH_FEIE 0x08 /* fifo error interrupt enable */
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#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
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#define ICH_RESETREGS 0x02 /* reset busmaster registers */
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#define ICH_STARTBM 0x01 /* start busmaster operation */
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#define ICH_REG_GLOB_CNT 0x3c /* dword - global control */
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#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
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#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
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#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
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#define ICH_ACLINK 0x00000008 /* AClink shut off */
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#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
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#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
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#define ICH_GIE 0x00000001 /* GPI interrupt enable */
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#define ICH_REG_GLOB_STA 0x40 /* dword - global status */
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#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
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#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
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#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
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#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
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#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
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#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
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#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
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#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
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#define ICH_MD3 0x00020000 /* modem power down semaphore */
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#define ICH_AD3 0x00010000 /* audio power down semaphore */
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#define ICH_RCS 0x00008000 /* read completion status */
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#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
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#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
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#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
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#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
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#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
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#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
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#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
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#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
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#define ICH_POINT 0x00000040 /* playback interrupt */
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#define ICH_PIINT 0x00000020 /* capture interrupt */
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#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
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#define ICH_MOINT 0x00000004 /* modem playback interrupt */
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#define ICH_MIINT 0x00000002 /* modem capture interrupt */
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#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
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#define ICH_REG_ACC_SEMA 0x44 /* byte - codec write semaphore */
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#define ICH_CAS 0x01 /* codec access semaphore */
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#define ICH_MAX_FRAGS 32 /* max hw frags */
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enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT };
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enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT };
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#define get_ichdev(substream) (substream->runtime->private_data)
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unsigned int ichd; /* ich device number */
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unsigned long reg_offset; /* offset to bmaddr */
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u32 *bdbar; /* CPU address (32bit) */
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unsigned int bdbar_addr; /* PCI bus address (32bit) */
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struct snd_pcm_substream *substream;
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unsigned int physbuf; /* physical address (32bit) */
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unsigned int fragsize;
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unsigned int fragsize1;
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unsigned int position;
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unsigned int ack_bit;
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unsigned int roff_sr;
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unsigned int roff_picb;
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unsigned int int_sta_mask; /* interrupt status mask */
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unsigned int ali_slot; /* ALI DMA slot */
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struct snd_ac97 *ac97;
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unsigned int device_type;
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void __iomem *bmaddr;
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struct snd_card *card;
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struct snd_pcm *pcm[2];
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struct ichdev ichd[2];
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unsigned int in_ac97_init: 1;
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struct snd_ac97_bus *ac97_bus;
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struct snd_ac97 *ac97;
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struct snd_dma_buffer bdbars;
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u32 int_sta_reg; /* interrupt status register */
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u32 int_sta_mask; /* interrupt status mask */
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unsigned int pcm_pos_shift;
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static struct pci_device_id snd_intel8x0m_ids[] = {
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{ PCI_VDEVICE(INTEL, 0x2416), DEVICE_INTEL }, /* 82801AA */
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{ PCI_VDEVICE(INTEL, 0x2426), DEVICE_INTEL }, /* 82901AB */
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{ PCI_VDEVICE(INTEL, 0x2446), DEVICE_INTEL }, /* 82801BA */
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{ PCI_VDEVICE(INTEL, 0x2486), DEVICE_INTEL }, /* ICH3 */
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{ PCI_VDEVICE(INTEL, 0x24c6), DEVICE_INTEL }, /* ICH4 */
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{ PCI_VDEVICE(INTEL, 0x24d6), DEVICE_INTEL }, /* ICH5 */
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{ PCI_VDEVICE(INTEL, 0x266d), DEVICE_INTEL }, /* ICH6 */
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{ PCI_VDEVICE(INTEL, 0x27dd), DEVICE_INTEL }, /* ICH7 */
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{ PCI_VDEVICE(INTEL, 0x7196), DEVICE_INTEL }, /* 440MX */
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{ PCI_VDEVICE(AMD, 0x7446), DEVICE_INTEL }, /* AMD768 */
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{ PCI_VDEVICE(SI, 0x7013), DEVICE_SIS }, /* SI7013 */
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{ PCI_VDEVICE(NVIDIA, 0x01c1), DEVICE_NFORCE }, /* NFORCE */
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{ PCI_VDEVICE(NVIDIA, 0x0069), DEVICE_NFORCE }, /* NFORCE2 */
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{ PCI_VDEVICE(NVIDIA, 0x0089), DEVICE_NFORCE }, /* NFORCE2s */
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{ PCI_VDEVICE(NVIDIA, 0x00d9), DEVICE_NFORCE }, /* NFORCE3 */
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{ PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */
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{ PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */
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MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids);
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* Lowlevel I/O - busmaster
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static inline u8 igetbyte(struct intel8x0m *chip, u32 offset)
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return ioread8(chip->bmaddr + offset);
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static inline u16 igetword(struct intel8x0m *chip, u32 offset)
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return ioread16(chip->bmaddr + offset);
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static inline u32 igetdword(struct intel8x0m *chip, u32 offset)
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return ioread32(chip->bmaddr + offset);
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static inline void iputbyte(struct intel8x0m *chip, u32 offset, u8 val)
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iowrite8(val, chip->bmaddr + offset);
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static inline void iputword(struct intel8x0m *chip, u32 offset, u16 val)
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iowrite16(val, chip->bmaddr + offset);
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static inline void iputdword(struct intel8x0m *chip, u32 offset, u32 val)
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iowrite32(val, chip->bmaddr + offset);
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* Lowlevel I/O - AC'97 registers
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static inline u16 iagetword(struct intel8x0m *chip, u32 offset)
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return ioread16(chip->addr + offset);
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static inline void iaputword(struct intel8x0m *chip, u32 offset, u16 val)
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iowrite16(val, chip->addr + offset);
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* access to AC97 codec via normal i/o (for ICH and SIS7013)
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/* return the GLOB_STA bit for the corresponding codec */
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static unsigned int get_ich_codec_bit(struct intel8x0m *chip, unsigned int codec)
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static unsigned int codec_bit[3] = {
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ICH_PCR, ICH_SCR, ICH_TCR
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if (snd_BUG_ON(codec >= 3))
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return codec_bit[codec];
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static int snd_intel8x0m_codec_semaphore(struct intel8x0m *chip, unsigned int codec)
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codec = get_ich_codec_bit(chip, codec);
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if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
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/* Anyone holding a semaphore for 1 msec should be shot... */
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if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
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/* access to some forbidden (non existant) ac97 registers will not
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* reset the semaphore. So even if you don't get the semaphore, still
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* continue the access. We don't need the semaphore anyway. */
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snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
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igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
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iagetword(chip, 0); /* clear semaphore flag */
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/* I don't care about the semaphore */
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static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
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struct intel8x0m *chip = ac97->private_data;
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if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
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if (! chip->in_ac97_init)
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snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
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iaputword(chip, reg + ac97->num * 0x80, val);
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static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
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struct intel8x0m *chip = ac97->private_data;
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if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
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if (! chip->in_ac97_init)
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snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
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res = iagetword(chip, reg + ac97->num * 0x80);
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if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
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/* reset RCS and preserve other R/WC bits */
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iputdword(chip, ICHREG(GLOB_STA),
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tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
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if (! chip->in_ac97_init)
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snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
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if (reg == AC97_GPIO_STATUS)
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iagetword(chip, 0); /* clear semaphore */
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static void snd_intel8x0_setup_periods(struct intel8x0m *chip, struct ichdev *ichdev)
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u32 *bdbar = ichdev->bdbar;
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unsigned long port = ichdev->reg_offset;
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iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
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if (ichdev->size == ichdev->fragsize) {
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ichdev->ack_reload = ichdev->ack = 2;
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ichdev->fragsize1 = ichdev->fragsize >> 1;
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for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
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bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
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bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
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ichdev->fragsize1 >> chip->pcm_pos_shift);
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bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
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bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
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ichdev->fragsize1 >> chip->pcm_pos_shift);
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ichdev->ack_reload = ichdev->ack = 1;
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ichdev->fragsize1 = ichdev->fragsize;
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for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
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bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
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bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
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ichdev->fragsize >> chip->pcm_pos_shift);
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printk(KERN_DEBUG "bdbar[%i] = 0x%x [0x%x]\n",
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idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
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ichdev->frags = ichdev->size / ichdev->fragsize;
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iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
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iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
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ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
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ichdev->position = 0;
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printk(KERN_DEBUG "lvi_frag = %i, frags = %i, period_size = 0x%x, "
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"period_size1 = 0x%x\n",
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ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
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/* clear interrupts */
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iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
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static inline void snd_intel8x0_update(struct intel8x0m *chip, struct ichdev *ichdev)
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unsigned long port = ichdev->reg_offset;
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civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
447
if (civ == ichdev->civ) {
448
// snd_printd("civ same %d\n", civ);
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ichdev->civ &= ICH_REG_LVI_MASK;
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step = civ - ichdev->civ;
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step += ICH_REG_LVI_MASK + 1;
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// snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
461
ichdev->position += step * ichdev->fragsize1;
462
ichdev->position %= ichdev->size;
464
ichdev->lvi &= ICH_REG_LVI_MASK;
465
iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
466
for (i = 0; i < step; i++) {
468
ichdev->lvi_frag %= ichdev->frags;
469
ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf +
473
printk(KERN_DEBUG "new: bdbar[%i] = 0x%x [0x%x], "
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"prefetch = %i, all = 0x%x, 0x%x\n",
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ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
476
ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
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inl(port + 4), inb(port + ICH_REG_OFF_CR));
479
if (--ichdev->ack == 0) {
480
ichdev->ack = ichdev->ack_reload;
484
if (ack && ichdev->substream) {
485
spin_unlock(&chip->reg_lock);
486
snd_pcm_period_elapsed(ichdev->substream);
487
spin_lock(&chip->reg_lock);
489
iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
492
static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
494
struct intel8x0m *chip = dev_id;
495
struct ichdev *ichdev;
499
spin_lock(&chip->reg_lock);
500
status = igetdword(chip, chip->int_sta_reg);
501
if (status == 0xffffffff) { /* we are not yet resumed */
502
spin_unlock(&chip->reg_lock);
505
if ((status & chip->int_sta_mask) == 0) {
507
iputdword(chip, chip->int_sta_reg, status);
508
spin_unlock(&chip->reg_lock);
512
for (i = 0; i < chip->bdbars_count; i++) {
513
ichdev = &chip->ichd[i];
514
if (status & ichdev->int_sta_mask)
515
snd_intel8x0_update(chip, ichdev);
519
iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
520
spin_unlock(&chip->reg_lock);
529
static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
531
struct intel8x0m *chip = snd_pcm_substream_chip(substream);
532
struct ichdev *ichdev = get_ichdev(substream);
533
unsigned char val = 0;
534
unsigned long port = ichdev->reg_offset;
537
case SNDRV_PCM_TRIGGER_START:
538
case SNDRV_PCM_TRIGGER_RESUME:
539
val = ICH_IOCE | ICH_STARTBM;
541
case SNDRV_PCM_TRIGGER_STOP:
542
case SNDRV_PCM_TRIGGER_SUSPEND:
545
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
548
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
549
val = ICH_IOCE | ICH_STARTBM;
554
iputbyte(chip, port + ICH_REG_OFF_CR, val);
555
if (cmd == SNDRV_PCM_TRIGGER_STOP) {
556
/* wait until DMA stopped */
557
while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
558
/* reset whole DMA things */
559
iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
564
static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
565
struct snd_pcm_hw_params *hw_params)
567
return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
570
static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
572
return snd_pcm_lib_free_pages(substream);
575
static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
577
struct intel8x0m *chip = snd_pcm_substream_chip(substream);
578
struct ichdev *ichdev = get_ichdev(substream);
581
ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;
583
ptr = ichdev->fragsize1 - ptr1;
586
ptr += ichdev->position;
587
if (ptr >= ichdev->size)
589
return bytes_to_frames(substream->runtime, ptr);
592
static int snd_intel8x0m_pcm_prepare(struct snd_pcm_substream *substream)
594
struct intel8x0m *chip = snd_pcm_substream_chip(substream);
595
struct snd_pcm_runtime *runtime = substream->runtime;
596
struct ichdev *ichdev = get_ichdev(substream);
598
ichdev->physbuf = runtime->dma_addr;
599
ichdev->size = snd_pcm_lib_buffer_bytes(substream);
600
ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
601
snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate);
602
snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0);
603
snd_intel8x0_setup_periods(chip, ichdev);
607
static struct snd_pcm_hardware snd_intel8x0m_stream =
609
.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
610
SNDRV_PCM_INFO_BLOCK_TRANSFER |
611
SNDRV_PCM_INFO_MMAP_VALID |
612
SNDRV_PCM_INFO_PAUSE |
613
SNDRV_PCM_INFO_RESUME),
614
.formats = SNDRV_PCM_FMTBIT_S16_LE,
615
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT,
620
.buffer_bytes_max = 64 * 1024,
621
.period_bytes_min = 32,
622
.period_bytes_max = 64 * 1024,
629
static int snd_intel8x0m_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
631
static unsigned int rates[] = { 8000, 9600, 12000, 16000 };
632
static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
633
.count = ARRAY_SIZE(rates),
637
struct snd_pcm_runtime *runtime = substream->runtime;
640
ichdev->substream = substream;
641
runtime->hw = snd_intel8x0m_stream;
642
err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
643
&hw_constraints_rates);
646
runtime->private_data = ichdev;
650
static int snd_intel8x0m_playback_open(struct snd_pcm_substream *substream)
652
struct intel8x0m *chip = snd_pcm_substream_chip(substream);
654
return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]);
657
static int snd_intel8x0m_playback_close(struct snd_pcm_substream *substream)
659
struct intel8x0m *chip = snd_pcm_substream_chip(substream);
661
chip->ichd[ICHD_MDMOUT].substream = NULL;
665
static int snd_intel8x0m_capture_open(struct snd_pcm_substream *substream)
667
struct intel8x0m *chip = snd_pcm_substream_chip(substream);
669
return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]);
672
static int snd_intel8x0m_capture_close(struct snd_pcm_substream *substream)
674
struct intel8x0m *chip = snd_pcm_substream_chip(substream);
676
chip->ichd[ICHD_MDMIN].substream = NULL;
681
static struct snd_pcm_ops snd_intel8x0m_playback_ops = {
682
.open = snd_intel8x0m_playback_open,
683
.close = snd_intel8x0m_playback_close,
684
.ioctl = snd_pcm_lib_ioctl,
685
.hw_params = snd_intel8x0_hw_params,
686
.hw_free = snd_intel8x0_hw_free,
687
.prepare = snd_intel8x0m_pcm_prepare,
688
.trigger = snd_intel8x0_pcm_trigger,
689
.pointer = snd_intel8x0_pcm_pointer,
692
static struct snd_pcm_ops snd_intel8x0m_capture_ops = {
693
.open = snd_intel8x0m_capture_open,
694
.close = snd_intel8x0m_capture_close,
695
.ioctl = snd_pcm_lib_ioctl,
696
.hw_params = snd_intel8x0_hw_params,
697
.hw_free = snd_intel8x0_hw_free,
698
.prepare = snd_intel8x0m_pcm_prepare,
699
.trigger = snd_intel8x0_pcm_trigger,
700
.pointer = snd_intel8x0_pcm_pointer,
704
struct ich_pcm_table {
706
struct snd_pcm_ops *playback_ops;
707
struct snd_pcm_ops *capture_ops;
708
size_t prealloc_size;
709
size_t prealloc_max_size;
713
static int __devinit snd_intel8x0_pcm1(struct intel8x0m *chip, int device,
714
struct ich_pcm_table *rec)
721
sprintf(name, "Intel ICH - %s", rec->suffix);
723
strcpy(name, "Intel ICH");
724
err = snd_pcm_new(chip->card, name, device,
725
rec->playback_ops ? 1 : 0,
726
rec->capture_ops ? 1 : 0, &pcm);
730
if (rec->playback_ops)
731
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
732
if (rec->capture_ops)
733
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
735
pcm->private_data = chip;
737
pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
739
sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
741
strcpy(pcm->name, chip->card->shortname);
742
chip->pcm[device] = pcm;
744
snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
745
snd_dma_pci_data(chip->pci),
747
rec->prealloc_max_size);
752
static struct ich_pcm_table intel_pcms[] __devinitdata = {
755
.playback_ops = &snd_intel8x0m_playback_ops,
756
.capture_ops = &snd_intel8x0m_capture_ops,
757
.prealloc_size = 32 * 1024,
758
.prealloc_max_size = 64 * 1024,
762
static int __devinit snd_intel8x0_pcm(struct intel8x0m *chip)
764
int i, tblsize, device, err;
765
struct ich_pcm_table *tbl, *rec;
771
switch (chip->device_type) {
774
tblsize = ARRAY_SIZE(nforce_pcms);
778
tblsize = ARRAY_SIZE(ali_pcms);
787
for (i = 0; i < tblsize; i++) {
789
if (i > 0 && rec->ac97_idx) {
790
/* activate PCM only when associated AC'97 codec */
791
if (! chip->ichd[rec->ac97_idx].ac97)
794
err = snd_intel8x0_pcm1(chip, device, rec);
800
chip->pcm_devs = device;
809
static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
811
struct intel8x0m *chip = bus->private_data;
812
chip->ac97_bus = NULL;
815
static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
817
struct intel8x0m *chip = ac97->private_data;
822
static int __devinit snd_intel8x0_mixer(struct intel8x0m *chip, int ac97_clock)
824
struct snd_ac97_bus *pbus;
825
struct snd_ac97_template ac97;
826
struct snd_ac97 *x97;
828
unsigned int glob_sta = 0;
829
static struct snd_ac97_bus_ops ops = {
830
.write = snd_intel8x0_codec_write,
831
.read = snd_intel8x0_codec_read,
834
chip->in_ac97_init = 1;
836
memset(&ac97, 0, sizeof(ac97));
837
ac97.private_data = chip;
838
ac97.private_free = snd_intel8x0_mixer_free_ac97;
839
ac97.scaps = AC97_SCAP_SKIP_AUDIO | AC97_SCAP_POWER_SAVE;
841
glob_sta = igetdword(chip, ICHREG(GLOB_STA));
843
if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0)
845
pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
846
if (ac97_clock >= 8000 && ac97_clock <= 48000)
847
pbus->clock = ac97_clock;
848
chip->ac97_bus = pbus;
850
ac97.pci = chip->pci;
851
ac97.num = glob_sta & ICH_SCR ? 1 : 0;
852
if ((err = snd_ac97_mixer(pbus, &ac97, &x97)) < 0) {
853
snd_printk(KERN_ERR "Unable to initialize codec #%d\n", ac97.num);
859
if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97) {
860
chip->ichd[ICHD_MDMIN].ac97 = x97;
861
chip->ichd[ICHD_MDMOUT].ac97 = x97;
864
chip->in_ac97_init = 0;
868
/* clear the cold-reset bit for the next chance */
869
if (chip->device_type != DEVICE_ALI)
870
iputdword(chip, ICHREG(GLOB_CNT),
871
igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
880
static int snd_intel8x0m_ich_chip_init(struct intel8x0m *chip, int probing)
882
unsigned long end_time;
883
unsigned int cnt, status, nstatus;
885
/* put logic to right state */
886
/* first clear status bits */
887
status = ICH_RCS | ICH_MIINT | ICH_MOINT;
888
cnt = igetdword(chip, ICHREG(GLOB_STA));
889
iputdword(chip, ICHREG(GLOB_STA), cnt & status);
891
/* ACLink on, 2 channels */
892
cnt = igetdword(chip, ICHREG(GLOB_CNT));
893
cnt &= ~(ICH_ACLINK);
894
/* finish cold or do warm reset */
895
cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
896
iputdword(chip, ICHREG(GLOB_CNT), cnt);
897
end_time = (jiffies + (HZ / 4)) + 1;
899
if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
901
schedule_timeout_uninterruptible(1);
902
} while (time_after_eq(end_time, jiffies));
903
snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
904
igetdword(chip, ICHREG(GLOB_CNT)));
909
/* wait for any codec ready status.
910
* Once it becomes ready it should remain ready
911
* as long as we do not disable the ac97 link.
913
end_time = jiffies + HZ;
915
status = igetdword(chip, ICHREG(GLOB_STA)) &
916
(ICH_PCR | ICH_SCR | ICH_TCR);
919
schedule_timeout_uninterruptible(1);
920
} while (time_after_eq(end_time, jiffies));
922
/* no codec is found */
923
snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
924
igetdword(chip, ICHREG(GLOB_STA)));
928
/* up to two codecs (modem cannot be tertiary with ICH4) */
929
nstatus = ICH_PCR | ICH_SCR;
931
/* wait for other codecs ready status. */
932
end_time = jiffies + HZ / 4;
933
while (status != nstatus && time_after_eq(end_time, jiffies)) {
934
schedule_timeout_uninterruptible(1);
935
status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
942
status |= get_ich_codec_bit(chip, chip->ac97->num);
943
/* wait until all the probed codecs are ready */
944
end_time = jiffies + HZ;
946
nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
947
(ICH_PCR | ICH_SCR | ICH_TCR);
948
if (status == nstatus)
950
schedule_timeout_uninterruptible(1);
951
} while (time_after_eq(end_time, jiffies));
954
if (chip->device_type == DEVICE_SIS) {
955
/* unmute the output on SIS7012 */
956
iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
962
static int snd_intel8x0_chip_init(struct intel8x0m *chip, int probing)
967
if ((err = snd_intel8x0m_ich_chip_init(chip, probing)) < 0)
969
iagetword(chip, 0); /* clear semaphore flag */
971
/* disable interrupts */
972
for (i = 0; i < chip->bdbars_count; i++)
973
iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
975
for (i = 0; i < chip->bdbars_count; i++)
976
iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
977
/* initialize Buffer Descriptor Lists */
978
for (i = 0; i < chip->bdbars_count; i++)
979
iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
983
static int snd_intel8x0_free(struct intel8x0m *chip)
989
/* disable interrupts */
990
for (i = 0; i < chip->bdbars_count; i++)
991
iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
993
for (i = 0; i < chip->bdbars_count; i++)
994
iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
997
free_irq(chip->irq, chip);
998
if (chip->bdbars.area)
999
snd_dma_free_pages(&chip->bdbars);
1001
pci_iounmap(chip->pci, chip->addr);
1003
pci_iounmap(chip->pci, chip->bmaddr);
1004
pci_release_regions(chip->pci);
1005
pci_disable_device(chip->pci);
1014
static int intel8x0m_suspend(struct pci_dev *pci, pm_message_t state)
1016
struct snd_card *card = pci_get_drvdata(pci);
1017
struct intel8x0m *chip = card->private_data;
1020
snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1021
for (i = 0; i < chip->pcm_devs; i++)
1022
snd_pcm_suspend_all(chip->pcm[i]);
1023
snd_ac97_suspend(chip->ac97);
1024
if (chip->irq >= 0) {
1025
free_irq(chip->irq, chip);
1028
pci_disable_device(pci);
1029
pci_save_state(pci);
1030
pci_set_power_state(pci, pci_choose_state(pci, state));
1034
static int intel8x0m_resume(struct pci_dev *pci)
1036
struct snd_card *card = pci_get_drvdata(pci);
1037
struct intel8x0m *chip = card->private_data;
1039
pci_set_power_state(pci, PCI_D0);
1040
pci_restore_state(pci);
1041
if (pci_enable_device(pci) < 0) {
1042
printk(KERN_ERR "intel8x0m: pci_enable_device failed, "
1043
"disabling device\n");
1044
snd_card_disconnect(card);
1047
pci_set_master(pci);
1048
if (request_irq(pci->irq, snd_intel8x0_interrupt,
1049
IRQF_SHARED, card->shortname, chip)) {
1050
printk(KERN_ERR "intel8x0m: unable to grab IRQ %d, "
1051
"disabling device\n", pci->irq);
1052
snd_card_disconnect(card);
1055
chip->irq = pci->irq;
1056
snd_intel8x0_chip_init(chip, 0);
1057
snd_ac97_resume(chip->ac97);
1059
snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1062
#endif /* CONFIG_PM */
1064
#ifdef CONFIG_PROC_FS
1065
static void snd_intel8x0m_proc_read(struct snd_info_entry * entry,
1066
struct snd_info_buffer *buffer)
1068
struct intel8x0m *chip = entry->private_data;
1071
snd_iprintf(buffer, "Intel8x0m\n\n");
1072
if (chip->device_type == DEVICE_ALI)
1074
tmp = igetdword(chip, ICHREG(GLOB_STA));
1075
snd_iprintf(buffer, "Global control : 0x%08x\n",
1076
igetdword(chip, ICHREG(GLOB_CNT)));
1077
snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
1078
snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
1079
tmp & ICH_PCR ? " primary" : "",
1080
tmp & ICH_SCR ? " secondary" : "",
1081
tmp & ICH_TCR ? " tertiary" : "",
1082
(tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
1085
static void __devinit snd_intel8x0m_proc_init(struct intel8x0m * chip)
1087
struct snd_info_entry *entry;
1089
if (! snd_card_proc_new(chip->card, "intel8x0m", &entry))
1090
snd_info_set_text_ops(entry, chip, snd_intel8x0m_proc_read);
1092
#else /* !CONFIG_PROC_FS */
1093
#define snd_intel8x0m_proc_init(chip)
1094
#endif /* CONFIG_PROC_FS */
1097
static int snd_intel8x0_dev_free(struct snd_device *device)
1099
struct intel8x0m *chip = device->device_data;
1100
return snd_intel8x0_free(chip);
1103
struct ich_reg_info {
1104
unsigned int int_sta_mask;
1105
unsigned int offset;
1108
static int __devinit snd_intel8x0m_create(struct snd_card *card,
1109
struct pci_dev *pci,
1110
unsigned long device_type,
1111
struct intel8x0m ** r_intel8x0)
1113
struct intel8x0m *chip;
1116
unsigned int int_sta_masks;
1117
struct ichdev *ichdev;
1118
static struct snd_device_ops ops = {
1119
.dev_free = snd_intel8x0_dev_free,
1121
static struct ich_reg_info intel_regs[2] = {
1123
{ ICH_MOINT, 0x10 },
1125
struct ich_reg_info *tbl;
1129
if ((err = pci_enable_device(pci)) < 0)
1132
chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1134
pci_disable_device(pci);
1137
spin_lock_init(&chip->reg_lock);
1138
chip->device_type = device_type;
1143
if ((err = pci_request_regions(pci, card->shortname)) < 0) {
1145
pci_disable_device(pci);
1149
if (device_type == DEVICE_ALI) {
1150
/* ALI5455 has no ac97 region */
1151
chip->bmaddr = pci_iomap(pci, 0, 0);
1155
if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
1156
chip->addr = pci_iomap(pci, 2, 0);
1158
chip->addr = pci_iomap(pci, 0, 0);
1160
snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
1161
snd_intel8x0_free(chip);
1164
if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
1165
chip->bmaddr = pci_iomap(pci, 3, 0);
1167
chip->bmaddr = pci_iomap(pci, 1, 0);
1168
if (!chip->bmaddr) {
1169
snd_printk(KERN_ERR "Controller space ioremap problem\n");
1170
snd_intel8x0_free(chip);
1175
if (request_irq(pci->irq, snd_intel8x0_interrupt, IRQF_SHARED,
1176
card->shortname, chip)) {
1177
snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1178
snd_intel8x0_free(chip);
1181
chip->irq = pci->irq;
1182
pci_set_master(pci);
1183
synchronize_irq(chip->irq);
1185
/* initialize offsets */
1186
chip->bdbars_count = 2;
1189
for (i = 0; i < chip->bdbars_count; i++) {
1190
ichdev = &chip->ichd[i];
1192
ichdev->reg_offset = tbl[i].offset;
1193
ichdev->int_sta_mask = tbl[i].int_sta_mask;
1194
if (device_type == DEVICE_SIS) {
1195
/* SiS 7013 swaps the registers */
1196
ichdev->roff_sr = ICH_REG_OFF_PICB;
1197
ichdev->roff_picb = ICH_REG_OFF_SR;
1199
ichdev->roff_sr = ICH_REG_OFF_SR;
1200
ichdev->roff_picb = ICH_REG_OFF_PICB;
1202
if (device_type == DEVICE_ALI)
1203
ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
1205
/* SIS7013 handles the pcm data in bytes, others are in words */
1206
chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
1208
/* allocate buffer descriptor lists */
1209
/* the start of each lists must be aligned to 8 bytes */
1210
if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1211
chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
1212
&chip->bdbars) < 0) {
1213
snd_intel8x0_free(chip);
1216
/* tables must be aligned to 8 bytes here, but the kernel pages
1217
are much bigger, so we don't care (on i386) */
1219
for (i = 0; i < chip->bdbars_count; i++) {
1220
ichdev = &chip->ichd[i];
1221
ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
1222
ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
1223
int_sta_masks |= ichdev->int_sta_mask;
1225
chip->int_sta_reg = ICH_REG_GLOB_STA;
1226
chip->int_sta_mask = int_sta_masks;
1228
if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
1229
snd_intel8x0_free(chip);
1233
if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1234
snd_intel8x0_free(chip);
1238
snd_card_set_dev(card, &pci->dev);
1244
static struct shortname_table {
1247
} shortnames[] __devinitdata = {
1248
{ PCI_DEVICE_ID_INTEL_82801AA_6, "Intel 82801AA-ICH" },
1249
{ PCI_DEVICE_ID_INTEL_82801AB_6, "Intel 82901AB-ICH0" },
1250
{ PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" },
1251
{ PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" },
1252
{ PCI_DEVICE_ID_INTEL_82801CA_6, "Intel 82801CA-ICH3" },
1253
{ PCI_DEVICE_ID_INTEL_82801DB_6, "Intel 82801DB-ICH4" },
1254
{ PCI_DEVICE_ID_INTEL_82801EB_6, "Intel ICH5" },
1255
{ PCI_DEVICE_ID_INTEL_ICH6_17, "Intel ICH6" },
1256
{ PCI_DEVICE_ID_INTEL_ICH7_19, "Intel ICH7" },
1257
{ 0x7446, "AMD AMD768" },
1258
{ PCI_DEVICE_ID_SI_7013, "SiS SI7013" },
1259
{ PCI_DEVICE_ID_NVIDIA_MCP1_MODEM, "NVidia nForce" },
1260
{ PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" },
1261
{ PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" },
1262
{ PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" },
1264
{ 0x5455, "ALi M5455" },
1265
{ 0x746d, "AMD AMD8111" },
1270
static int __devinit snd_intel8x0m_probe(struct pci_dev *pci,
1271
const struct pci_device_id *pci_id)
1273
struct snd_card *card;
1274
struct intel8x0m *chip;
1276
struct shortname_table *name;
1278
err = snd_card_create(index, id, THIS_MODULE, 0, &card);
1282
strcpy(card->driver, "ICH-MODEM");
1283
strcpy(card->shortname, "Intel ICH");
1284
for (name = shortnames; name->id; name++) {
1285
if (pci->device == name->id) {
1286
strcpy(card->shortname, name->s);
1290
strcat(card->shortname," Modem");
1292
if ((err = snd_intel8x0m_create(card, pci, pci_id->driver_data, &chip)) < 0) {
1293
snd_card_free(card);
1296
card->private_data = chip;
1298
if ((err = snd_intel8x0_mixer(chip, ac97_clock)) < 0) {
1299
snd_card_free(card);
1302
if ((err = snd_intel8x0_pcm(chip)) < 0) {
1303
snd_card_free(card);
1307
snd_intel8x0m_proc_init(chip);
1309
sprintf(card->longname, "%s at irq %i",
1310
card->shortname, chip->irq);
1312
if ((err = snd_card_register(card)) < 0) {
1313
snd_card_free(card);
1316
pci_set_drvdata(pci, card);
1320
static void __devexit snd_intel8x0m_remove(struct pci_dev *pci)
1322
snd_card_free(pci_get_drvdata(pci));
1323
pci_set_drvdata(pci, NULL);
1326
static struct pci_driver driver = {
1327
.name = "Intel ICH Modem",
1328
.id_table = snd_intel8x0m_ids,
1329
.probe = snd_intel8x0m_probe,
1330
.remove = __devexit_p(snd_intel8x0m_remove),
1332
.suspend = intel8x0m_suspend,
1333
.resume = intel8x0m_resume,
1338
static int __init alsa_card_intel8x0m_init(void)
1340
return pci_register_driver(&driver);
1343
static void __exit alsa_card_intel8x0m_exit(void)
1345
pci_unregister_driver(&driver);
1348
module_init(alsa_card_intel8x0m_init)
1349
module_exit(alsa_card_intel8x0m_exit)