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/******************************************************************************
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* Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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* Contact Information:
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*****************************************************************************/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <linux/delay.h>
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#include <linux/sched.h>
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#include <linux/skbuff.h>
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#include <linux/netdevice.h>
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#include <linux/wireless.h>
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#include <net/mac80211.h>
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#include <linux/etherdevice.h>
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#include <asm/unaligned.h>
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#include "iwl-eeprom.h"
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#include "iwl-helpers.h"
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#include "iwl-agn-led.h"
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#include "iwl-5000-hw.h"
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#include "iwl-6000-hw.h"
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/* Highest firmware API version supported */
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#define IWL5000_UCODE_API_MAX 2
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#define IWL5150_UCODE_API_MAX 2
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/* Lowest firmware API version supported */
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#define IWL5000_UCODE_API_MIN 1
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#define IWL5150_UCODE_API_MIN 1
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#define IWL5000_FW_PRE "iwlwifi-5000-"
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#define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
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#define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
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#define IWL5150_FW_PRE "iwlwifi-5150-"
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#define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
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#define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
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static const u16 iwl5000_default_queue_to_tx_fifo[] = {
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/* NIC configuration for 5000 series */
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void iwl5000_nic_config(struct iwl_priv *priv)
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spin_lock_irqsave(&priv->lock, flags);
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radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
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/* write radio config values to register */
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if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX)
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iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
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EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
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EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
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EEPROM_RF_CFG_DASH_MSK(radio_cfg));
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/* set CSR_HW_CONFIG_REG for uCode use */
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iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
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CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
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/* W/A : NIC is stuck in a reset state after Early PCIe power off
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* (PCIe power is lost before PERST# is asserted),
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* causing ME FW to lose ownership and not being able to obtain it back.
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iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
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APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
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~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
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spin_unlock_irqrestore(&priv->lock, flags);
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static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
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if ((address & INDIRECT_ADDRESS) == 0)
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switch (address & INDIRECT_TYPE_MSK) {
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offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
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case INDIRECT_GENERAL:
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offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
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case INDIRECT_REGULATORY:
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offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
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case INDIRECT_CALIBRATION:
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offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
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case INDIRECT_PROCESS_ADJST:
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offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
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case INDIRECT_OTHERS:
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offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
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IWL_ERR(priv, "illegal indirect type: 0x%X\n",
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address & INDIRECT_TYPE_MSK);
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/* translate the offset from words to byte */
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return (address & ADDRESS_MSK) + (offset << 1);
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u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
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struct iwl_eeprom_calib_hdr {
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hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
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EEPROM_5000_CALIB_ALL);
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static void iwl5000_gain_computation(struct iwl_priv *priv,
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u32 average_noise[NUM_RX_CHAINS],
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u16 min_average_noise_antenna_i,
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u32 min_average_noise,
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struct iwl_chain_noise_data *data = &priv->chain_noise_data;
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* Find Gain Code for the chains based on "default chain"
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for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) {
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if ((data->disconn_array[i])) {
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data->delta_gain_code[i] = 0;
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delta_g = (1000 * ((s32)average_noise[default_chain] -
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(s32)average_noise[i])) / 1500;
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/* bound gain by 2 bits value max, 3rd bit is sign */
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data->delta_gain_code[i] =
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min(abs(delta_g), (long) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
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/* set negative sign */
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data->delta_gain_code[i] |= (1 << 2);
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IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n",
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data->delta_gain_code[1], data->delta_gain_code[2]);
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if (!data->radio_write) {
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struct iwl_calib_chain_noise_gain_cmd cmd;
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memset(&cmd, 0, sizeof(cmd));
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cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
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cmd.hdr.first_group = 0;
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cmd.hdr.groups_num = 1;
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cmd.hdr.data_valid = 1;
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cmd.delta_gain_1 = data->delta_gain_code[1];
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cmd.delta_gain_2 = data->delta_gain_code[2];
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iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
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sizeof(cmd), &cmd, NULL);
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data->radio_write = 1;
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data->state = IWL_CHAIN_NOISE_CALIBRATED;
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data->chain_noise_a = 0;
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data->chain_noise_b = 0;
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data->chain_noise_c = 0;
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data->chain_signal_a = 0;
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data->chain_signal_b = 0;
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data->chain_signal_c = 0;
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data->beacon_count = 0;
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static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
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struct iwl_chain_noise_data *data = &priv->chain_noise_data;
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if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
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struct iwl_calib_chain_noise_reset_cmd cmd;
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memset(&cmd, 0, sizeof(cmd));
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cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
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cmd.hdr.first_group = 0;
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cmd.hdr.groups_num = 1;
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cmd.hdr.data_valid = 1;
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ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
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"Could not send REPLY_PHY_CALIBRATION_CMD\n");
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data->state = IWL_CHAIN_NOISE_ACCUMULATE;
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IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
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void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
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if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
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(info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
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*tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
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*tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
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static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
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.max_nrg_cck = 0, /* not used, set to 0 */
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.auto_corr_min_ofdm = 90,
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.auto_corr_min_ofdm_mrc = 170,
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.auto_corr_min_ofdm_x1 = 120,
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.auto_corr_min_ofdm_mrc_x1 = 240,
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.auto_corr_max_ofdm = 120,
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.auto_corr_max_ofdm_mrc = 210,
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.auto_corr_max_ofdm_x1 = 155,
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.auto_corr_max_ofdm_mrc_x1 = 290,
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.auto_corr_min_cck = 125,
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.auto_corr_max_cck = 200,
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.auto_corr_min_cck_mrc = 170,
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.auto_corr_max_cck_mrc = 400,
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.barker_corr_th_min = 190,
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.barker_corr_th_min_mrc = 390,
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static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
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.max_nrg_cck = 0, /* not used, set to 0 */
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.auto_corr_min_ofdm = 90,
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.auto_corr_min_ofdm_mrc = 170,
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.auto_corr_min_ofdm_x1 = 105,
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.auto_corr_min_ofdm_mrc_x1 = 220,
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.auto_corr_max_ofdm = 120,
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.auto_corr_max_ofdm_mrc = 210,
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/* max = min for performance bug in 5150 DSP */
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.auto_corr_max_ofdm_x1 = 105,
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.auto_corr_max_ofdm_mrc_x1 = 220,
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.auto_corr_min_cck = 125,
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.auto_corr_max_cck = 200,
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.auto_corr_min_cck_mrc = 170,
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.auto_corr_max_cck_mrc = 400,
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.barker_corr_th_min = 190,
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.barker_corr_th_min_mrc = 390,
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const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
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u32 address = eeprom_indirect_address(priv, offset);
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BUG_ON(address >= priv->cfg->eeprom_size);
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return &priv->eeprom[address];
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static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
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const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
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s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) -
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iwl_temp_calib_to_offset(priv);
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priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
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static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
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priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
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static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
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struct iwl_calib_xtal_freq_cmd cmd;
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(__le16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
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cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
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cmd.hdr.first_group = 0;
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cmd.hdr.groups_num = 1;
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cmd.hdr.data_valid = 1;
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cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
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cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
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return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
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(u8 *)&cmd, sizeof(cmd));
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static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
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struct iwl_calib_cfg_cmd calib_cfg_cmd;
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struct iwl_host_cmd cmd = {
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.id = CALIBRATION_CFG_CMD,
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.len = sizeof(struct iwl_calib_cfg_cmd),
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.data = &calib_cfg_cmd,
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memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
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calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
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calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
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calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
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calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
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return iwl_send_cmd(priv, &cmd);
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static void iwl5000_rx_calib_result(struct iwl_priv *priv,
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struct iwl_rx_mem_buffer *rxb)
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struct iwl_rx_packet *pkt = rxb_addr(rxb);
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struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
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int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
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/* reduce the size of the length field itself */
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/* Define the order in which the results will be sent to the runtime
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* uCode. iwl_send_calib_results sends them in a row according to their
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* index. We sort them here */
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switch (hdr->op_code) {
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case IWL_PHY_CALIBRATE_DC_CMD:
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index = IWL_CALIB_DC;
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case IWL_PHY_CALIBRATE_LO_CMD:
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index = IWL_CALIB_LO;
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case IWL_PHY_CALIBRATE_TX_IQ_CMD:
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index = IWL_CALIB_TX_IQ;
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case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
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index = IWL_CALIB_TX_IQ_PERD;
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case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
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index = IWL_CALIB_BASE_BAND;
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IWL_ERR(priv, "Unknown calibration notification %d\n",
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iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
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static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
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struct iwl_rx_mem_buffer *rxb)
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IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
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queue_work(priv->workqueue, &priv->restart);
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static int iwl5000_load_section(struct iwl_priv *priv,
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struct fw_desc *image,
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dma_addr_t phy_addr = image->p_addr;
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u32 byte_cnt = image->len;
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iwl_write_direct32(priv,
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FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
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iwl_write_direct32(priv,
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FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
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iwl_write_direct32(priv,
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FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
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phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
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iwl_write_direct32(priv,
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FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
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(iwl_get_dma_hi_addr(phy_addr)
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<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
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iwl_write_direct32(priv,
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FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
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1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
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1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
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FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
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iwl_write_direct32(priv,
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FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
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FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
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static int iwl5000_load_given_ucode(struct iwl_priv *priv,
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struct fw_desc *inst_image,
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struct fw_desc *data_image)
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ret = iwl5000_load_section(priv, inst_image,
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IWL50_RTC_INST_LOWER_BOUND);
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IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n");
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ret = wait_event_interruptible_timeout(priv->wait_command_queue,
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priv->ucode_write_complete, 5 * HZ);
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if (ret == -ERESTARTSYS) {
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IWL_ERR(priv, "Could not load the INST uCode section due "
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IWL_ERR(priv, "Could not load the INST uCode section\n");
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priv->ucode_write_complete = 0;
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ret = iwl5000_load_section(
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priv, data_image, IWL50_RTC_DATA_LOWER_BOUND);
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IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n");
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ret = wait_event_interruptible_timeout(priv->wait_command_queue,
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priv->ucode_write_complete, 5 * HZ);
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if (ret == -ERESTARTSYS) {
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IWL_ERR(priv, "Could not load the INST uCode section due "
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IWL_ERR(priv, "Could not load the DATA uCode section\n");
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priv->ucode_write_complete = 0;
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int iwl5000_load_ucode(struct iwl_priv *priv)
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/* check whether init ucode should be loaded, or rather runtime ucode */
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if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
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IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
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ret = iwl5000_load_given_ucode(priv,
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&priv->ucode_init, &priv->ucode_init_data);
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IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
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priv->ucode_type = UCODE_INIT;
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IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
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"Loading runtime ucode...\n");
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ret = iwl5000_load_given_ucode(priv,
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&priv->ucode_code, &priv->ucode_data);
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IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
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priv->ucode_type = UCODE_RT;
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void iwl5000_init_alive_start(struct iwl_priv *priv)
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/* Check alive response for "valid" sign from uCode */
535
if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
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/* We had an error bringing up the hardware, so take it
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* all the way back down so we can try again */
538
IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
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/* initialize uCode was loaded... verify inst image.
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* This is a paranoid check, because we would not have gotten the
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* "initialize" alive if code weren't properly loaded. */
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if (iwl_verify_ucode(priv)) {
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/* Runtime instruction load was bad;
547
* take it all the way back down so we can try again */
548
IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
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iwl_clear_stations_table(priv);
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ret = priv->cfg->ops->lib->alive_notify(priv);
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"Could not complete ALIVE transition: %d\n", ret);
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iwl5000_send_calib_cfg(priv);
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/* real restart (first load init_ucode) */
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queue_work(priv->workqueue, &priv->restart);
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static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
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int txq_id, u32 index)
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iwl_write_direct32(priv, HBUS_TARG_WRPTR,
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(index & 0xff) | (txq_id << 8));
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iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
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static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
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struct iwl_tx_queue *txq,
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int tx_fifo_id, int scd_retry)
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int txq_id = txq->q.id;
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int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
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iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
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(active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
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(tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
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(1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
587
IWL50_SCD_QUEUE_STTS_REG_MSK);
589
txq->sched_retry = scd_retry;
591
IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
592
active ? "Activate" : "Deactivate",
593
scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
596
int iwl5000_alive_notify(struct iwl_priv *priv)
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spin_lock_irqsave(&priv->lock, flags);
605
priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
606
a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
607
for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
609
iwl_write_targ_mem(priv, a, 0);
610
for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
612
iwl_write_targ_mem(priv, a, 0);
613
for (; a < priv->scd_base_addr +
614
IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
615
iwl_write_targ_mem(priv, a, 0);
617
iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
618
priv->scd_bc_tbls.dma >> 10);
620
/* Enable DMA channel */
621
for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
622
iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
623
FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
624
FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
626
/* Update FH chicken bits */
627
reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
628
iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
629
reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
631
iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
632
IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
633
iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
635
/* initiate the queues */
636
for (i = 0; i < priv->hw_params.max_txq_num; i++) {
637
iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
638
iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
639
iwl_write_targ_mem(priv, priv->scd_base_addr +
640
IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
641
iwl_write_targ_mem(priv, priv->scd_base_addr +
642
IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
645
IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
646
IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
648
IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
649
IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
652
iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
653
IWL_MASK(0, priv->hw_params.max_txq_num));
655
/* Activate all Tx DMA/FIFO channels */
656
priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
658
iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
660
/* map qos queues to fifos one-to-one */
661
for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
662
int ac = iwl5000_default_queue_to_tx_fifo[i];
663
iwl_txq_ctx_activate(priv, i);
664
iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
668
* TODO - need to initialize these queues and map them to FIFOs
669
* in the loop above, not only mark them as active. We do this
670
* because we want the first aggregation queue to be queue #10,
671
* but do not use 8 or 9 otherwise yet.
673
iwl_txq_ctx_activate(priv, 7);
674
iwl_txq_ctx_activate(priv, 8);
675
iwl_txq_ctx_activate(priv, 9);
677
spin_unlock_irqrestore(&priv->lock, flags);
680
iwl_send_wimax_coex(priv);
682
iwl5000_set_Xtal_calib(priv);
683
iwl_send_calib_results(priv);
688
int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
690
if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
691
priv->cfg->mod_params->num_of_queues <= IWL50_NUM_QUEUES)
692
priv->cfg->num_of_queues =
693
priv->cfg->mod_params->num_of_queues;
695
priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
696
priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
697
priv->hw_params.scd_bc_tbls_size =
698
priv->cfg->num_of_queues *
699
sizeof(struct iwl5000_scd_bc_tbl);
700
priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
701
priv->hw_params.max_stations = IWL5000_STATION_COUNT;
702
priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
704
priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
705
priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
707
priv->hw_params.max_bsm_size = 0;
708
priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
709
BIT(IEEE80211_BAND_5GHZ);
710
priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
712
priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
713
priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
714
priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
715
priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
717
if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
718
priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
720
/* Set initial sensitivity parameters */
721
/* Set initial calibration set */
722
switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
723
case CSR_HW_REV_TYPE_5150:
724
priv->hw_params.sens = &iwl5150_sensitivity;
725
priv->hw_params.calib_init_cfg =
728
BIT(IWL_CALIB_TX_IQ) |
729
BIT(IWL_CALIB_BASE_BAND);
733
priv->hw_params.sens = &iwl5000_sensitivity;
734
priv->hw_params.calib_init_cfg =
735
BIT(IWL_CALIB_XTAL) |
737
BIT(IWL_CALIB_TX_IQ) |
738
BIT(IWL_CALIB_TX_IQ_PERD) |
739
BIT(IWL_CALIB_BASE_BAND);
747
* iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
749
void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
750
struct iwl_tx_queue *txq,
753
struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
754
int write_ptr = txq->q.write_ptr;
755
int txq_id = txq->q.id;
758
u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
761
WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
763
if (txq_id != IWL_CMD_QUEUE_NUM) {
764
sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
765
sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
767
switch (sec_ctl & TX_CMD_SEC_MSK) {
771
case TX_CMD_SEC_TKIP:
775
len += WEP_IV_LEN + WEP_ICV_LEN;
780
bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
782
scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
784
if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
786
tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
789
void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
790
struct iwl_tx_queue *txq)
792
struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
793
int txq_id = txq->q.id;
794
int read_ptr = txq->q.read_ptr;
798
WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
800
if (txq_id != IWL_CMD_QUEUE_NUM)
801
sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
803
bc_ent = cpu_to_le16(1 | (sta_id << 12));
804
scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
806
if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
808
tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
811
static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
818
scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
820
tbl_dw_addr = priv->scd_base_addr +
821
IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
823
tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
826
tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
828
tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
830
iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
834
static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
836
/* Simply stop the queue, but don't change any configuration;
837
* the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
839
IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
840
(0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
841
(1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
844
int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
845
int tx_fifo, int sta_id, int tid, u16 ssn_idx)
850
if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
851
(IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
854
"queue number out of range: %d, must be %d to %d\n",
855
txq_id, IWL50_FIRST_AMPDU_QUEUE,
856
IWL50_FIRST_AMPDU_QUEUE +
857
priv->cfg->num_of_ampdu_queues - 1);
861
ra_tid = BUILD_RAxTID(sta_id, tid);
863
/* Modify device's station table to Tx this TID */
864
iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
866
spin_lock_irqsave(&priv->lock, flags);
868
/* Stop this Tx queue before configuring it */
869
iwl5000_tx_queue_stop_scheduler(priv, txq_id);
871
/* Map receiver-address / traffic-ID to this queue */
872
iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
874
/* Set this queue as a chain-building queue */
875
iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
877
/* enable aggregations for the queue */
878
iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
880
/* Place first TFD at index corresponding to start sequence number.
881
* Assumes that ssn_idx is valid (!= 0xFFF) */
882
priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
883
priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
884
iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
886
/* Set up Tx window size and frame limit for this queue */
887
iwl_write_targ_mem(priv, priv->scd_base_addr +
888
IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
891
IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
892
IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
894
IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
895
IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
897
iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
899
/* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
900
iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
902
spin_unlock_irqrestore(&priv->lock, flags);
907
int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
908
u16 ssn_idx, u8 tx_fifo)
910
if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
911
(IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
914
"queue number out of range: %d, must be %d to %d\n",
915
txq_id, IWL50_FIRST_AMPDU_QUEUE,
916
IWL50_FIRST_AMPDU_QUEUE +
917
priv->cfg->num_of_ampdu_queues - 1);
921
iwl5000_tx_queue_stop_scheduler(priv, txq_id);
923
iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
925
priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
926
priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
927
/* supposes that ssn_idx is valid (!= 0xFFF) */
928
iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
930
iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
931
iwl_txq_ctx_deactivate(priv, txq_id);
932
iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
937
u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
939
u16 size = (u16)sizeof(struct iwl_addsta_cmd);
940
struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
941
memcpy(addsta, cmd, size);
942
/* resrved in 5000 */
943
addsta->rate_n_flags = cpu_to_le16(0);
949
* Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
950
* must be called under priv->lock and mac access
952
void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
954
iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
958
static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
960
return le32_to_cpup((__le32 *)&tx_resp->status +
961
tx_resp->frame_count) & MAX_SN;
964
static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
965
struct iwl_ht_agg *agg,
966
struct iwl5000_tx_resp *tx_resp,
967
int txq_id, u16 start_idx)
970
struct agg_tx_status *frame_status = &tx_resp->status;
971
struct ieee80211_tx_info *info = NULL;
972
struct ieee80211_hdr *hdr = NULL;
973
u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
977
if (agg->wait_for_ba)
978
IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
980
agg->frame_count = tx_resp->frame_count;
981
agg->start_idx = start_idx;
982
agg->rate_n_flags = rate_n_flags;
985
/* # frames attempted by Tx command */
986
if (agg->frame_count == 1) {
987
/* Only one frame was attempted; no block-ack will arrive */
988
status = le16_to_cpu(frame_status[0].status);
991
/* FIXME: code repetition */
992
IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
993
agg->frame_count, agg->start_idx, idx);
995
info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
996
info->status.rates[0].count = tx_resp->failure_frame + 1;
997
info->flags &= ~IEEE80211_TX_CTL_AMPDU;
998
info->flags |= iwl_tx_status_to_mac80211(status);
999
iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1001
/* FIXME: code repetition end */
1003
IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1004
status & 0xff, tx_resp->failure_frame);
1005
IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1007
agg->wait_for_ba = 0;
1009
/* Two or more frames were attempted; expect block-ack */
1011
int start = agg->start_idx;
1013
/* Construct bit-map of pending frames within Tx window */
1014
for (i = 0; i < agg->frame_count; i++) {
1016
status = le16_to_cpu(frame_status[i].status);
1017
seq = le16_to_cpu(frame_status[i].sequence);
1018
idx = SEQ_TO_INDEX(seq);
1019
txq_id = SEQ_TO_QUEUE(seq);
1021
if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1022
AGG_TX_STATE_ABORT_MSK))
1025
IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1026
agg->frame_count, txq_id, idx);
1028
hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1031
"BUG_ON idx doesn't point to valid skb"
1032
" idx=%d, txq_id=%d\n", idx, txq_id);
1036
sc = le16_to_cpu(hdr->seq_ctrl);
1037
if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1039
"BUG_ON idx doesn't match seq control"
1040
" idx=%d, seq_idx=%d, seq=%d\n",
1046
IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1047
i, idx, SEQ_TO_SN(sc));
1051
sh = (start - idx) + 0xff;
1052
bitmap = bitmap << sh;
1055
} else if (sh < -64)
1056
sh = 0xff - (start - idx);
1060
bitmap = bitmap << sh;
1063
bitmap |= 1ULL << sh;
1064
IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1065
start, (unsigned long long)bitmap);
1068
agg->bitmap = bitmap;
1069
agg->start_idx = start;
1070
IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1071
agg->frame_count, agg->start_idx,
1072
(unsigned long long)agg->bitmap);
1075
agg->wait_for_ba = 1;
1080
static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1081
struct iwl_rx_mem_buffer *rxb)
1083
struct iwl_rx_packet *pkt = rxb_addr(rxb);
1084
u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1085
int txq_id = SEQ_TO_QUEUE(sequence);
1086
int index = SEQ_TO_INDEX(sequence);
1087
struct iwl_tx_queue *txq = &priv->txq[txq_id];
1088
struct ieee80211_tx_info *info;
1089
struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1090
u32 status = le16_to_cpu(tx_resp->status.status);
1095
if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1096
IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
1097
"is out of range [0-%d] %d %d\n", txq_id,
1098
index, txq->q.n_bd, txq->q.write_ptr,
1103
info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1104
memset(&info->status, 0, sizeof(info->status));
1106
tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1107
sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1109
if (txq->sched_retry) {
1110
const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1111
struct iwl_ht_agg *agg = NULL;
1113
agg = &priv->stations[sta_id].tid[tid].agg;
1115
iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1117
/* check if BAR is needed */
1118
if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1119
info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1121
if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1122
index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1123
IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
1124
"scd_ssn=%d idx=%d txq=%d swq=%d\n",
1125
scd_ssn , index, txq_id, txq->swq_id);
1127
freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1128
priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1130
if (priv->mac80211_registered &&
1131
(iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1132
(agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1133
if (agg->state == IWL_AGG_OFF)
1134
iwl_wake_queue(priv, txq_id);
1136
iwl_wake_queue(priv, txq->swq_id);
1140
BUG_ON(txq_id != txq->swq_id);
1142
info->status.rates[0].count = tx_resp->failure_frame + 1;
1143
info->flags |= iwl_tx_status_to_mac80211(status);
1144
iwl_hwrate_to_tx_control(priv,
1145
le32_to_cpu(tx_resp->rate_n_flags),
1148
IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
1149
"0x%x retries %d\n",
1151
iwl_get_tx_fail_reason(status), status,
1152
le32_to_cpu(tx_resp->rate_n_flags),
1153
tx_resp->failure_frame);
1155
freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1156
if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1157
priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1159
if (priv->mac80211_registered &&
1160
(iwl_queue_space(&txq->q) > txq->q.low_mark))
1161
iwl_wake_queue(priv, txq_id);
1164
if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1165
iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1167
if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1168
IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
1171
/* Currently 5000 is the superset of everything */
1172
u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1177
void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1179
/* in 5000 the tx power calibration is done in uCode */
1180
priv->disable_tx_power_cal = 1;
1183
void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1185
/* init calibration handlers */
1186
priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1187
iwl5000_rx_calib_result;
1188
priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1189
iwl5000_rx_calib_complete;
1190
priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1194
int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1196
return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
1197
(addr < IWL50_RTC_DATA_UPPER_BOUND);
1200
static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1203
struct iwl5000_rxon_assoc_cmd rxon_assoc;
1204
const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1205
const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1207
if ((rxon1->flags == rxon2->flags) &&
1208
(rxon1->filter_flags == rxon2->filter_flags) &&
1209
(rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1210
(rxon1->ofdm_ht_single_stream_basic_rates ==
1211
rxon2->ofdm_ht_single_stream_basic_rates) &&
1212
(rxon1->ofdm_ht_dual_stream_basic_rates ==
1213
rxon2->ofdm_ht_dual_stream_basic_rates) &&
1214
(rxon1->ofdm_ht_triple_stream_basic_rates ==
1215
rxon2->ofdm_ht_triple_stream_basic_rates) &&
1216
(rxon1->acquisition_data == rxon2->acquisition_data) &&
1217
(rxon1->rx_chain == rxon2->rx_chain) &&
1218
(rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1219
IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1223
rxon_assoc.flags = priv->staging_rxon.flags;
1224
rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1225
rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1226
rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1227
rxon_assoc.reserved1 = 0;
1228
rxon_assoc.reserved2 = 0;
1229
rxon_assoc.reserved3 = 0;
1230
rxon_assoc.ofdm_ht_single_stream_basic_rates =
1231
priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1232
rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1233
priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1234
rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1235
rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1236
priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1237
rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1239
ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1240
sizeof(rxon_assoc), &rxon_assoc, NULL);
1246
int iwl5000_send_tx_power(struct iwl_priv *priv)
1248
struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1251
/* half dBm need to multiply */
1252
tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1254
if (priv->tx_power_lmt_in_half_dbm &&
1255
priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
1257
* For the newer devices which using enhanced/extend tx power
1258
* table in EEPROM, the format is in half dBm. driver need to
1259
* convert to dBm format before report to mac80211.
1260
* By doing so, there is a possibility of 1/2 dBm resolution
1261
* lost. driver will perform "round-up" operation before
1262
* reporting, but it will cause 1/2 dBm tx power over the
1263
* regulatory limit. Perform the checking here, if the
1264
* "tx_power_user_lmt" is higher than EEPROM value (in
1265
* half-dBm format), lower the tx power based on EEPROM
1267
tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
1269
tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1270
tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1272
if (IWL_UCODE_API(priv->ucode_ver) == 1)
1273
tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1275
tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1277
return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
1278
sizeof(tx_power_cmd), &tx_power_cmd,
1282
void iwl5000_temperature(struct iwl_priv *priv)
1284
/* store temperature from statistics (in Celsius) */
1285
priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1286
iwl_tt_handler(priv);
1289
static void iwl5150_temperature(struct iwl_priv *priv)
1292
s32 offset = iwl_temp_calib_to_offset(priv);
1294
vt = le32_to_cpu(priv->statistics.general.temperature);
1295
vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1296
/* now vt hold the temperature in Kelvin */
1297
priv->temperature = KELVIN_TO_CELSIUS(vt);
1298
iwl_tt_handler(priv);
1301
/* Calc max signal level (dBm) among 3 possible receivers */
1302
int iwl5000_calc_rssi(struct iwl_priv *priv,
1303
struct iwl_rx_phy_res *rx_resp)
1305
/* data from PHY/DSP regarding signal strength, etc.,
1306
* contents are always there, not configurable by host
1308
struct iwl5000_non_cfg_phy *ncphy =
1309
(struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1310
u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1313
val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1314
agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1316
/* Find max rssi among 3 possible receivers.
1317
* These values are measured by the digital signal processor (DSP).
1318
* They should stay fairly constant even as the signal strength varies,
1319
* if the radio's automatic gain control (AGC) is working right.
1320
* AGC value (see below) will provide the "interesting" info.
1322
val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1323
rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1324
rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1325
val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1326
rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1328
max_rssi = max_t(u32, rssi_a, rssi_b);
1329
max_rssi = max_t(u32, max_rssi, rssi_c);
1331
IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1332
rssi_a, rssi_b, rssi_c, max_rssi, agc);
1334
/* dBm = max_rssi dB - agc dB - constant.
1335
* Higher AGC (higher radio gain) means lower signal. */
1336
return max_rssi - agc - IWL49_RSSI_OFFSET;
1339
static int iwl5000_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant)
1341
struct iwl_tx_ant_config_cmd tx_ant_cmd = {
1342
.valid = cpu_to_le32(valid_tx_ant),
1345
if (IWL_UCODE_API(priv->ucode_ver) > 1) {
1346
IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant);
1347
return iwl_send_cmd_pdu(priv, TX_ANT_CONFIGURATION_CMD,
1348
sizeof(struct iwl_tx_ant_config_cmd),
1351
IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n");
1357
#define IWL5000_UCODE_GET(item) \
1358
static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
1362
return le32_to_cpu(ucode->u.v1.item); \
1363
return le32_to_cpu(ucode->u.v2.item); \
1366
static u32 iwl5000_ucode_get_header_size(u32 api_ver)
1369
return UCODE_HEADER_SIZE(1);
1370
return UCODE_HEADER_SIZE(2);
1373
static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode,
1378
return le32_to_cpu(ucode->u.v2.build);
1381
static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode,
1385
return (u8 *) ucode->u.v1.data;
1386
return (u8 *) ucode->u.v2.data;
1389
IWL5000_UCODE_GET(inst_size);
1390
IWL5000_UCODE_GET(data_size);
1391
IWL5000_UCODE_GET(init_size);
1392
IWL5000_UCODE_GET(init_data_size);
1393
IWL5000_UCODE_GET(boot_size);
1395
static int iwl5000_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1397
struct iwl5000_channel_switch_cmd cmd;
1398
const struct iwl_channel_info *ch_info;
1399
struct iwl_host_cmd hcmd = {
1400
.id = REPLY_CHANNEL_SWITCH,
1402
.flags = CMD_SIZE_HUGE,
1406
IWL_DEBUG_11H(priv, "channel switch from %d to %d\n",
1407
priv->active_rxon.channel, channel);
1408
cmd.band = priv->band == IEEE80211_BAND_2GHZ;
1409
cmd.channel = cpu_to_le16(channel);
1410
cmd.rxon_flags = priv->staging_rxon.flags;
1411
cmd.rxon_filter_flags = priv->staging_rxon.filter_flags;
1412
cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1413
ch_info = iwl_get_channel_info(priv, priv->band, channel);
1415
cmd.expect_beacon = is_channel_radar(ch_info);
1417
IWL_ERR(priv, "invalid channel switch from %u to %u\n",
1418
priv->active_rxon.channel, channel);
1421
priv->switch_rxon.channel = cpu_to_le16(channel);
1422
priv->switch_rxon.switch_in_progress = true;
1424
return iwl_send_cmd_sync(priv, &hcmd);
1427
struct iwl_hcmd_ops iwl5000_hcmd = {
1428
.rxon_assoc = iwl5000_send_rxon_assoc,
1429
.commit_rxon = iwl_commit_rxon,
1430
.set_rxon_chain = iwl_set_rxon_chain,
1431
.set_tx_ant = iwl5000_send_tx_ant_config,
1434
struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1435
.get_hcmd_size = iwl5000_get_hcmd_size,
1436
.build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1437
.gain_computation = iwl5000_gain_computation,
1438
.chain_noise_reset = iwl5000_chain_noise_reset,
1439
.rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1440
.calc_rssi = iwl5000_calc_rssi,
1443
struct iwl_ucode_ops iwl5000_ucode = {
1444
.get_header_size = iwl5000_ucode_get_header_size,
1445
.get_build = iwl5000_ucode_get_build,
1446
.get_inst_size = iwl5000_ucode_get_inst_size,
1447
.get_data_size = iwl5000_ucode_get_data_size,
1448
.get_init_size = iwl5000_ucode_get_init_size,
1449
.get_init_data_size = iwl5000_ucode_get_init_data_size,
1450
.get_boot_size = iwl5000_ucode_get_boot_size,
1451
.get_data = iwl5000_ucode_get_data,
1454
struct iwl_lib_ops iwl5000_lib = {
1455
.set_hw_params = iwl5000_hw_set_hw_params,
1456
.txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1457
.txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1458
.txq_set_sched = iwl5000_txq_set_sched,
1459
.txq_agg_enable = iwl5000_txq_agg_enable,
1460
.txq_agg_disable = iwl5000_txq_agg_disable,
1461
.txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1462
.txq_free_tfd = iwl_hw_txq_free_tfd,
1463
.txq_init = iwl_hw_tx_queue_init,
1464
.rx_handler_setup = iwl5000_rx_handler_setup,
1465
.setup_deferred_work = iwl5000_setup_deferred_work,
1466
.is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1467
.dump_nic_event_log = iwl_dump_nic_event_log,
1468
.dump_nic_error_log = iwl_dump_nic_error_log,
1469
.load_ucode = iwl5000_load_ucode,
1470
.init_alive_start = iwl5000_init_alive_start,
1471
.alive_notify = iwl5000_alive_notify,
1472
.send_tx_power = iwl5000_send_tx_power,
1473
.update_chain_flags = iwl_update_chain_flags,
1474
.set_channel_switch = iwl5000_hw_channel_switch,
1476
.init = iwl_apm_init,
1477
.stop = iwl_apm_stop,
1478
.config = iwl5000_nic_config,
1479
.set_pwr_src = iwl_set_pwr_src,
1482
.regulatory_bands = {
1483
EEPROM_5000_REG_BAND_1_CHANNELS,
1484
EEPROM_5000_REG_BAND_2_CHANNELS,
1485
EEPROM_5000_REG_BAND_3_CHANNELS,
1486
EEPROM_5000_REG_BAND_4_CHANNELS,
1487
EEPROM_5000_REG_BAND_5_CHANNELS,
1488
EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1489
EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1491
.verify_signature = iwlcore_eeprom_verify_signature,
1492
.acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1493
.release_semaphore = iwlcore_eeprom_release_semaphore,
1494
.calib_version = iwl5000_eeprom_calib_version,
1495
.query_addr = iwl5000_eeprom_query_addr,
1497
.post_associate = iwl_post_associate,
1499
.config_ap = iwl_config_ap,
1501
.temperature = iwl5000_temperature,
1502
.set_ct_kill = iwl5000_set_ct_threshold,
1506
static struct iwl_lib_ops iwl5150_lib = {
1507
.set_hw_params = iwl5000_hw_set_hw_params,
1508
.txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1509
.txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1510
.txq_set_sched = iwl5000_txq_set_sched,
1511
.txq_agg_enable = iwl5000_txq_agg_enable,
1512
.txq_agg_disable = iwl5000_txq_agg_disable,
1513
.txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1514
.txq_free_tfd = iwl_hw_txq_free_tfd,
1515
.txq_init = iwl_hw_tx_queue_init,
1516
.rx_handler_setup = iwl5000_rx_handler_setup,
1517
.setup_deferred_work = iwl5000_setup_deferred_work,
1518
.is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1519
.dump_nic_event_log = iwl_dump_nic_event_log,
1520
.dump_nic_error_log = iwl_dump_nic_error_log,
1521
.load_ucode = iwl5000_load_ucode,
1522
.init_alive_start = iwl5000_init_alive_start,
1523
.alive_notify = iwl5000_alive_notify,
1524
.send_tx_power = iwl5000_send_tx_power,
1525
.update_chain_flags = iwl_update_chain_flags,
1526
.set_channel_switch = iwl5000_hw_channel_switch,
1528
.init = iwl_apm_init,
1529
.stop = iwl_apm_stop,
1530
.config = iwl5000_nic_config,
1531
.set_pwr_src = iwl_set_pwr_src,
1534
.regulatory_bands = {
1535
EEPROM_5000_REG_BAND_1_CHANNELS,
1536
EEPROM_5000_REG_BAND_2_CHANNELS,
1537
EEPROM_5000_REG_BAND_3_CHANNELS,
1538
EEPROM_5000_REG_BAND_4_CHANNELS,
1539
EEPROM_5000_REG_BAND_5_CHANNELS,
1540
EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1541
EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1543
.verify_signature = iwlcore_eeprom_verify_signature,
1544
.acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1545
.release_semaphore = iwlcore_eeprom_release_semaphore,
1546
.calib_version = iwl5000_eeprom_calib_version,
1547
.query_addr = iwl5000_eeprom_query_addr,
1549
.post_associate = iwl_post_associate,
1551
.config_ap = iwl_config_ap,
1553
.temperature = iwl5150_temperature,
1554
.set_ct_kill = iwl5150_set_ct_threshold,
1558
static struct iwl_ops iwl5000_ops = {
1559
.ucode = &iwl5000_ucode,
1560
.lib = &iwl5000_lib,
1561
.hcmd = &iwl5000_hcmd,
1562
.utils = &iwl5000_hcmd_utils,
1563
.led = &iwlagn_led_ops,
1566
static struct iwl_ops iwl5150_ops = {
1567
.ucode = &iwl5000_ucode,
1568
.lib = &iwl5150_lib,
1569
.hcmd = &iwl5000_hcmd,
1570
.utils = &iwl5000_hcmd_utils,
1571
.led = &iwlagn_led_ops,
1574
struct iwl_mod_params iwl50_mod_params = {
1577
/* the rest are 0 by default */
1581
struct iwl_cfg iwl5300_agn_cfg = {
1583
.fw_name_pre = IWL5000_FW_PRE,
1584
.ucode_api_max = IWL5000_UCODE_API_MAX,
1585
.ucode_api_min = IWL5000_UCODE_API_MIN,
1586
.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1587
.ops = &iwl5000_ops,
1588
.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1589
.eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1590
.eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1591
.num_of_queues = IWL50_NUM_QUEUES,
1592
.num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1593
.mod_params = &iwl50_mod_params,
1594
.valid_tx_ant = ANT_ABC,
1595
.valid_rx_ant = ANT_ABC,
1596
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1599
.ht_greenfield_support = true,
1600
.led_compensation = 51,
1601
.chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1602
.sm_ps_mode = WLAN_HT_CAP_SM_PS_DISABLED,
1605
struct iwl_cfg iwl5100_bgn_cfg = {
1607
.fw_name_pre = IWL5000_FW_PRE,
1608
.ucode_api_max = IWL5000_UCODE_API_MAX,
1609
.ucode_api_min = IWL5000_UCODE_API_MIN,
1610
.sku = IWL_SKU_G|IWL_SKU_N,
1611
.ops = &iwl5000_ops,
1612
.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1613
.eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1614
.eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1615
.num_of_queues = IWL50_NUM_QUEUES,
1616
.num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1617
.mod_params = &iwl50_mod_params,
1618
.valid_tx_ant = ANT_B,
1619
.valid_rx_ant = ANT_AB,
1620
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1623
.ht_greenfield_support = true,
1624
.led_compensation = 51,
1625
.chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1628
struct iwl_cfg iwl5100_abg_cfg = {
1630
.fw_name_pre = IWL5000_FW_PRE,
1631
.ucode_api_max = IWL5000_UCODE_API_MAX,
1632
.ucode_api_min = IWL5000_UCODE_API_MIN,
1633
.sku = IWL_SKU_A|IWL_SKU_G,
1634
.ops = &iwl5000_ops,
1635
.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1636
.eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1637
.eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1638
.num_of_queues = IWL50_NUM_QUEUES,
1639
.num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1640
.mod_params = &iwl50_mod_params,
1641
.valid_tx_ant = ANT_B,
1642
.valid_rx_ant = ANT_AB,
1643
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1646
.led_compensation = 51,
1647
.chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1650
struct iwl_cfg iwl5100_agn_cfg = {
1652
.fw_name_pre = IWL5000_FW_PRE,
1653
.ucode_api_max = IWL5000_UCODE_API_MAX,
1654
.ucode_api_min = IWL5000_UCODE_API_MIN,
1655
.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1656
.ops = &iwl5000_ops,
1657
.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1658
.eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1659
.eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1660
.num_of_queues = IWL50_NUM_QUEUES,
1661
.num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1662
.mod_params = &iwl50_mod_params,
1663
.valid_tx_ant = ANT_B,
1664
.valid_rx_ant = ANT_AB,
1665
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1668
.ht_greenfield_support = true,
1669
.led_compensation = 51,
1670
.chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1671
.sm_ps_mode = WLAN_HT_CAP_SM_PS_DISABLED,
1674
struct iwl_cfg iwl5350_agn_cfg = {
1676
.fw_name_pre = IWL5000_FW_PRE,
1677
.ucode_api_max = IWL5000_UCODE_API_MAX,
1678
.ucode_api_min = IWL5000_UCODE_API_MIN,
1679
.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1680
.ops = &iwl5000_ops,
1681
.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1682
.eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1683
.eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1684
.num_of_queues = IWL50_NUM_QUEUES,
1685
.num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1686
.mod_params = &iwl50_mod_params,
1687
.valid_tx_ant = ANT_ABC,
1688
.valid_rx_ant = ANT_ABC,
1689
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1692
.ht_greenfield_support = true,
1693
.led_compensation = 51,
1694
.chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1695
.sm_ps_mode = WLAN_HT_CAP_SM_PS_DISABLED,
1698
struct iwl_cfg iwl5150_agn_cfg = {
1700
.fw_name_pre = IWL5150_FW_PRE,
1701
.ucode_api_max = IWL5150_UCODE_API_MAX,
1702
.ucode_api_min = IWL5150_UCODE_API_MIN,
1703
.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1704
.ops = &iwl5150_ops,
1705
.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1706
.eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1707
.eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1708
.num_of_queues = IWL50_NUM_QUEUES,
1709
.num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1710
.mod_params = &iwl50_mod_params,
1711
.valid_tx_ant = ANT_A,
1712
.valid_rx_ant = ANT_AB,
1713
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1716
.ht_greenfield_support = true,
1717
.led_compensation = 51,
1718
.chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1719
.sm_ps_mode = WLAN_HT_CAP_SM_PS_DISABLED,
1722
struct iwl_cfg iwl5150_abg_cfg = {
1724
.fw_name_pre = IWL5150_FW_PRE,
1725
.ucode_api_max = IWL5150_UCODE_API_MAX,
1726
.ucode_api_min = IWL5150_UCODE_API_MIN,
1727
.sku = IWL_SKU_A|IWL_SKU_G,
1728
.ops = &iwl5150_ops,
1729
.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1730
.eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1731
.eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1732
.num_of_queues = IWL50_NUM_QUEUES,
1733
.num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1734
.mod_params = &iwl50_mod_params,
1735
.valid_tx_ant = ANT_A,
1736
.valid_rx_ant = ANT_AB,
1737
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1740
.led_compensation = 51,
1741
.chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1744
MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1745
MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1747
module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, S_IRUGO);
1748
MODULE_PARM_DESC(swcrypto50,
1749
"using software crypto engine (default 0 [hardware])\n");
1750
module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, S_IRUGO);
1751
MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1752
module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, S_IRUGO);
1753
MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1754
module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K,
1756
MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1757
module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, S_IRUGO);
1758
MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
added
removed
updates/compat-wireless-2.6/drivers/net/wireless/iwlwifi/iwl-5000.c
