78
80
/* ------------------------------------------------------------------------- */
80
const char *mem_romset_resources_list[] = {
81
"KernalName", "ChargenName", "BasicName",
82
"DosName2031", "DosName1001",
83
"DosName1541", "DosName1571", "DosName1581", "DosName1541ii",
87
/* ------------------------------------------------------------------------- */
89
82
/* Number of possible video banks (16K each). */
90
83
#define NUM_VBANKS 4
92
85
/* The C128 memory. */
93
86
BYTE mem_ram[C128_RAM_SIZE];
94
BYTE mem_basic_rom[C128_BASIC_ROM_SIZE + C128_EDITOR_ROM_SIZE];
95
BYTE mem_kernal_rom[C128_KERNAL_ROM_SIZE];
96
87
BYTE mem_chargen_rom[C128_CHARGEN_ROM_SIZE];
98
BYTE mem_basic64_rom[C128_BASIC64_ROM_SIZE];
99
BYTE mem_kernal64_rom[C128_KERNAL64_ROM_SIZE];
100
BYTE mem_kernal64_trap_rom[C128_KERNAL64_ROM_SIZE];
102
89
/* Internal color memory. */
103
90
static BYTE mem_color_ram[0x800];
104
91
BYTE *mem_color_ram_cpu, *mem_color_ram_vicii;
160
147
static BYTE REGPARM1 watch_read(WORD addr)
162
mon_watch_push_load_addr(addr, e_comp_space);
149
monitor_watch_push_load_addr(addr, e_comp_space);
163
150
return mem_read_tab[mem_config][addr >> 8](addr);
167
153
static void REGPARM2 watch_store(WORD addr, BYTE value)
169
mon_watch_push_store_addr(addr, e_comp_space);
155
monitor_watch_push_store_addr(addr, e_comp_space);
170
156
mem_write_tab[mem_config][addr >> 8](addr, value);
370
356
/* External memory access functions. */
372
BYTE REGPARM1 basic_read(WORD addr)
374
return mem_basic_rom[addr - 0x4000];
377
void REGPARM2 basic_store(WORD addr, BYTE value)
379
mem_basic_rom[addr - 0x4000] = value;
382
BYTE REGPARM1 kernal_read(WORD addr)
384
return mem_kernal_rom[addr & 0x1fff];
387
void REGPARM2 kernal_store(WORD addr, BYTE value)
389
mem_kernal_rom[addr & 0x1fff] = value;
392
358
BYTE REGPARM1 chargen_read(WORD addr)
394
360
return mem_chargen_rom_ptr[addr & 0x0fff];
399
365
mem_chargen_rom_ptr[addr & 0x0fff] = value;
402
BYTE REGPARM1 rom_read(WORD addr)
404
switch (addr & 0xf000) {
406
return bios_read(addr);
415
return basic_read(addr);
418
return kernal_read(addr);
424
void REGPARM2 rom_store(WORD addr, BYTE value)
426
switch (addr & 0xf000) {
428
bios_store(addr, value);
438
basic_store(addr, value);
442
kernal_store(addr, value);
368
/* ------------------------------------------------------------------------- */
447
370
/* Generic memory access. */
456
379
return _mem_read_tab_ptr[addr >> 8](addr);
382
void REGPARM2 mem_store_without_ultimax(WORD addr, BYTE value)
384
store_func_ptr_t *write_tab_ptr;
386
write_tab_ptr = mem_write_tab[mem_config & 7];
388
write_tab_ptr[addr >> 8](addr, value);
391
BYTE REGPARM1 mem_read_without_ultimax(WORD addr)
393
read_func_ptr_t *read_tab_ptr;
395
read_tab_ptr = mem_read_tab[mem_config & 7];
397
return read_tab_ptr[addr >> 8](addr);
459
400
/* ------------------------------------------------------------------------- */
461
402
/* CPU Memory interface. */
514
455
/* $4000 - $7FFF: RAM or low BASIC ROM. */
515
456
BYTE REGPARM1 basic_lo_read(WORD addr)
517
return mem_basic_rom[addr - 0x4000];
458
return c128memrom_basic_rom[addr - 0x4000];
520
461
void REGPARM2 basic_lo_store(WORD addr, BYTE value)
526
467
/* $8000 - $BFFF: RAM or high BASIC ROM. */
527
468
BYTE REGPARM1 basic_hi_read(WORD addr)
529
return mem_basic_rom[addr - 0x4000];
470
return c128memrom_basic_rom[addr - 0x4000];
532
473
void REGPARM2 basic_hi_store(WORD addr, BYTE value)
538
479
/* $C000 - $CFFF: RAM (normal or shared) or Editor ROM. */
539
480
BYTE REGPARM1 editor_read(WORD addr)
541
return mem_basic_rom[addr - 0x4000];
482
return c128memrom_basic_rom[addr - 0x4000];
544
485
void REGPARM2 editor_store(WORD addr, BYTE value)
567
508
/* $E000 - $FFFF: RAM or Kernal. */
568
509
BYTE REGPARM1 hi_read(WORD addr)
570
return mem_kernal_rom[addr & 0x1fff];
511
return c128memrom_kernal_rom[addr & 0x1fff];
573
514
void REGPARM2 hi_store(WORD addr, BYTE value)
648
589
/* Setup character generator ROM at $D000-$DFFF (memory configs 1, 2,
649
590
3, 9, 10, 11, 25, 26, 27). */
650
591
for (i = 0xd0; i <= 0xdf; i++) {
651
mem_read_tab[128+1][i] = chargen_read;
652
mem_read_tab[128+2][i] = chargen_read;
653
mem_read_tab[128+3][i] = chargen_read;
654
mem_read_tab[128+9][i] = chargen_read;
655
mem_read_tab[128+10][i] = chargen_read;
656
mem_read_tab[128+11][i] = chargen_read;
657
mem_read_tab[128+25][i] = chargen_read;
658
mem_read_tab[128+26][i] = chargen_read;
659
mem_read_tab[128+27][i] = chargen_read;
660
mem_read_base_tab[128+1][i] = NULL;
661
mem_read_base_tab[128+2][i] = NULL;
662
mem_read_base_tab[128+3][i] = NULL;
663
mem_read_base_tab[128+9][i] = NULL;
664
mem_read_base_tab[128+10][i] = NULL;
665
mem_read_base_tab[128+11][i] = NULL;
666
mem_read_base_tab[128+25][i] = NULL;
667
mem_read_base_tab[128+26][i] = NULL;
668
mem_read_base_tab[128+27][i] = NULL;
592
mem_read_tab[128 + 1][i] = chargen_read;
593
mem_read_tab[128 + 2][i] = chargen_read;
594
mem_read_tab[128 + 3][i] = chargen_read;
595
mem_read_tab[128 + 9][i] = chargen_read;
596
mem_read_tab[128 + 10][i] = chargen_read;
597
mem_read_tab[128 + 11][i] = chargen_read;
598
mem_read_tab[128 + 25][i] = chargen_read;
599
mem_read_tab[128 + 26][i] = chargen_read;
600
mem_read_tab[128 + 27][i] = chargen_read;
601
mem_read_base_tab[128 + 1][i] = NULL;
602
mem_read_base_tab[128 + 2][i] = NULL;
603
mem_read_base_tab[128 + 3][i] = NULL;
604
mem_read_base_tab[128 + 9][i] = NULL;
605
mem_read_base_tab[128 + 10][i] = NULL;
606
mem_read_base_tab[128 + 11][i] = NULL;
607
mem_read_base_tab[128 + 25][i] = NULL;
608
mem_read_base_tab[128 + 26][i] = NULL;
609
mem_read_base_tab[128 + 27][i] = NULL;
673
614
/* Setup C128 specific I/O at $D000-$DFFF. */
674
615
for (j = 0; j < 32; j++) {
675
616
if (c64meminit_io_config[j]) {
676
mem_read_tab[128+j][0xd4] = sid_read;
677
mem_write_tab[128+j][0xd4] = sid_store;
678
mem_read_tab[128+j][0xd5] = d5xx_read;
679
mem_write_tab[128+j][0xd5] = d5xx_store;
680
mem_read_tab[128+j][0xd6] = vdc_read;
681
mem_write_tab[128+j][0xd6] = vdc_store;
682
mem_read_tab[128+j][0xd7] = d7xx_read;
683
mem_write_tab[128+j][0xd7] = d7xx_store;
617
mem_read_tab[128 + j][0xd4] = sid_read;
618
mem_write_tab[128 + j][0xd4] = sid_store;
619
mem_read_tab[128 + j][0xd5] = d5xx_read;
620
mem_write_tab[128 + j][0xd5] = d5xx_store;
621
mem_read_tab[128 + j][0xd6] = vdc_read;
622
mem_write_tab[128 + j][0xd6] = vdc_store;
623
mem_read_tab[128 + j][0xd7] = d7xx_read;
624
mem_write_tab[128 + j][0xd7] = d7xx_store;
752
693
mem_pla_config_changed();
755
/* Enable/disable the REU. FIXME: should initialize the REU if necessary? */
756
/* @SRT FIXME: Is this used anywhere?
757
void mem_toggle_reu(int flag)
764
/* Enable/disable the IEEE488 interface. */
765
void mem_toggle_ieee488(int flag)
767
ieee488_enabled = flag;
770
/* Enable/disable the Emulator ID. */
771
void mem_toggle_emu_id(int flag)
773
emu_id_enabled = flag;
777
696
/* ------------------------------------------------------------------------- */
779
698
void mem_get_basic_text(WORD *start, WORD *end)
983
902
return bios_read(addr);
985
904
if (addr >= 0x4000 && addr <= 0xcfff) {
986
return mem_basic_rom[addr - 0x4000];
905
return c128memrom_basic_rom[addr - 0x4000];
988
907
if (addr >= 0xd000 && addr <= 0xdfff) {
989
908
return mem_chargen_rom[addr & 0x0fff];
991
910
if (addr >= 0xe000) {
992
return mem_kernal_rom[addr & 0x1fff];
911
return c128memrom_kernal_rom[addr & 0x1fff];
994
913
case 1: /* ram */
1014
933
if (addr >= 0xa000 && addr <= 0xbfff) {
1015
return mem_basic64_rom[addr & 0x1fff];
934
return c64memrom_basic64_rom[addr & 0x1fff];
1017
936
if (addr >= 0xd000 && addr <= 0xdfff) {
1018
937
return mem_chargen_rom[addr & 0x0fff];
1020
939
if (addr >= 0xe000) {
1021
return mem_kernal64_rom[addr & 0x1fff];
940
return c64memrom_kernal64_rom[addr & 0x1fff];