49
49
static BYTE cpu_data, cpu_clock, cpu_atn;
50
static BYTE drive_data, drive_clock, drive_atna, drive_data_modifier;
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static BYTE drive2_data, drive2_clock, drive2_atna, drive2_data_modifier;
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static BYTE drive_data[DRIVE_NUM], drive_clock[DRIVE_NUM];
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static BYTE drive_atna[DRIVE_NUM], drive_data_modifier[DRIVE_NUM];
52
52
static BYTE bus_data, bus_clock, bus_atn;
53
53
static BYTE cpu_bus_val;
54
static BYTE drive_bus_val, drive2_bus_val;
56
55
static inline void resolve_bus_signals(void)
58
drive_t *drive0, *drive1;
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drive0 = drive_context[0]->drive;
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drive1 = drive_context[1]->drive;
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60
bus_atn = NOT(cpu_atn);
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bus_clock = NOT(cpu_clock) & (drive0->enable ? NOT(drive_clock) : 0x01)
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& (drive1->enable ? NOT(drive2_clock) : 0x01);
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bus_data = (drive0->enable
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? NOT(drive_data) & NOT(drive_data_modifier) : 0x01)
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? NOT(drive2_data) & NOT(drive2_data_modifier) : 0x01)
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fprintf(logfile, "SB: [%ld] data:%d clock:%d atn:%d\n",
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drive_clk[0], bus_data, bus_clock, bus_atn);
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bus_clock = NOT(cpu_clock);
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bus_data = NOT(cpu_data);
64
for (i = 0; i < DRIVE_NUM; i++) {
65
drive = drive_context[i]->drive;
67
bus_clock &= drive->enable ? NOT(drive_clock[i]) : 0x01;
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bus_data &= drive->enable ? NOT(drive_data[i])
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& NOT(drive_data_modifier[i]) : 0x01;
77
73
void iec_update_ports(void)
95
91
iec_update_ports();
98
static void iec_calculate_data_modifier(void)
100
if (drive_context[0]->drive->type != DRIVE_TYPE_1581)
101
drive_data_modifier = (NOT(cpu_atn) ^ NOT(drive_atna));
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drive_data_modifier = (cpu_atn & drive_atna);
106
static void iec_calculate_data_modifier2(void)
108
if (drive_context[1]->drive->type != DRIVE_TYPE_1581)
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drive2_data_modifier = (NOT(cpu_atn) ^ NOT(drive2_atna));
111
drive2_data_modifier = (cpu_atn & drive2_atna);
114
void iec_drive0_write(BYTE data)
116
static int last_write = 0;
119
drive_data = ((data & 2) >> 1);
120
drive_clock = ((data & 8) >> 3);
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drive_atna = ((data & 16) >> 4);
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iec_calculate_data_modifier();
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resolve_bus_signals();
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last_write = data & 26;
127
void iec_drive1_write(BYTE data)
129
static int last_write = 0;
132
drive2_data = ((data & 2) >> 1);
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drive2_clock = ((data & 8) >> 3);
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drive2_atna = ((data & 16) >> 4);
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iec_calculate_data_modifier2();
136
resolve_bus_signals();
137
last_write = data & 26;
140
BYTE iec_drive0_read(void)
94
static void iec_calculate_data_modifier(unsigned int dnr)
96
if (drive_context[dnr]->drive->type != DRIVE_TYPE_1581)
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drive_data_modifier[dnr] = (NOT(cpu_atn) ^ NOT(drive_atna[dnr]));
99
drive_data_modifier[dnr] = (cpu_atn & drive_atna[dnr]);
102
void iec_drive_write(BYTE data, unsigned int dnr)
104
static int last_write = 0;
107
drive_data[dnr] = ((data & 2) >> 1);
108
drive_clock[dnr] = ((data & 8) >> 3);
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drive_atna[dnr] = ((data & 16) >> 4);
110
iec_calculate_data_modifier(dnr);
111
resolve_bus_signals();
112
last_write = data & 26;
115
BYTE iec_drive_read(unsigned int dnr)
142
119
drive_bus_val = bus_data | (bus_clock << 2) | (bus_atn << 7);
143
121
return drive_bus_val;
146
BYTE iec_drive1_read(void)
148
drive2_bus_val = bus_data | (bus_clock << 2) | (bus_atn << 7);
149
return drive2_bus_val;
153
125
The VIC20 has a strange bus layout for the serial IEC bus.
175
147
void iec_pa_write(BYTE data)
177
149
static int last_write = 0;
178
drive_t *drive0, *drive1;
180
drive0 = drive_context[0]->drive;
181
drive1 = drive_context[1]->drive;
183
153
drivecpu_execute_all(maincpu_clk);
185
155
/* Signal ATN interrupt to the drives. */
186
156
if ((cpu_atn == 0) && (data & 128)) {
187
if (drive0->enable) {
188
if (drive0->type != DRIVE_TYPE_1581)
189
viacore_signal(drive_context[0]->via1d1541, VIA_SIG_CA1,
192
ciacore_set_flag(drive_context[0]->cia1581);
194
if (drive1->enable) {
195
if (drive1->type != DRIVE_TYPE_1581)
196
viacore_signal(drive_context[1]->via1d1541, VIA_SIG_CA1,
199
ciacore_set_flag(drive_context[1]->cia1581);
157
for (i = 0; i < DRIVE_NUM; i++) {
158
drive = drive_context[i]->drive;
161
if (drive->type != DRIVE_TYPE_1581)
162
viacore_signal(drive_context[i]->via1d1541, VIA_SIG_CA1,
165
ciacore_set_flag(drive_context[i]->cia1581);
203
170
/* Release ATN signal. */
204
171
if (!(data & 128)) {
205
if (drive0->enable) {
206
if (drive0->type != DRIVE_TYPE_1581)
207
viacore_signal(drive_context[0]->via1d1541, VIA_SIG_CA1, 0);
209
if (drive1->enable) {
210
if (drive1->type != DRIVE_TYPE_1581)
211
viacore_signal(drive_context[1]->via1d1541, VIA_SIG_CA1, 0);
172
for (i = 0; i < DRIVE_NUM; i++) {
173
drive = drive_context[i]->drive;
176
if (drive->type != DRIVE_TYPE_1581)
177
viacore_signal(drive_context[i]->via1d1541, VIA_SIG_CA1, 0);
215
183
cpu_atn = ((data & 128) >> 7);
217
iec_calculate_data_modifier();
218
iec_calculate_data_modifier2();
185
for (i = 0; i < DRIVE_NUM; i++)
186
iec_calculate_data_modifier(i);
220
188
resolve_bus_signals();
221
189
last_write = data & 128;
230
198
void iec_pcr_write(BYTE data)
232
200
static int last_write = 0;
234
if (!(drive_context[0]->drive->enable)
235
&& !(drive_context[1]->drive->enable))
238
203
drivecpu_execute_all(maincpu_clk);
240
205
cpu_data = ((data & 32) >> 5);
241
206
cpu_clock = ((data & 2) >> 1);
243
iec_calculate_data_modifier();
244
iec_calculate_data_modifier2();
208
for (i = 0; i < DRIVE_NUM; i++)
209
iec_calculate_data_modifier(i);
246
211
resolve_bus_signals();
247
212
last_write = data & 34;
264
void parallel_cable_drive0_write(BYTE data, int handshake)
268
void parallel_cable_drive1_write(BYTE data, int handshake)
229
void parallel_cable_drive_write(BYTE data, int handshake, unsigned int dnr)