← Back to branch summary

~ubuntu-branches/ubuntu/precise/gnuradio/precise

« back to all changes in this revision

Viewing changes to gr-radar-mono/src/fpga/top/usrp_radar_mono.psf

  • Committer: Bazaar Package Importer
  • Author(s): Kamal Mostafa
  • Date: 2010-03-13 07:46:01 UTC
  • mfrom: (2.1.2 sid)
  • Revision ID: james.westby@ubuntu.com-20100313074601-zjsa893a87bozyh7
Tags: 3.2.2.dfsg-1ubuntu1
https://launchpad.net/bugs/260406
* Fix build for Ubuntu lucid (LP: #260406)
  - add binary package dep for libusrp0, libusrp2-0: adduser
  - debian/rules clean: remove pre-built Qt moc files

Show diffs side-by-side

added added

removed removed

Lines of Context:
gr-radar-mono/src/fpga/top/usrp_radar_mono.psf
 
1
DEFAULT_DESIGN_ASSISTANT_SETTINGS
 
2
{
 
3
        HCPY_ALOAD_SIGNALS = OFF;
 
4
        HCPY_VREF_PINS = OFF;
 
5
        HCPY_CAT = OFF;
 
6
        HCPY_ILLEGAL_HC_DEV_PKG = OFF;
 
7
        ACLK_RULE_IMSZER_ADOMAIN = OFF;
 
8
        ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF;
 
9
        ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF;
 
10
        ACLK_CAT = OFF;
 
11
        SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF;
 
12
        SIGNALRACE_CAT = OFF;
 
13
        NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF;
 
14
        NONSYNCHSTRUCT_RULE_SRLATCH = OFF;
 
15
        NONSYNCHSTRUCT_RULE_DLATCH = OFF;
 
16
        NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF;
 
17
        NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF;
 
18
        NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF;
 
19
        NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF;
 
20
        NONSYNCHSTRUCT_RULE_REG_LOOP = OFF;
 
21
        NONSYNCHSTRUCT_RULE_COMBLOOP = OFF;
 
22
        NONSYNCHSTRUCT_CAT = OFF;
 
23
        NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF;
 
24
        TIMING_RULE_COIN_CLKEDGE = OFF;
 
25
        TIMING_RULE_SHIFT_REG = OFF;
 
26
        TIMING_RULE_HIGH_FANOUTS = OFF;
 
27
        TIMING_CAT = OFF;
 
28
        RESET_RULE_ALL = OFF;
 
29
        RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF;
 
30
        RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF;
 
31
        RESET_RULE_REG_ASNYCH = OFF;
 
32
        RESET_RULE_COMB_ASYNCH_RESET = OFF;
 
33
        RESET_RULE_IMSYNCH_EXRESET = OFF;
 
34
        RESET_RULE_UNSYNCH_EXRESET = OFF;
 
35
        RESET_RULE_INPINS_RESETNET = OFF;
 
36
        RESET_CAT = OFF;
 
37
        CLK_RULE_ALL = OFF;
 
38
        CLK_RULE_MIX_EDGES = OFF;
 
39
        CLK_RULE_CLKNET_CLKSPINES = OFF;
 
40
        CLK_RULE_INPINS_CLKNET = OFF;
 
41
        CLK_RULE_GATING_SCHEME = OFF;
 
42
        CLK_RULE_INV_CLOCK = OFF;
 
43
        CLK_RULE_COMB_CLOCK = OFF;
 
44
        CLK_CAT = OFF;
 
45
        HCPY_EXCEED_USER_IO_USAGE = OFF;
 
46
        HCPY_EXCEED_RAM_USAGE = OFF;
 
47
        NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF;
 
48
        SIGNALRACE_RULE_TRISTATE = OFF;
 
49
        ASSG_RULE_MISSING_TIMING = OFF;
 
50
        ASSG_RULE_MISSING_FMAX = OFF;
 
51
        ASSG_CAT = OFF;
 
52
}
 
53
SYNTHESIS_FITTING_SETTINGS
 
54
{
 
55
        AUTO_SHIFT_REGISTER_RECOGNITION = ON;
 
56
        AUTO_DSP_RECOGNITION = ON;
 
57
        AUTO_RAM_RECOGNITION = ON;
 
58
        REMOVE_DUPLICATE_LOGIC = ON;
 
59
        AUTO_TURBO_BIT = ON;
 
60
        AUTO_MERGE_PLLS = ON;
 
61
        AUTO_OPEN_DRAIN_PINS = ON;
 
62
        AUTO_PARALLEL_EXPANDERS = ON;
 
63
        AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF;
 
64
        AUTO_FAST_OUTPUT_REGISTERS = OFF;
 
65
        AUTO_FAST_INPUT_REGISTERS = OFF;
 
66
        AUTO_CASCADE_CHAINS = ON;
 
67
        AUTO_CARRY_CHAINS = ON;
 
68
        AUTO_DELAY_CHAINS = ON;
 
69
        MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4;
 
70
        PARALLEL_EXPANDER_CHAIN_LENGTH = 16;
 
71
        CASCADE_CHAIN_LENGTH = 2;
 
72
        STRATIX_CARRY_CHAIN_LENGTH = 70;
 
73
        MERCURY_CARRY_CHAIN_LENGTH = 48;
 
74
        FLEX10K_CARRY_CHAIN_LENGTH = 32;
 
75
        FLEX6K_CARRY_CHAIN_LENGTH = 32;
 
76
        CARRY_CHAIN_LENGTH = 48;
 
77
        CARRY_OUT_PINS_LCELL_INSERT = ON;
 
78
        NORMAL_LCELL_INSERT = ON;
 
79
        AUTO_LCELL_INSERTION = ON;
 
80
        ALLOW_XOR_GATE_USAGE = ON;
 
81
        AUTO_PACKED_REGISTERS_STRATIX = NORMAL;
 
82
        AUTO_PACKED_REGISTERS = OFF;
 
83
        AUTO_PACKED_REG_CYCLONE = NORMAL;
 
84
        FLEX10K_OPTIMIZATION_TECHNIQUE = AREA;
 
85
        FLEX6K_OPTIMIZATION_TECHNIQUE = AREA;
 
86
        MERCURY_OPTIMIZATION_TECHNIQUE = AREA;
 
87
        APEX20K_OPTIMIZATION_TECHNIQUE = SPEED;
 
88
        MAX7000_OPTIMIZATION_TECHNIQUE = SPEED;
 
89
        STRATIX_OPTIMIZATION_TECHNIQUE = SPEED;
 
90
        CYCLONE_OPTIMIZATION_TECHNIQUE = AREA;
 
91
        FLEX10K_TECHNOLOGY_MAPPER = LUT;
 
92
        FLEX6K_TECHNOLOGY_MAPPER = LUT;
 
93
        MERCURY_TECHNOLOGY_MAPPER = LUT;
 
94
        APEX20K_TECHNOLOGY_MAPPER = LUT;
 
95
        MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM";
 
96
        STRATIX_TECHNOLOGY_MAPPER = LUT;
 
97
        AUTO_IMPLEMENT_IN_ROM = OFF;
 
98
        AUTO_GLOBAL_MEMORY_CONTROLS = OFF;
 
99
        AUTO_GLOBAL_REGISTER_CONTROLS = ON;
 
100
        AUTO_GLOBAL_OE = ON;
 
101
        AUTO_GLOBAL_CLOCK = ON;
 
102
        USE_LPM_FOR_AHDL_OPERATORS = ON;
 
103
        LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF;
 
104
        ENABLE_BUS_HOLD_CIRCUITRY = OFF;
 
105
        WEAK_PULL_UP_RESISTOR = OFF;
 
106
        TURBO_BIT = ON;
 
107
        MAX7000_IGNORE_SOFT_BUFFERS = OFF;
 
108
        IGNORE_SOFT_BUFFERS = ON;
 
109
        MAX7000_IGNORE_LCELL_BUFFERS = AUTO;
 
110
        IGNORE_LCELL_BUFFERS = OFF;
 
111
        IGNORE_ROW_GLOBAL_BUFFERS = OFF;
 
112
        IGNORE_GLOBAL_BUFFERS = OFF;
 
113
        IGNORE_CASCADE_BUFFERS = OFF;
 
114
        IGNORE_CARRY_BUFFERS = OFF;
 
115
        REMOVE_DUPLICATE_REGISTERS = ON;
 
116
        REMOVE_REDUNDANT_LOGIC_CELLS = OFF;
 
117
        ALLOW_POWER_UP_DONT_CARE = ON;
 
118
        PCI_IO = OFF;
 
119
        NOT_GATE_PUSH_BACK = ON;
 
120
        SLOW_SLEW_RATE = OFF;
 
121
        DSP_BLOCK_BALANCING = AUTO;
 
122
        STATE_MACHINE_PROCESSING = AUTO;
 
123
}
 
124
DEFAULT_HARDCOPY_SETTINGS
 
125
{
 
126
        HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS";
 
127
}
 
128
DEFAULT_TIMING_REQUIREMENTS
 
129
{
 
130
        INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
 
131
        RUN_ALL_TIMING_ANALYSES = ON;
 
132
        IGNORE_CLOCK_SETTINGS = OFF;
 
133
        DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE";
 
134
        CUT_OFF_IO_PIN_FEEDBACK = ON;
 
135
        CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
 
136
        CUT_OFF_READ_DURING_WRITE_PATHS = ON;
 
137
        CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON;
 
138
        DO_MIN_ANALYSIS = ON;
 
139
        DO_MIN_TIMING = OFF;
 
140
        NUMBER_OF_PATHS_TO_REPORT = 200;
 
141
        NUMBER_OF_DESTINATION_TO_REPORT = 10;
 
142
        NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10;
 
143
        MAX_SCC_SIZE = 50;
 
144
}
 
145
HDL_SETTINGS
 
146
{
 
147
        VERILOG_INPUT_VERSION = VERILOG_2001;
 
148
        ENABLE_IP_DEBUG = OFF;
 
149
        VHDL_INPUT_VERSION = VHDL93;
 
150
        VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF;
 
151
}
 
152
PROJECT_INFO(usrp_radar_mono)
 
153
{
 
154
        ORIGINAL_QUARTUS_VERSION = 3.0;
 
155
        PROJECT_CREATION_TIME_DATE = "00:14:04  JULY 13, 2003";
 
156
        LAST_QUARTUS_VERSION = 3.0;
 
157
        SHOW_REGISTRATION_MESSAGE = ON;
 
158
        USER_LIBRARIES = "h:\\gnuradio\\trunk\\usrp\\fpga\\megacells";
 
159
}
 
160
THIRD_PARTY_EDA_TOOLS(usrp_radar_mono)
 
161
{
 
162
        EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = "<NONE>";
 
163
        EDA_SIMULATION_TOOL = "<NONE>";
 
164
        EDA_TIMING_ANALYSIS_TOOL = "<NONE>";
 
165
        EDA_BOARD_DESIGN_TOOL = "<NONE>";
 
166
        EDA_FORMAL_VERIFICATION_TOOL = "<NONE>";
 
167
        EDA_RESYNTHESIS_TOOL = "<NONE>";
 
168
}
 
169
EDA_TOOL_SETTINGS(eda_design_synthesis)
 
170
{
 
171
        EDA_INPUT_GND_NAME = GND;
 
172
        EDA_INPUT_VCC_NAME = VCC;
 
173
        EDA_SHOW_LMF_MAPPING_MESSAGES = OFF;
 
174
        EDA_RUN_TOOL_AUTOMATICALLY = OFF;
 
175
        EDA_INPUT_DATA_FORMAT = EDIF;
 
176
        EDA_OUTPUT_DATA_FORMAT = NONE;
 
177
        USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
 
178
        RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
 
179
        RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
 
180
        RESYNTHESIS_RETIMING = FULL;
 
181
}
 
182
EDA_TOOL_SETTINGS(eda_simulation)
 
183
{
 
184
        EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
 
185
        EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
 
186
        EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
 
187
        EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
 
188
        EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
 
189
        EDA_FLATTEN_BUSES = OFF;
 
190
        EDA_MAP_ILLEGAL_CHARACTERS = OFF;
 
191
        EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
 
192
        EDA_RUN_TOOL_AUTOMATICALLY = OFF;
 
193
        EDA_OUTPUT_DATA_FORMAT = NONE;
 
194
        USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
 
195
        RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
 
196
        RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
 
197
        RESYNTHESIS_RETIMING = FULL;
 
198
}
 
199
EDA_TOOL_SETTINGS(eda_timing_analysis)
 
200
{
 
201
        EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
 
202
        EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
 
203
        EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
 
204
        EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
 
205
        EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
 
206
        EDA_FLATTEN_BUSES = OFF;
 
207
        EDA_MAP_ILLEGAL_CHARACTERS = OFF;
 
208
        EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
 
209
        EDA_RUN_TOOL_AUTOMATICALLY = OFF;
 
210
        EDA_OUTPUT_DATA_FORMAT = NONE;
 
211
        EDA_LAUNCH_CMD_LINE_TOOL = OFF;
 
212
        USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
 
213
        RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
 
214
        RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
 
215
        RESYNTHESIS_RETIMING = FULL;
 
216
}
 
217
EDA_TOOL_SETTINGS(eda_board_design)
 
218
{
 
219
        EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
 
220
        EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
 
221
        EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
 
222
        EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
 
223
        EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
 
224
        EDA_FLATTEN_BUSES = OFF;
 
225
        EDA_MAP_ILLEGAL_CHARACTERS = OFF;
 
226
        EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
 
227
        EDA_RUN_TOOL_AUTOMATICALLY = OFF;
 
228
        EDA_OUTPUT_DATA_FORMAT = NONE;
 
229
        USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
 
230
        RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
 
231
        RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
 
232
        RESYNTHESIS_RETIMING = FULL;
 
233
}
 
234
EDA_TOOL_SETTINGS(eda_formal_verification)
 
235
{
 
236
        EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
 
237
        EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
 
238
        EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
 
239
        EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
 
240
        EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
 
241
        EDA_FLATTEN_BUSES = OFF;
 
242
        EDA_MAP_ILLEGAL_CHARACTERS = OFF;
 
243
        EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
 
244
        EDA_RUN_TOOL_AUTOMATICALLY = OFF;
 
245
        EDA_OUTPUT_DATA_FORMAT = NONE;
 
246
        USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
 
247
        RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
 
248
        RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
 
249
        RESYNTHESIS_RETIMING = FULL;
 
250
}
 
251
EDA_TOOL_SETTINGS(eda_palace)
 
252
{
 
253
        EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
 
254
        EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
 
255
        EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
 
256
        EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
 
257
        EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
 
258
        EDA_FLATTEN_BUSES = OFF;
 
259
        EDA_MAP_ILLEGAL_CHARACTERS = OFF;
 
260
        EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
 
261
        EDA_RUN_TOOL_AUTOMATICALLY = OFF;
 
262
        EDA_OUTPUT_DATA_FORMAT = NONE;
 
263
        RESYNTHESIS_RETIMING = FULL;
 
264
        RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
 
265
        RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
 
266
        USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
 
267
}
 
268
CLOCK(clk_120mhz)
 
269
{
 
270
        FMAX_REQUIREMENT = "120.0 MHz";
 
271
        INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
 
272
        DUTY_CYCLE = 50;
 
273
        DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
 
274
        MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
 
275
        INVERT_BASE_CLOCK = OFF;
 
276
}
 
277
CLOCK(usbclk)
 
278
{
 
279
        FMAX_REQUIREMENT = "48.0 MHz";
 
280
        INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
 
281
        DUTY_CYCLE = 50;
 
282
        DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
 
283
        MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
 
284
        INVERT_BASE_CLOCK = OFF;
 
285
}
 
286
CLOCK(SCLK)
 
287
{
 
288
        FMAX_REQUIREMENT = "1.0 MHz";
 
289
        INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
 
290
        DUTY_CYCLE = 50;
 
291
        DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
 
292
        MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
 
293
        INVERT_BASE_CLOCK = OFF;
 
294
}
 
295
CLOCK(adclk0)
 
296
{
 
297
        FMAX_REQUIREMENT = "60.0 MHz";
 
298
        INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
 
299
        DUTY_CYCLE = 50;
 
300
        DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
 
301
        MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
 
302
        INVERT_BASE_CLOCK = OFF;
 
303
}
 
304
CLOCK(adclk1)
 
305
{
 
306
        FMAX_REQUIREMENT = "60.0 MHz";
 
307
        INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
 
308
        DUTY_CYCLE = 50;
 
309
        DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
 
310
        MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
 
311
        INVERT_BASE_CLOCK = OFF;
 
312
}