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* Copyright 2007 Free Software Foundation, Inc.
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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#include "memory_map.h"
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#include "eth_mac_regs.h"
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#include "usrp2_i2c_addr.h"
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static ethernet_t ed_state;
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static ethernet_link_changed_callback_t ed_callback = 0;
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ethernet_register_link_changed_callback(ethernet_link_changed_callback_t new_callback)
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ed_callback = new_callback;
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ed_set_mac_speed(int speed)
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// putstr("ed_link_up: "); puthex16_nl(speed);
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ed_set_mac_speed(speed);
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if (ed_callback) // fire link changed callback
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(*ed_callback)(speed);
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// putstr("ed_link_down\n");
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if (ed_callback) // fire link changed callback
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ed_link_speed_change(int speed)
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print_flow_control(int flow_control)
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static const char *flow_control_msg[4] = {
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"NONE", "WE_TX", "WE_RX", "SYMMETRIC"
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putstr("ethernet flow control: ");
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puts(flow_control_msg[flow_control & 0x3]);
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check_flow_control_resolution(void)
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static const unsigned char table[16] = {
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// index = {local_asm, local_pause, partner_asm, partner_pause}
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FC_NONE, FC_NONE, FC_NONE, FC_NONE,
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FC_NONE, FC_SYMM, FC_NONE, FC_SYMM,
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FC_NONE, FC_NONE, FC_NONE, FC_WE_TX,
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FC_NONE, FC_SYMM, FC_WE_RX, FC_SYMM
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int us = eth_mac_miim_read(PHY_AUTONEG_ADV);
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int lp = eth_mac_miim_read(PHY_LP_ABILITY);
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int index = (((us >> 10) & 0x3) << 2) | ((lp >> 10) & 0x3);
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ed_state.flow_control = table[index];
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print_flow_control(ed_state.flow_control);
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* Read the PHY state register to determine link state and speed
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ed_check_phy_state(void)
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int lansr = eth_mac_miim_read(PHY_LINK_AN);
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eth_link_state_t new_state = LS_UNKNOWN;
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int new_speed = S_UNKNOWN;
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if (lansr & LANSR_LINK_GOOD){ // link's up
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switch (lansr & LANSR_SPEED_MASK){
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case LANSR_SPEED_100:
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case LANSR_SPEED_1000:
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new_speed = S_UNKNOWN;
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check_flow_control_resolution();
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else { // link's down
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puts(" NOT LINK_GOOD");
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new_speed = S_UNKNOWN;
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if (new_state != ed_state.link_state){
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ed_state.link_state = new_state; // remember new state
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if (new_state == LS_UP)
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ed_link_up(new_speed);
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else if (new_state == LS_DOWN)
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else if (new_state == LS_UP && new_speed != ed_state.link_speed){
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ed_state.link_speed = new_speed; // remember new speed
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ed_link_speed_change(new_speed);
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* This is fired when the ethernet PHY state changes
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eth_phy_irq_handler(unsigned irq)
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ed_check_phy_state();
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eth_mac_miim_write(PHY_INT_CLEAR, ~0); // clear all ints
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eth_mac_init(ethernet_mac_addr());
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ed_state.link_state = LS_UNKNOWN;
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ed_state.link_speed = S_UNKNOWN;
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// initialize MAC registers
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eth_mac->tx_hwmark = 0x1e;
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eth_mac->tx_lwmark = 0x19;
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eth_mac->crc_chk_en = 1;
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eth_mac->rx_max_length = 2048;
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// configure PAUSE frame stuff
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eth_mac->tx_pause_en = 1; // pay attn to pause frames sent to us
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eth_mac->pause_quanta_set = 38; // a bit more than 1 max frame 16kb/512 + fudge
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eth_mac->pause_frame_send_en = 1; // enable sending pause frames
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// setup PHY to interrupt on changes
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(PHY_INT_AN_CMPL // auto-neg completed
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| PHY_INT_NO_LINK // no link after auto-neg
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| PHY_INT_NO_HCD // no highest common denominator
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| PHY_INT_MAS_SLA_ERR // couldn't resolve master/slave
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| PHY_INT_PRL_DET_FLT // parallel detection fault
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| PHY_INT_LNK_CNG // link established or broken
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| PHY_INT_SPD_CNG // speed changed
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eth_mac_miim_write(PHY_INT_CLEAR, ~0); // clear all pending interrupts
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eth_mac_miim_write(PHY_INT_MASK, mask); // enable the ones we want
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pic_register_handler(IRQ_PHY, eth_phy_irq_handler);
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// Advertise our flow control configuation.
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// We and the link partner each specify two bits in the base page
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// related to autoconfiguration: NWAY_AR_PAUSE and NWAY_AR_ASM_DIR.
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// The bits say what a device is "willing" to do, not what may actually
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// happen as a result of the negotiation. There are 4 cases:
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// 0 0 I have no flow control capability.
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// 1 0 I both assert and respond to flow control.
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// 0 1 I assert flow control, but cannot respond. That is,
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// I want to be able to send PAUSE frames, but will ignore any
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// you send to me. (This is our configuration.)
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// 1 1 I can both assert and respond to flow control AND I am willing
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// to operate symmetrically OR asymmetrically in EITHER direction.
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// (We hope the link partner advertises this, otherwise we don't
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// get what we want.)
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int t = eth_mac_miim_read(PHY_AUTONEG_ADV);
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t &= ~(NWAY_AR_PAUSE | NWAY_AR_ASM_DIR);
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t |= NWAY_AR_ASM_DIR;
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// Say we can't to 10BASE-T or 100BASE-TX, half or full duplex
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t &= ~(NWAY_AR_10T_HD_CAPS | NWAY_AR_10T_FD_CAPS | NWAY_AR_100TX_HD_CAPS | NWAY_AR_100TX_FD_CAPS);
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eth_mac_miim_write(PHY_AUTONEG_ADV, t);
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// Restart autonegotation.
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// We want to ensure that we're advertising our PAUSE capabilities.
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t = eth_mac_miim_read(PHY_CTRL);
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eth_mac_miim_write(PHY_CTRL, t | MII_CR_RESTART_AUTO_NEG);
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unprogrammed(const u2_mac_addr_t *t)
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bool all_zeros = true;
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bool all_ones = true;
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for (i = 0; i < 6; i++){
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all_zeros &= t->addr[i] == 0x00;
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all_ones &= t->addr[i] == 0xff;
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return all_ones | all_zeros;
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static int8_t src_addr_initialized = false;
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static u2_mac_addr_t src_addr = {{
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0x00, 0x50, 0xC2, 0x85, 0x3f, 0xff
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const u2_mac_addr_t *
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ethernet_mac_addr(void)
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if (!src_addr_initialized){ // fetch from eeprom
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src_addr_initialized = true;
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// if we're simulating, don't read the EEPROM model, it's REALLY slow
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if (hwconfig_simulation_p())
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bool ok = eeprom_read(I2C_ADDR_MBOARD, MBOARD_MAC_ADDR, &tmp.addr[0], 6);
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if (!ok || unprogrammed(&tmp)){
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ethernet_set_mac_addr(const u2_mac_addr_t *t)
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bool ok = eeprom_write(I2C_ADDR_MBOARD, MBOARD_MAC_ADDR, &t->addr[0], 6);
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src_addr_initialized = true;
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ethernet_check_errors(void)
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// these registers are reset when read
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if (eth_mac_read_rmon(0x05) != 0)
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if (eth_mac_read_rmon(0x06) != 0)
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r |= RME_RX_FIFO_FULL;
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if (eth_mac_read_rmon(0x07) != 0)
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r |= RME_RX_2SHORT_2LONG;
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if (eth_mac_read_rmon(0x25) != 0)
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r |= RME_TX_JAM_DROP;
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if (eth_mac_read_rmon(0x26) != 0)
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r |= RME_TX_FIFO_UNDER;
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if (eth_mac_read_rmon(0x27) != 0)
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r |= RME_TX_FIFO_OVER;