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// Copyright 2008 Free Software Foundation, Inc.
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// This file is part of GNU Radio
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// GNU Radio is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either asversion 3, or (at your option)
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// GNU Radio is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// You should have received a copy of the GNU General Public License
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// along with GNU Radio; see the file COPYING. If not, write to
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// the Free Software Foundation, Inc., 51 Franklin Street,
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// Boston, MA 02110-1301, USA.
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#include <db_flexrf.h>
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#include <db_base_impl.h>
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// d'board i/o pin defs
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// Tx and Rx have shared defs, but different i/o regs
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#define AUX_RXAGC (1 << 8)
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#define POWER_UP (1 << 7) // enables power supply
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#define RX_TXN (1 << 6) // Tx only: T/R antenna switch for TX/RX port
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#define RX2_RX1N (1 << 6) // Rx only: antenna switch between RX2 and TX/RX port
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#define ENABLE (1 << 5) // enables mixer
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#define AUX_SEN (1 << 4)
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#define AUX_SCLK (1 << 3)
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#define PLL_LOCK_DETECT (1 << 2)
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#define AUX_SDO (1 << 1)
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#define CLOCK_OUT (1 << 0)
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flexrf_base::flexrf_base(usrp_basic_sptr _usrp, int which, int _power_on)
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: db_base(_usrp, which), d_power_on(_power_on)
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@param usrp: instance of usrp.source_c
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@param which: which side: 0 or 1 corresponding to side A or B respectively
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d_spi_format = SPI_FMT_MSB | SPI_FMT_HDR_0;
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usrp()->_write_oe(d_which, 0, 0xffff); // turn off all outputs
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_enable_refclk(false); // disable refclk
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flexrf_base::~flexrf_base()
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flexrf_base::_write_all(int R, int control, int N)
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Write R counter latch, control latch and N counter latch to VCO.
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Adds 10ms delay between writing control and N if this is first call.
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This is the required power-up sequence.
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@param R: 24-bit R counter latch
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@param control: 24-bit control latch
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@param N: 24-bit N counter latch
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_write_control(control);
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flexrf_base::_write_control(int control)
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_write_it((control & ~0x3) | 0);
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flexrf_base::_write_R(int R)
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_write_it((R & ~0x3) | 1);
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flexrf_base::_write_N(int N)
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_write_it((N & ~0x3) | 2);
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flexrf_base::_write_it(int v)
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s[0] = (char)((v >> 16) & 0xff);
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s[1] = (char)((v >> 8) & 0xff);
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s[2] = (char)(v & 0xff);
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std::string str(s, 3);
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usrp()->_write_spi(0, d_spi_enable, d_spi_format, str);
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flexrf_base::_lock_detect()
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@returns: the value of the VCO/PLL lock detect bit.
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if(usrp()->read_io(d_which) & PLL_LOCK_DETECT) {
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else { // Give it a second chance
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// FIXME: make portable sleep
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t.tv_nsec = 100000000;
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if(usrp()->read_io(d_which) & PLL_LOCK_DETECT) {
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flexrf_base::_compute_regs(double freq, int &retR, int &retcontrol,
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int &retN, double &retfreq)
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Determine values of R, control, and N registers, along with actual freq.
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@param freq: target frequency in Hz
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@returns: (R, control, N, actual_freq)
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@rtype: tuple(int, int, int, float)
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Override this in derived classes.
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//raise NotImplementedError;
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throw std::runtime_error("_compute_regs called from flexrf_base\n");
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flexrf_base::_compute_control_reg()
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return d_common->_compute_control_reg();
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flexrf_base::_refclk_divisor()
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return d_common->_refclk_divisor();
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flexrf_base::_refclk_freq()
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return 64e6/_refclk_divisor();
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flexrf_base::set_freq(double freq)
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@returns (ok, actual_baseband_freq) where:
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ok is True or False and indicates success or failure,
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actual_baseband_freq is the RF frequency that corresponds to DC in the IF.
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struct freq_result_t args = {false, 0};
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// Offsetting the LO helps get the Tx carrier leakage out of the way.
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// This also ensures that on Rx, we're not getting hosed by the
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// FPGA's DC removal loop's time constant. We were seeing a
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// problem when running with discontinuous transmission.
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// Offsetting the LO made the problem go away.
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_compute_regs(freq, R, control, N, actual_freq);
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_write_all(R, control, N);
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args.ok = _lock_detect();
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args.baseband_freq = actual_freq;
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flexrf_base::_set_pga(float pga_gain)
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usrp()->set_pga(0, pga_gain);
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usrp()->set_pga(1, pga_gain);
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usrp()->set_pga(2, pga_gain);
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usrp()->set_pga(3, pga_gain);
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flexrf_base::is_quadrature()
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Return True if this board requires both I & Q analog channels.
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This bit of info is useful when setting up the USRP Rx mux register.
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flexrf_base::freq_min()
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return d_common->freq_min();
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flexrf_base::freq_max()
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return d_common->freq_max();
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// ----------------------------------------------------------------
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flexrf_base_tx::flexrf_base_tx(usrp_basic_sptr _usrp, int which, int _power_on)
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: flexrf_base(_usrp, which, _power_on)
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@param usrp: instance of usrp.sink_c
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@param which: 0 or 1 corresponding to side TX_A or TX_B respectively.
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d_spi_enable = SPI_ENABLE_TX_A;
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d_spi_enable = SPI_ENABLE_TX_B;
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// power up the transmit side, but don't enable the mixer
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usrp()->_write_oe(d_which,(POWER_UP|RX_TXN|ENABLE), 0xffff);
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usrp()->write_io(d_which, (power_on()|RX_TXN), (POWER_UP|RX_TXN|ENABLE));
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set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
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flexrf_base_tx::~flexrf_base_tx()
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flexrf_base_tx::shutdown()
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// fprintf(stderr, "flexrf_base_tx::shutdown d_is_shutdown = %d\n", d_is_shutdown);
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d_is_shutdown = true;
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// do whatever there is to do to shutdown
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// Power down and leave the T/R switch in the R position
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usrp()->write_io(d_which, (power_off()|RX_TXN), (POWER_UP|RX_TXN|ENABLE));
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// Power down VCO/PLL
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_write_control(_compute_control_reg());
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_enable_refclk(false); // turn off refclk
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flexrf_base_tx::set_auto_tr(bool on)
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ok &= set_atr_mask (RX_TXN | ENABLE);
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ok &= set_atr_txval(0 | ENABLE);
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ok &= set_atr_rxval(RX_TXN | 0);
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ok &= set_atr_mask (0);
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ok &= set_atr_txval(0);
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ok &= set_atr_rxval(0);
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flexrf_base_tx::set_enable(bool on)
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Enable transmitter if on is true
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int mask = RX_TXN | ENABLE;
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return usrp()->write_io(d_which, v, mask);
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flexrf_base_tx::gain_min()
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return usrp()->pga_max();
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flexrf_base_tx::gain_max()
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return usrp()->pga_max();
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flexrf_base_tx::gain_db_per_step()
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flexrf_base_tx::set_gain(float gain)
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@param gain: gain in decibels
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return _set_pga(usrp()->pga_max());
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/**************************************************************************/
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flexrf_base_rx::flexrf_base_rx(usrp_basic_sptr _usrp, int which, int _power_on)
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: flexrf_base(_usrp, which, _power_on)
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@param usrp: instance of usrp.source_c
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@param which: 0 or 1 corresponding to side RX_A or RX_B respectively.
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d_spi_enable = SPI_ENABLE_RX_A;
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d_spi_enable = SPI_ENABLE_RX_B;
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usrp()->_write_oe(d_which, (POWER_UP|RX2_RX1N|ENABLE), 0xffff);
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usrp()->write_io(d_which, (power_on()|RX2_RX1N|ENABLE),
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(POWER_UP|RX2_RX1N|ENABLE));
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// set up for RX on TX/RX port
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select_rx_antenna("TX/RX");
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bypass_adc_buffers(true);
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flexrf_base_rx::~flexrf_base_rx()
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flexrf_base_rx::shutdown()
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// fprintf(stderr, "flexrf_base_rx::shutdown d_is_shutdown = %d\n", d_is_shutdown);
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d_is_shutdown = true;
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// do whatever there is to do to shutdown
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usrp()->common_write_io(C_RX, d_which, power_off(), (POWER_UP|ENABLE));
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// Power down VCO/PLL
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// fprintf(stderr, "flexrf_base_rx::shutdown before _write_control\n");
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_write_control(_compute_control_reg());
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// fprintf(stderr, "flexrf_base_rx::shutdown before _enable_refclk\n");
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_enable_refclk(false); // turn off refclk
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// fprintf(stderr, "flexrf_base_rx::shutdown before set_auto_tr\n");
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// fprintf(stderr, "flexrf_base_rx::shutdown after set_auto_tr\n");
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flexrf_base_rx::set_auto_tr(bool on)
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ok &= set_atr_mask (ENABLE);
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ok &= set_atr_txval( 0);
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ok &= set_atr_rxval(ENABLE);
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ok &= set_atr_mask (0);
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ok &= set_atr_txval(0);
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ok &= set_atr_rxval(0);
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flexrf_base_rx::select_rx_antenna(int which_antenna)
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Specify which antenna port to use for reception.
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@param which_antenna: either 'TX/RX' or 'RX2'
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if(which_antenna == 0) {
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usrp()->write_io(d_which, 0,RX2_RX1N);
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else if(which_antenna == 1) {
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usrp()->write_io(d_which, RX2_RX1N, RX2_RX1N);
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// throw std::invalid_argument("which_antenna must be either 'TX/RX' or 'RX2'\n");
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flexrf_base_rx::select_rx_antenna(const std::string &which_antenna)
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Specify which antenna port to use for reception.
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@param which_antenna: either 'TX/RX' or 'RX2'
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if(which_antenna == "TX/RX") {
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usrp()->write_io(d_which, 0, RX2_RX1N);
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else if(which_antenna == "RX2") {
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usrp()->write_io(d_which, RX2_RX1N, RX2_RX1N);
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// throw std::invalid_argument("which_antenna must be either 'TX/RX' or 'RX2'\n");
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flexrf_base_rx::set_gain(float gain)
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@param gain: gain in decibels
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gain = std::max(gain_min(), std::min(gain, gain_max()));
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float pga_gain, agc_gain;
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float V_maxgain, V_mingain, V_fullscale, dac_value;
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float maxgain = gain_max() - usrp()->pga_max();
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float mingain = gain_min();
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pga_gain = gain-maxgain;
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assert(pga_gain <= usrp()->pga_max());
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dac_value = (agc_gain*(V_maxgain-V_mingain)/(maxgain-mingain) + V_mingain)*4096/V_fullscale;
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assert(dac_value>=0 && dac_value<4096);
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return (usrp()->write_aux_dac(d_which, 0, int(dac_value))
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&& _set_pga(int(pga_gain)));
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// ----------------------------------------------------------------
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_AD4360_common::_AD4360_common()
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// R-Register Common Values
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d_R_RSV = 0; // bits 23,22
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d_BSC = 3; // bits 21,20 Div by 8 to be safe
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d_TEST = 0; // bit 19
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d_ABP = 0; // bit 17,16 3ns
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// N-Register Common Values
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d_N_RSV = 0; // bit 7
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// Control Register Common Values
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d_PD = 0; // bits 21,20 Normal operation
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d_PL = 0; // bits 13,12 11mA
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d_MTLD = 1; // bit 11 enabled
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d_CPG = 0; // bit 10 CP setting 1
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d_CP3S = 0; // bit 9 Normal
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d_PDP = 1; // bit 8 Positive
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d_MUXOUT = 1; // bits 7:5 Digital Lock Detect
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d_CR = 0; // bit 4 Normal
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d_PC = 1; // bits 3,2 Core power 10mA
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_AD4360_common::~_AD4360_common()
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_AD4360_common::_compute_regs(double refclk_freq, double freq, int &retR,
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int &retcontrol, int &retN, double &retfreq)
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Determine values of R, control, and N registers, along with actual freq.
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@param freq: target frequency in Hz
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@returns: (R, control, N, actual_freq)
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@rtype: tuple(int, int, int, float)
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// Band-specific N-Register Values
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//float phdet_freq = _refclk_freq()/d_R_DIV;
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double phdet_freq = refclk_freq/d_R_DIV;
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double desired_n = round(freq*d_freq_mult/phdet_freq);
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double actual_freq = desired_n * phdet_freq;
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int B = floor(desired_n/_prescaler());
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int A = desired_n - _prescaler()*B;
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d_B_DIV = int(B); // bits 20:8
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d_A_DIV = int(A); // bit 6:2
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//assert db_B_DIV >= db_A_DIV
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if(d_B_DIV < d_A_DIV) {
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int R = (d_R_RSV<<22) | (d_BSC<<20) | (d_TEST<<19) |
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(d_LDP<<18) | (d_ABP<<16) | (d_R_DIV<<2);
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int control = _compute_control_reg();
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int N = (d_DIVSEL<<23) | (d_DIV2<<22) | (d_CPGAIN<<21) |
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(d_B_DIV<<8) | (d_N_RSV<<7) | (d_A_DIV<<2);
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retcontrol = control;
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retfreq = actual_freq/d_freq_mult;
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_AD4360_common::_compute_control_reg()
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int control = (d_P<<22) | (d_PD<<20) | (d_CP2<<17) | (d_CP1<<14)
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| (d_PL<<12) | (d_MTLD<<11) | (d_CPG<<10) | (d_CP3S<<9) | (d_PDP<<8)
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| (d_MUXOUT<<5) | (d_CR<<4) | (d_PC<<2);
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_AD4360_common::_refclk_divisor()
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Return value to stick in REFCLK_DIVISOR register
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_AD4360_common::_prescaler()
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//----------------------------------------------------------------------
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_2400_common::_2400_common()
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// Band-specific R-Register Values
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d_R_DIV = 16; // bits 15:2
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// Band-specific C-Register values
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d_P = 1; // bits 23,22 Div by 16/17
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d_CP2 = 7; // bits 19:17
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d_CP1 = 7; // bits 16:14
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// Band specifc N-Register Values
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d_DIVSEL = 0; // bit 23
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d_DIV2 = 0; // bit 22
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d_CPGAIN = 0; // bit 21
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_2400_common::freq_min()
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_2400_common::freq_max()
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//----------------------------------------------------------------------
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_1200_common::_1200_common()
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// Band-specific R-Register Values
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d_R_DIV = 16; // bits 15:2 DIV by 16 for a 1 MHz phase detector freq
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// Band-specific C-Register values
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d_P = 1; // bits 23,22 Div by 16/17
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d_CP2 = 7; // bits 19:17 1.25 mA
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d_CP1 = 7; // bits 16:14 1.25 mA
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// Band specifc N-Register Values
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d_DIVSEL = 0; // bit 23
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d_DIV2 = 1; // bit 22
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d_CPGAIN = 0; // bit 21
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_1200_common::freq_min()
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_1200_common::freq_max()
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//-------------------------------------------------------------------------
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_1800_common::_1800_common()
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// Band-specific R-Register Values
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d_R_DIV = 16; // bits 15:2 DIV by 16 for a 1 MHz phase detector freq
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// Band-specific C-Register values
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d_P = 1; // bits 23,22 Div by 16/17
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d_CP2 = 7; // bits 19:17 1.25 mA
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d_CP1 = 7; // bits 16:14 1.25 mA
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// Band specifc N-Register Values
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d_DIVSEL = 0; // bit 23
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d_DIV2 = 0; // bit 22
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d_CPGAIN = 0; // bit 21
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_1800_common::freq_min()
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_1800_common::freq_max()
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//-------------------------------------------------------------------------
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_900_common::_900_common()
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// Band-specific R-Register Values
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d_R_DIV = 16; // bits 15:2 DIV by 16 for a 1 MHz phase detector freq
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// Band-specific C-Register values
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d_P = 1; // bits 23,22 Div by 16/17
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d_CP2 = 7; // bits 19:17 1.25 mA
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d_CP1 = 7; // bits 16:14 1.25 mA
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// Band specifc N-Register Values
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d_DIVSEL = 0; // bit 23
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d_DIV2 = 1; // bit 22
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d_CPGAIN = 0; // bit 21
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_900_common::freq_min()
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_900_common::freq_max()
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//-------------------------------------------------------------------------
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_400_common::_400_common()
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// Band-specific R-Register Values
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d_R_DIV = 16; // bits 15:2
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// Band-specific C-Register values
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d_P = 0; // bits 23,22 Div by 8/9
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d_CP2 = 7; // bits 19:17 1.25 mA
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d_CP1 = 7; // bits 16:14 1.25 mA
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// Band specifc N-Register Values These are different for TX/RX
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d_DIVSEL = 0; // bit 23
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d_CPGAIN = 0; // bit 21
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_400_common::freq_min()
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_400_common::freq_max()
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d_DIV2 = 1; // bit 22
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d_DIV2 = 0; // bit 22 // RX side has built-in DIV2 in AD8348
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//------------------------------------------------------------
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db_flexrf_2400_tx::db_flexrf_2400_tx(usrp_basic_sptr usrp, int which)
817
: flexrf_base_tx(usrp, which)
819
d_common = new _2400_common();
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db_flexrf_2400_tx::~db_flexrf_2400_tx()
827
db_flexrf_2400_tx::_compute_regs(double freq, int &retR, int &retcontrol,
828
int &retN, double &retfreq)
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return d_common->_compute_regs(_refclk_freq(), freq, retR,
831
retcontrol, retN, retfreq);
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db_flexrf_2400_rx::db_flexrf_2400_rx(usrp_basic_sptr usrp, int which)
837
: flexrf_base_rx(usrp, which)
839
d_common = new _2400_common();
840
set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
843
db_flexrf_2400_rx::~db_flexrf_2400_rx()
848
db_flexrf_2400_rx::gain_min()
850
return usrp()->pga_min();
854
db_flexrf_2400_rx::gain_max()
856
return usrp()->pga_max()+70;
860
db_flexrf_2400_rx::gain_db_per_step()
867
db_flexrf_2400_rx::i_and_q_swapped()
873
db_flexrf_2400_rx::_compute_regs(double freq, int &retR, int &retcontrol,
874
int &retN, double &retfreq)
876
return d_common->_compute_regs(_refclk_freq(), freq, retR,
877
retcontrol, retN, retfreq);
880
//------------------------------------------------------------
883
db_flexrf_1200_tx::db_flexrf_1200_tx(usrp_basic_sptr usrp, int which)
884
: flexrf_base_tx(usrp, which)
886
d_common = new _1200_common();
889
db_flexrf_1200_tx::~db_flexrf_1200_tx()
894
db_flexrf_1200_tx::_compute_regs(double freq, int &retR, int &retcontrol,
895
int &retN, double &retfreq)
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return d_common->_compute_regs(_refclk_freq(), freq, retR,
898
retcontrol, retN, retfreq);
904
db_flexrf_1200_rx::db_flexrf_1200_rx(usrp_basic_sptr usrp, int which)
905
: flexrf_base_rx(usrp, which)
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d_common = new _1200_common();
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set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
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db_flexrf_1200_rx::~db_flexrf_1200_rx()
916
db_flexrf_1200_rx::gain_min()
918
return usrp()->pga_min();
922
db_flexrf_1200_rx::gain_max()
924
return usrp()->pga_max()+70;
928
db_flexrf_1200_rx::gain_db_per_step()
934
db_flexrf_1200_rx::i_and_q_swapped()
940
db_flexrf_1200_rx::_compute_regs(double freq, int &retR, int &retcontrol,
941
int &retN, double &retfreq)
943
return d_common->_compute_regs(_refclk_freq(), freq, retR,
944
retcontrol, retN, retfreq);
948
//------------------------------------------------------------
951
db_flexrf_1800_tx::db_flexrf_1800_tx(usrp_basic_sptr usrp, int which)
952
: flexrf_base_tx(usrp, which)
954
d_common = new _1800_common();
957
db_flexrf_1800_tx::~db_flexrf_1800_tx()
962
db_flexrf_1800_tx::_compute_regs(double freq, int &retR, int &retcontrol,
963
int &retN, double &retfreq)
965
return d_common->_compute_regs(_refclk_freq(), freq, retR,
966
retcontrol, retN, retfreq);
971
db_flexrf_1800_rx::db_flexrf_1800_rx(usrp_basic_sptr usrp, int which)
972
: flexrf_base_rx(usrp, which)
974
d_common = new _1800_common();
975
set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
978
db_flexrf_1800_rx::~db_flexrf_1800_rx()
984
db_flexrf_1800_rx::gain_min()
986
return usrp()->pga_min();
990
db_flexrf_1800_rx::gain_max()
992
return usrp()->pga_max()+70;
996
db_flexrf_1800_rx::gain_db_per_step()
1002
db_flexrf_1800_rx::i_and_q_swapped()
1008
db_flexrf_1800_rx::_compute_regs(double freq, int &retR, int &retcontrol,
1009
int &retN, double &retfreq)
1011
return d_common->_compute_regs(_refclk_freq(), freq, retR,
1012
retcontrol, retN, retfreq);
1016
//------------------------------------------------------------
1019
db_flexrf_900_tx::db_flexrf_900_tx(usrp_basic_sptr usrp, int which)
1020
: flexrf_base_tx(usrp, which)
1022
d_common = new _900_common();
1025
db_flexrf_900_tx::~db_flexrf_900_tx()
1030
db_flexrf_900_tx::_compute_regs(double freq, int &retR, int &retcontrol,
1031
int &retN, double &retfreq)
1033
return d_common->_compute_regs(_refclk_freq(), freq, retR,
1034
retcontrol, retN, retfreq);
1038
db_flexrf_900_rx::db_flexrf_900_rx(usrp_basic_sptr usrp, int which)
1039
: flexrf_base_rx(usrp, which)
1041
d_common = new _900_common();
1042
set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
1045
db_flexrf_900_rx::~db_flexrf_900_rx()
1050
db_flexrf_900_rx::gain_min()
1052
return usrp()->pga_min();
1056
db_flexrf_900_rx::gain_max()
1058
return usrp()->pga_max()+70;
1062
db_flexrf_900_rx::gain_db_per_step()
1068
db_flexrf_900_rx::i_and_q_swapped()
1074
db_flexrf_900_rx::_compute_regs(double freq, int &retR, int &retcontrol,
1075
int &retN, double &retfreq)
1077
return d_common->_compute_regs(_refclk_freq(), freq, retR,
1078
retcontrol, retN, retfreq);
1081
//------------------------------------------------------------
1084
db_flexrf_400_tx::db_flexrf_400_tx(usrp_basic_sptr usrp, int which)
1085
: flexrf_base_tx(usrp, which, POWER_UP)
1087
d_common = new _400_tx();
1090
db_flexrf_400_tx::~db_flexrf_400_tx()
1095
db_flexrf_400_tx::_compute_regs(double freq, int &retR, int &retcontrol,
1096
int &retN, double &retfreq)
1098
return d_common->_compute_regs(_refclk_freq(), freq, retR,
1099
retcontrol, retN, retfreq);
1104
db_flexrf_400_rx::db_flexrf_400_rx(usrp_basic_sptr usrp, int which)
1105
: flexrf_base_rx(usrp, which, POWER_UP)
1107
d_common = new _400_rx();
1108
set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
1111
db_flexrf_400_rx::~db_flexrf_400_rx()
1116
db_flexrf_400_rx::gain_min()
1118
return usrp()->pga_min();
1122
db_flexrf_400_rx::gain_max()
1124
return usrp()->pga_max()+45;
1129
db_flexrf_400_rx::gain_db_per_step()
1136
db_flexrf_400_rx::i_and_q_swapped()
1142
db_flexrf_400_rx::_compute_regs(double freq, int &retR, int &retcontrol,
1143
int &retN, double &retfreq)
1145
return d_common->_compute_regs(_refclk_freq(), freq, retR,
1146
retcontrol, retN, retfreq);
added
removed
usrp/host/lib/legacy/db_flexrf.cc
