~ubuntu-branches/ubuntu/precise/mame/precise-proposed

Viewing changes to src/emu/cpu/h83002/h8speriph.c

Committer: Package Import Robot
Author(s): Cesare Falco
Date: 2011-11-30 18:50:10 UTC
mfrom: (1.1.4)
Revision ID: package-import@ubuntu.com-20111130185010-02hcxybht1mn082w

Tags: 0.144-0ubuntu1

* New upstream release (LP: #913550)
* mame.install:
- Added artwork/ images to be used with -effect switch
- Be more selective with hash/ contents
* contrib/mame.ini: added /usr/share/games/mame/artwork/ to artpath

files added:
hash/neogeo.xml

src/build/makedev.c

src/emu/cpu/h83002/h8speriph.c

src/emu/cpu/scudsp

src/emu/cpu/scudsp/scudspdasm.c

src/emu/cpu/sh4/sh3comn.c

src/emu/cpu/sh4/sh3comn.h

src/emu/cpu/sh4/sh4dmac.c

src/emu/cpu/sh4/sh4dmac.h

src/emu/cpu/sh4/sh4tmu.c

src/emu/cpu/sh4/sh4tmu.h

src/emu/device.c

src/emu/device.h

src/emu/dinetwork.c

src/emu/dinetwork.h

src/emu/diserial.c

src/emu/diserial.h

src/emu/imagedev/floppy.c

src/emu/imagedev/floppy.h

src/emu/imagedev/serial.c

src/emu/imagedev/serial.h

src/emu/ioport.c

src/emu/ioport.h

src/emu/layout/noscreens.lay

src/emu/layout/quadhsxs.lay

src/emu/machine/6551acia.c

src/emu/machine/6551acia.h

src/emu/machine/am8530h.c

src/emu/machine/am8530h.h

src/emu/machine/amigafdc.c

src/emu/machine/amigafdc.h

src/emu/machine/i8251.c

src/emu/machine/i8251.h

src/emu/machine/ncr539x.c

src/emu/machine/ncr539x.h

src/emu/machine/rtc9701.c

src/emu/machine/rtc9701.h

src/emu/sound/awacs.c

src/emu/sound/awacs.h

src/emu/sound/ymz770.c

src/emu/sound/ymz770.h

src/emu/video/h63484.c

src/emu/video/h63484.h

src/lib/formats/dsk_dsk.h

src/lib/formats/hxcmfm_dsk.c

src/lib/formats/hxcmfm_dsk.h

src/lib/formats/ipf_dsk.c

src/lib/formats/ipf_dsk.h

src/lib/formats/mfi_dsk.c

src/lib/formats/mfi_dsk.h

src/lib/formats/st_dsk.c

src/lib/formats/st_dsk.h

src/lib/softfloat/fpu_constant.h

src/lib/softfloat/fsincos.c

src/lib/util/chdcd.c

src/lib/util/chdcd.h

src/mame/audio/decobsmt.c

src/mame/audio/decobsmt.h

src/mame/drivers/30test.c

src/mame/drivers/aces1.c

src/mame/drivers/acesp.c

src/mame/drivers/aristmk6.c

src/mame/drivers/astrafr.c

src/mame/drivers/astropc.c

src/mame/drivers/atronic.c

src/mame/drivers/belatra.c

src/mame/drivers/bfm_sc4.c

src/mame/drivers/bfm_sc45.h

src/mame/drivers/bfm_sc5.c

src/mame/drivers/bfm_swp.c

src/mame/drivers/bfmsys83.c

src/mame/drivers/bgt.c

src/mame/drivers/castle.c

src/mame/drivers/cobra.c

src/mame/drivers/cupidon.c

src/mame/drivers/ecoinf1.c

src/mame/drivers/ecoinf2.c

src/mame/drivers/ecoinf3.c

src/mame/drivers/ecoinfr.c

src/mame/drivers/extrema.c

src/mame/drivers/galgame.c

src/mame/drivers/gamtor.c

src/mame/drivers/globalfr.c

src/mame/drivers/hazelgr.c

src/mame/drivers/igspc.c

src/mame/drivers/jeutel.c

src/mame/drivers/jpmmps.c

src/mame/drivers/jpms80.c

src/mame/drivers/jpmsys7.c

src/mame/drivers/kas89.c

src/mame/drivers/konendev.c

src/mame/drivers/maygayep.c

src/mame/drivers/maygaysw.c

src/mame/drivers/mmm.c

src/mame/drivers/mpu2.c

src/mame/drivers/mpu4vid.c

src/mame/drivers/nexus3d.c

src/mame/drivers/pluto5.c

src/mame/drivers/proconn.c

src/mame/drivers/segajw.c

src/mame/drivers/spectra.c

src/mame/drivers/splus.c

src/mame/drivers/sshot.c

src/mame/drivers/stellafr.c

src/mame/drivers/stv.c

src/mame/drivers/summit.c

src/mame/drivers/sumt8035.c

src/mame/drivers/tapatune.c

src/mame/drivers/tmspoker.c

src/mame/drivers/tonton.c

src/mame/drivers/umipoker.c

src/mame/drivers/unkfr.c

src/mame/drivers/unkpcp.c

src/mame/drivers/wms.c

src/mame/includes/galpnipt.h

src/mame/includes/mpu4.h

src/mame/includes/segaipt.h

src/mame/layout/30test.lay

src/mame/layout/bingowng.lay

src/mame/layout/cosmicm.lay

src/mame/layout/crmaze2p.lay

src/mame/layout/crmaze4p.lay

src/mame/layout/destroyr.lay

src/mame/layout/kas89.lay

src/mame/layout/kingdrby.lay

src/mame/layout/novoplay.lay

src/mame/layout/peyper.lay

src/mame/layout/saiyukip.lay

src/mame/layout/splus.lay

src/mame/machine/awboard.c

src/mame/machine/awboard.h

src/mame/machine/bfm_comn.c

src/mame/machine/bfm_comn.h

src/mame/machine/naomibd.h

src/mame/machine/naomig1.c

src/mame/machine/naomig1.h

src/mame/machine/naomigd.c

src/mame/machine/naomigd.h

src/mame/machine/naomim1.c

src/mame/machine/naomim1.h

src/mame/machine/naomim2.c

src/mame/machine/naomim2.h

src/mame/machine/naomim4.c

src/mame/machine/naomim4.h

src/mame/machine/naomirom.c

src/mame/machine/naomirom.h

src/mame/machine/smpc.c

src/mame/machine/smpc.h

src/mame/mame_dev.lst

src/mame/tiny_dev.lst

src/mame/video/tecmosys.c

src/osd/osdnet.c

src/osd/osdnet.h

src/osd/sdl/netdev.c

src/osd/sdl/netdev.h

src/osd/sdl/netdev_tap.c

src/osd/sdl/netdev_tap.h

src/osd/sdl/taputil.sh

src/osd/windows/netdev.c

src/osd/windows/netdev.h

src/osd/windows/netdev_pcap.c

src/osd/windows/netdev_pcap.h

src/osd/windows/winfile.h

src/osd/windows/winsocket.c

files removed:
src/emu/devintrf.c

src/emu/devintrf.h

src/emu/inptport.c

src/emu/inptport.h

src/emu/layout/pinball.lay

src/mame/drivers/cavesh3.c

src/mame/drivers/mpu4drvr.c

src/mame/drivers/stvinit.c

src/mame/includes/naomibd.h

src/mame/machine/gdcrypt.c

src/mame/machine/naomim4decoder.c

src/mame/machine/naomim4decoder.h

src/tools/chdcd.c

src/tools/chdcd.h

files modified:
debian/changelog

debian/contrib/mame.ini

debian/control

debian/copyright

debian/mame-tools.install

debian/mame.install

debian/rules

docs/hlsl.txt

hash/softwarelist.dtd

hlsl/phosphor.fx

hlsl/prescale.fx

makefile

src/build/build.mak

src/build/makedep.c

src/build/makelist.c

src/emu/addrmap.c

src/emu/addrmap.h

src/emu/attotime.h

src/emu/audit.c

src/emu/audit.h

src/emu/clifront.c

src/emu/cothread.h

src/emu/cpu/am29000/am29000.c

src/emu/cpu/apexc/apexcdsm.c

src/emu/cpu/avr8/avr8.c

src/emu/cpu/avr8/avr8.h

src/emu/cpu/avr8/avr8dasm.c

src/emu/cpu/cosmac/cosmac.c

src/emu/cpu/cosmac/cosmac.h

src/emu/cpu/cp1610/cp1610.c

src/emu/cpu/cpu.mak

src/emu/cpu/drcbex64.c

src/emu/cpu/dsp56k/inst.h

src/emu/cpu/esrip/esrip.c

src/emu/cpu/g65816/g65816.c

src/emu/cpu/h83002/h8.h

src/emu/cpu/h83002/h8_16.c

src/emu/cpu/h83002/h8_8.c

src/emu/cpu/h83002/h8disasm.c

src/emu/cpu/h83002/h8ops.h

src/emu/cpu/h83002/h8periph.c

src/emu/cpu/h83002/h8priv.h

src/emu/cpu/hd6309/6309ops.c

src/emu/cpu/hd6309/hd6309.c

src/emu/cpu/i386/i386.c

src/emu/cpu/i386/i386op16.c

src/emu/cpu/i386/i386op32.c

src/emu/cpu/i386/i386ops.c

src/emu/cpu/i386/i386ops.h

src/emu/cpu/i386/i386priv.h

src/emu/cpu/i386/i486ops.c

src/emu/cpu/i386/x87ops.c

src/emu/cpu/i4004/i4004.c

src/emu/cpu/i8008/i8008.c

src/emu/cpu/i86/i86.txt

src/emu/cpu/i86/instr186.c

src/emu/cpu/i86/instr286.c

src/emu/cpu/i86/instr86.c

src/emu/cpu/i86/instr86.h

src/emu/cpu/i860/i860dec.c

src/emu/cpu/i860/i860dis.c

src/emu/cpu/konami/konami.c

src/emu/cpu/m37710/m37710.c

src/emu/cpu/m37710/m37710cm.h

src/emu/cpu/m37710/m37710op.h

src/emu/cpu/m68000/m68000.h

src/emu/cpu/m68000/m68k_in.c

src/emu/cpu/m68000/m68kcpu.c

src/emu/cpu/m68000/m68kcpu.h

src/emu/cpu/m68000/m68kdasm.c

src/emu/cpu/m68000/m68kfpu.c

src/emu/cpu/m68000/m68kmake.c

src/emu/cpu/m68000/m68kmmu.h

src/emu/cpu/m6805/m6805.c

src/emu/cpu/m6809/m6809.c

src/emu/cpu/mb86233/mb86233.c

src/emu/cpu/mc68hc11/hc11ops.c

src/emu/cpu/mc68hc11/hc11ops.h

src/emu/cpu/mc68hc11/mc68hc11.c

src/emu/cpu/mc68hc11/mc68hc11.h

src/emu/cpu/nec/nec.c

src/emu/cpu/nec/necinstr.c

src/emu/cpu/nec/necpriv.h

src/emu/cpu/nec/v25.c

src/emu/cpu/nec/v25instr.c

src/emu/cpu/nec/v25priv.h

src/emu/cpu/pdp1/pdp1.c

src/emu/cpu/pdp1/tx0.c

src/emu/cpu/pic16c5x/dis16c5x.c

src/emu/cpu/pic16c5x/pic16c5x.c

src/emu/cpu/pic16c62x/dis16c62x.c

src/emu/cpu/pic16c62x/pic16c62x.c

src/emu/cpu/powerpc/ppccom.c

src/emu/cpu/powerpc/ppccom.h

src/emu/cpu/powerpc/ppcdrc.c

src/emu/cpu/psx/psx.c

src/emu/cpu/sc61860/readpc.c

src/emu/cpu/sc61860/scdasm.c

src/emu/cpu/scmp/scmp.c

src/emu/cpu/sh2/sh2comn.c

src/emu/cpu/sh4/sh4.c

src/emu/cpu/sh4/sh4.h

src/emu/cpu/sh4/sh4comn.c

src/emu/cpu/sh4/sh4comn.h

src/emu/cpu/sh4/sh4dasm.c

src/emu/cpu/sh4/sh4regs.h

src/emu/cpu/superfx/superfx.c

src/emu/cpu/t11/t11.c

src/emu/cpu/tlcs900/dasm900.c

src/emu/cpu/tms0980/tms0980.c

src/emu/cpu/tms32010/dis32010.c

src/emu/cpu/tms32025/dis32025.c

src/emu/cpu/tms32025/tms32025.c

src/emu/cpu/tms32051/32051ops.c

src/emu/cpu/tms32051/tms32051.c

src/emu/cpu/tms57002/tmsmake.c

src/emu/cpu/tms9900/99xxcore.h

src/emu/cpu/upd7725/upd7725.c

src/emu/cpu/upd7725/upd7725.h

src/emu/cpu/z80/z80.c

src/emu/crsshair.h

src/emu/debug/debugcpu.c

src/emu/debug/debugvw.c

src/emu/debug/debugvw.h

src/emu/debug/dvdisasm.c

src/emu/debug/express.c

src/emu/deprecat.h

src/emu/devcpu.c

src/emu/devcpu.h

src/emu/diexec.c

src/emu/diexec.h

src/emu/diimage.c

src/emu/dimemory.c

src/emu/dislot.c

src/emu/dislot.h

src/emu/disound.c

src/emu/disound.h

src/emu/driver.h

src/emu/drivers/xtal.h

src/emu/eigccx86.h

src/emu/eminline.h

src/emu/emu.h

src/emu/emu.mak

src/emu/emualloc.h

src/emu/emuopts.c

src/emu/emuopts.h

src/emu/emupal.c

src/emu/fileio.h

src/emu/hash.c

src/emu/hash.h

src/emu/hashfile.c

src/emu/imagedev/cartslot.c

src/emu/imagedev/cartslot.h

src/emu/imagedev/cassette.c

src/emu/imagedev/cassette.h

src/emu/imagedev/chd_cd.c

src/emu/imagedev/flopdrv.c

src/emu/imagedev/flopdrv.h

src/emu/imagedev/harddriv.c

src/emu/imagedev/multcart.c

src/emu/imagedev/multcart.h

src/emu/info.c

src/emu/info.h

src/emu/inpttype.h

src/emu/machine.c

src/emu/machine.h

src/emu/machine/6522via.c

src/emu/machine/6522via.h

src/emu/machine/6532riot.c

src/emu/machine/6532riot.h

src/emu/machine/68681.c

src/emu/machine/8042kbdc.c

src/emu/machine/ctronics.c

src/emu/machine/generic.c

src/emu/machine/idectrl.c

src/emu/machine/idectrl.h

src/emu/machine/ins8250.c

src/emu/machine/intelfsh.c

src/emu/machine/intelfsh.h

src/emu/machine/ldcore.c

src/emu/machine/ldpr8210.c

src/emu/machine/ldv1000.c

src/emu/machine/ldvp931.c

src/emu/machine/matsucd.c

src/emu/machine/mc146818.c

src/emu/machine/mc68901.c

src/emu/machine/microtch.c

src/emu/machine/pic8259.c

src/emu/machine/roc10937.c

src/emu/machine/wd17xx.c

src/emu/machine/z80dart.c

src/emu/machine/z80dart.h

src/emu/machine/z80dma.c

src/emu/machine/z8536.c

src/emu/machine/z8536.h

src/emu/mconfig.c

src/emu/mconfig.h

src/emu/memory.c

src/emu/memory.h

src/emu/render.c

src/emu/rendfont.c

src/emu/rendlay.c

src/emu/rendlay.h

src/emu/romload.c

src/emu/romload.h

src/emu/screen.h

src/emu/softlist.c

src/emu/softlist.h

src/emu/sound.c

src/emu/sound/asc.c

src/emu/sound/asc.h

src/emu/sound/ay8910.c

src/emu/sound/ay8910.h

src/emu/sound/bsmt2000.c

src/emu/sound/c352.c

src/emu/sound/cdda.c

src/emu/sound/digitalk.c

src/emu/sound/disc_dev.c

src/emu/sound/disc_mth.c

src/emu/sound/disc_wav.c

src/emu/sound/discrete.h

src/emu/sound/es5503.c

src/emu/sound/es5503.h

src/emu/sound/es5506.c

src/emu/sound/es5506.h

src/emu/sound/fm.c

src/emu/sound/fm2612.c

src/emu/sound/fmopl.c

src/emu/sound/k051649.c

src/emu/sound/k051649.h

src/emu/sound/k054539.h

src/emu/sound/mas3507d.h

src/emu/sound/mos6560.c

src/emu/sound/namco.c

src/emu/sound/namco.h

src/emu/sound/okim6376.c

src/emu/sound/okim9810.c

src/emu/sound/s14001a.c

src/emu/sound/scsp.c

src/emu/sound/sound.mak

src/emu/sound/sp0256.c

src/emu/sound/speaker.c

src/emu/sound/spu.c

src/emu/sound/tms5110r.c

src/emu/sound/tms5220.c

src/emu/sound/vlm5030.c

src/emu/sound/ym2413.c

src/emu/sound/ymf262.c

src/emu/sound/ymf271.c

src/emu/sound/ymf278b.c

src/emu/sound/ymz280b.c

src/emu/tilemap.c

src/emu/ui.c

src/emu/uimenu.c

src/emu/uiswlist.c

src/emu/validity.c

src/emu/video.c

src/emu/video.h

src/emu/video/hd61830.c

src/emu/video/hd63484.c

src/emu/video/k053250.c

src/emu/video/mc6845.c

src/emu/video/mc6845.h

src/emu/video/psx.c

src/emu/video/psx.h

src/emu/video/rgbgen.h

src/emu/video/rgbsse.h

src/emu/video/rgbvmx.h

src/emu/video/saa5050.c

src/emu/video/tms9928a.c

src/emu/video/tms9928a.h

src/emu/video/vooddefs.h

src/emu/video/voodoo.c

src/emu/watchdog.c

src/lib/cothread/ppc.c

src/lib/expat/expat.h

src/lib/expat/internal.h

src/lib/formats/ami_dsk.c

src/lib/formats/ami_dsk.h

src/lib/formats/ap2_dsk.c

src/lib/formats/ap2_dsk.h

src/lib/formats/ap_dsk35.c

src/lib/formats/ap_dsk35.h

src/lib/formats/apridisk.c

src/lib/formats/atari_dsk.c

src/lib/formats/atari_dsk.h

src/lib/formats/atarist_dsk.c

src/lib/formats/atarist_dsk.h

src/lib/formats/basicdsk.c

src/lib/formats/basicdsk.h

src/lib/formats/coco_dsk.c

src/lib/formats/coco_dsk.h

src/lib/formats/comx35_dsk.c

src/lib/formats/comx35_dsk.h

src/lib/formats/coupedsk.c

src/lib/formats/coupedsk.h

src/lib/formats/cpis_dsk.c

src/lib/formats/cpis_dsk.h

src/lib/formats/cqm_dsk.c

src/lib/formats/d64_dsk.c

src/lib/formats/d81_dsk.c

src/lib/formats/d88_dsk.c

src/lib/formats/dsk_dsk.c

src/lib/formats/fdi_dsk.c

src/lib/formats/flopimg.c

src/lib/formats/flopimg.h

src/lib/formats/g64_dsk.c

src/lib/formats/hect_dsk.c

src/lib/formats/hect_dsk.h

src/lib/formats/imd_dsk.c

src/lib/formats/msx_dsk.c

src/lib/formats/msx_dsk.h

src/lib/formats/nes_dsk.c

src/lib/formats/nes_dsk.h

src/lib/formats/oric_dsk.c

src/lib/formats/oric_dsk.h

src/lib/formats/oric_tap.c

src/lib/formats/pc_dsk.c

src/lib/formats/pc_dsk.h

src/lib/formats/smx_dsk.c

src/lib/formats/smx_dsk.h

src/lib/formats/sorc_dsk.c

src/lib/formats/sorc_dsk.h

src/lib/formats/svi_dsk.c

src/lib/formats/svi_dsk.h

src/lib/formats/td0_dsk.c

src/lib/formats/thom_cas.c

src/lib/formats/thom_dsk.c

src/lib/formats/thom_dsk.h

src/lib/formats/ti99_dsk.c

src/lib/formats/ti99_dsk.h

src/lib/formats/trd_dsk.c

src/lib/formats/trd_dsk.h

src/lib/formats/trs_dsk.c

src/lib/formats/trs_dsk.h

src/lib/formats/uef_cas.c

src/lib/formats/vt_dsk.c

src/lib/formats/vt_dsk.h

src/lib/formats/vtech1_dsk.c

src/lib/formats/vtech1_dsk.h

src/lib/formats/z80ne_dsk.c

src/lib/formats/z80ne_dsk.h

src/lib/lib.mak

src/lib/softfloat/softfloat-macros

src/lib/softfloat/softfloat-specialize

src/lib/softfloat/softfloat.c

src/lib/softfloat/softfloat.h

src/lib/util/cdrom.c

src/lib/util/cdrom.h

src/lib/util/corefile.c

src/lib/util/corestr.c

src/lib/util/corestr.h

src/lib/util/md5.c

src/lib/util/options.c

src/mame/audio/8080bw.c

src/mame/audio/cps3.c

src/mame/audio/firetrk.c

src/mame/audio/flower.c

src/mame/audio/gottlieb.c

src/mame/audio/m79amb.c

src/mame/audio/mw8080bw.c

src/mame/audio/namco52.c

src/mame/audio/namco54.c

src/mame/audio/qix.c

src/mame/audio/segag80r.c

src/mame/audio/seibu.c

src/mame/audio/sprint2.c

src/mame/audio/taito_en.c

src/mame/audio/taito_zm.c

src/mame/audio/vicdual.c

src/mame/drivers/1942.c

src/mame/drivers/1943.c

src/mame/drivers/20pacgal.c

src/mame/drivers/40love.c

src/mame/drivers/8080bw.c

src/mame/drivers/acefruit.c

src/mame/drivers/acommand.c

src/mame/drivers/adp.c

src/mame/drivers/aerofgt.c

src/mame/drivers/airbustr.c

src/mame/drivers/aleck64.c

src/mame/drivers/alg.c

src/mame/drivers/alien.c

src/mame/drivers/allied.c

src/mame/drivers/alvg.c

src/mame/drivers/ambush.c

src/mame/drivers/ampoker2.c

src/mame/drivers/arcadia.c

src/mame/drivers/argus.c

src/mame/drivers/aristmk4.c

src/mame/drivers/aristmk5.c

src/mame/drivers/arkanoid.c

src/mame/drivers/armedf.c

src/mame/drivers/asteroid.c

src/mame/drivers/asuka.c

src/mame/drivers/atari_s1.c

src/mame/drivers/atari_s2.c

src/mame/drivers/atari_s3.c

src/mame/drivers/atarisy2.c

src/mame/drivers/atvtrack.c

src/mame/drivers/avt.c

src/mame/drivers/badlands.c

src/mame/drivers/bagman.c

src/mame/drivers/balsente.c

src/mame/drivers/berzerk.c

src/mame/drivers/bfcobra.c

src/mame/drivers/bfm_sc1.c

src/mame/drivers/bfm_sc2.c

src/mame/drivers/bfmsys85.c

src/mame/drivers/big10.c

src/mame/drivers/bingo.c

src/mame/drivers/blitz.c

src/mame/drivers/brkthru.c

src/mame/drivers/by17.c

src/mame/drivers/by35.c

src/mame/drivers/by6803.c

src/mame/drivers/by68701.c

src/mame/drivers/byvid.c

src/mame/drivers/cabaret.c

src/mame/drivers/calomega.c

src/mame/drivers/capcom.c

src/mame/drivers/carrera.c

src/mame/drivers/cave.c

src/mame/drivers/cd32.c

src/mame/drivers/chaknpop.c

src/mame/drivers/chihiro.c

src/mame/drivers/chinagat.c

src/mame/drivers/chqflag.c

src/mame/drivers/cliffhgr.c

src/mame/drivers/cmmb.c

src/mame/drivers/cninja.c

src/mame/drivers/coinmstr.c

src/mame/drivers/corona.c

src/mame/drivers/cps1.c

src/mame/drivers/cps2.c

src/mame/drivers/cps3.c

src/mame/drivers/crshrace.c

src/mame/drivers/csplayh5.c

src/mame/drivers/cvs.c

src/mame/drivers/cybertnk.c

src/mame/drivers/dblewing.c

src/mame/drivers/dday.c

src/mame/drivers/ddenlovr.c

src/mame/drivers/de_1.c

src/mame/drivers/de_2.c

src/mame/drivers/de_3.c

src/mame/drivers/de_3b.c

src/mame/drivers/dec0.c

src/mame/drivers/deco32.c

src/mame/drivers/decocass.c

src/mame/drivers/destroyr.c

src/mame/drivers/dkong.c

src/mame/drivers/drgnmst.c

src/mame/drivers/drmicro.c

src/mame/drivers/drtomy.c

src/mame/drivers/dwarfd.c

src/mame/drivers/dynax.c

src/mame/drivers/eolith.c

src/mame/drivers/eolithsp.c

src/mame/drivers/esd16.c

src/mame/drivers/exerion.c

src/mame/drivers/exprraid.c

src/mame/drivers/f1gp.c

src/mame/drivers/famibox.c

src/mame/drivers/firetrap.c

src/mame/drivers/flicker.c

src/mame/drivers/flkatck.c

src/mame/drivers/flower.c

src/mame/drivers/flyball.c

src/mame/drivers/forte2.c

src/mame/drivers/freekick.c

src/mame/drivers/funkybee.c

src/mame/drivers/funkyjet.c

src/mame/drivers/funworld.c

src/mame/drivers/fuukifg2.c

src/mame/drivers/fuukifg3.c

src/mame/drivers/g627.c

src/mame/drivers/gaelco.c

src/mame/drivers/gaiden.c

src/mame/drivers/gal3.c

src/mame/drivers/galaga.c

src/mame/drivers/galaxold.c

src/mame/drivers/galdrvr.c

src/mame/drivers/galivan.c

src/mame/drivers/galpanic.c

src/mame/drivers/galspnbl.c

src/mame/drivers/gei.c

src/mame/drivers/goldnpkr.c

src/mame/drivers/goldstar.c

src/mame/drivers/gottlieb.c

src/mame/drivers/gp_1.c

src/mame/drivers/gp_2.c

src/mame/drivers/gts1.c

src/mame/drivers/gts3.c

src/mame/drivers/gts80.c

src/mame/drivers/gts80a.c

src/mame/drivers/gts80b.c

src/mame/drivers/gunbustr.c

src/mame/drivers/hankin.c

src/mame/drivers/hcastle.c

src/mame/drivers/hexion.c

src/mame/drivers/higemaru.c

src/mame/drivers/hikaru.c

src/mame/drivers/hitme.c

src/mame/drivers/hitpoker.c

src/mame/drivers/hornet.c

src/mame/drivers/icecold.c

src/mame/drivers/igs017.c

src/mame/drivers/imolagp.c

src/mame/drivers/inder.c

src/mame/drivers/itech32.c

src/mame/drivers/jack.c

src/mame/drivers/jalmah.c

src/mame/drivers/jp.c

src/mame/drivers/jpmimpct.c

src/mame/drivers/jpmsys5.c

src/mame/drivers/junofrst.c

src/mame/drivers/jvh.c

src/mame/drivers/kaneko16.c

src/mame/drivers/karnov.c

src/mame/drivers/kingdrby.c

src/mame/drivers/kingpin.c

src/mame/drivers/kissproto.c

src/mame/drivers/konamigq.c

src/mame/drivers/konamigv.c

src/mame/drivers/konamigx.c

src/mame/drivers/kongambl.c

src/mame/drivers/ksys573.c

src/mame/drivers/ladybug.c

src/mame/drivers/laserbas.c

src/mame/drivers/laserbat.c

src/mame/drivers/lastduel.c

src/mame/drivers/leland.c

src/mame/drivers/lethal.c

src/mame/drivers/lordgun.c

src/mame/drivers/ltd.c

src/mame/drivers/lucky74.c

src/mame/drivers/m72.c

src/mame/drivers/m90.c

src/mame/drivers/m92.c

src/mame/drivers/magic10.c

src/mame/drivers/magicard.c

src/mame/drivers/magicfly.c

src/mame/drivers/magictg.c

src/mame/drivers/maxaflex.c

src/mame/drivers/maygay1b.c

src/mame/drivers/maygayv1.c

src/mame/drivers/mcatadv.c

src/mame/drivers/megadrvb.c

src/mame/drivers/megaplay.c

src/mame/drivers/megasys1.c

src/mame/drivers/mephisto.c

src/mame/drivers/merit.c

src/mame/drivers/meritm.c

src/mame/drivers/metro.c

src/mame/drivers/micropin.c

src/mame/drivers/midtunit.c

src/mame/drivers/midyunit.c

src/mame/drivers/midzeus.c

src/mame/drivers/mil4000.c

src/mame/drivers/minivadr.c

src/mame/drivers/missile.c

src/mame/drivers/mjkjidai.c

src/mame/drivers/model1.c

src/mame/drivers/model2.c

src/mame/drivers/model3.c

src/mame/drivers/mosaic.c

src/mame/drivers/mpu3.c

src/mame/drivers/mpu4.c

src/mame/drivers/mpu5.c

src/mame/drivers/mquake.c

src/mame/drivers/mrdo.c

src/mame/drivers/mrflea.c

src/mame/drivers/mrgame.c

src/mame/drivers/ms32.c

src/mame/drivers/multfish.c

src/mame/drivers/multigam.c

src/mame/drivers/murogem.c

src/mame/drivers/mw8080bw.c

src/mame/drivers/namcofl.c

src/mame/drivers/namcona1.c

src/mame/drivers/namconb1.c

src/mame/drivers/namcond1.c

src/mame/drivers/namcos10.c

src/mame/drivers/namcos11.c

src/mame/drivers/namcos12.c

src/mame/drivers/namcos21.c

src/mame/drivers/namcos22.c

src/mame/drivers/namcos23.c

src/mame/drivers/naomi.c

src/mame/drivers/nemesis.c

src/mame/drivers/neodrvr.c

src/mame/drivers/neogeo.c

src/mame/drivers/neoprint.c

src/mame/drivers/nightgal.c

src/mame/drivers/ninjakd2.c

src/mame/drivers/ninjaw.c

src/mame/drivers/nmg5.c

src/mame/drivers/nmk16.c

src/mame/drivers/nova2001.c

src/mame/drivers/nsm.c

src/mame/drivers/nsmpoker.c

src/mame/drivers/nwk-tr.c

src/mame/drivers/olibochu.c

src/mame/drivers/oneshot.c

src/mame/drivers/opwolf.c

src/mame/drivers/pachifev.c

src/mame/drivers/pacman.c

src/mame/drivers/panicr.c

src/mame/drivers/paradise.c

src/mame/drivers/pbaction.c

src/mame/drivers/pcktgal.c

src/mame/drivers/pcxt.c

src/mame/drivers/pengadvb.c

src/mame/drivers/peyper.c

src/mame/drivers/pgm.c

src/mame/drivers/phoenix.c

src/mame/drivers/pipedrm.c

src/mame/drivers/pktgaldx.c

src/mame/drivers/play_1.c

src/mame/drivers/play_2.c

src/mame/drivers/play_3.c

src/mame/drivers/play_5.c

src/mame/drivers/polepos.c

src/mame/drivers/poo.c

src/mame/drivers/pooyan.c

src/mame/drivers/progolf.c

src/mame/drivers/psikyo.c

src/mame/drivers/psikyo4.c

src/mame/drivers/psikyosh.c

src/mame/drivers/psychic5.c

src/mame/drivers/pturn.c

src/mame/drivers/quasar.c

src/mame/drivers/quizpun2.c

src/mame/drivers/rabbit.c

src/mame/drivers/raiden.c

src/mame/drivers/raiden2.c

src/mame/drivers/rainbow.c

src/mame/drivers/rallyx.c

src/mame/drivers/rastan.c

src/mame/drivers/re900.c

src/mame/drivers/renegade.c

src/mame/drivers/rockrage.c

src/mame/drivers/rowamet.c

src/mame/drivers/s11.c

src/mame/drivers/s11a.c

src/mame/drivers/s11b.c

src/mame/drivers/s11c.c

src/mame/drivers/s3.c

src/mame/drivers/s4.c

src/mame/drivers/s6.c

src/mame/drivers/s6a.c

src/mame/drivers/s7.c

src/mame/drivers/s8.c

src/mame/drivers/s9.c

src/mame/drivers/saturn.c

src/mame/drivers/sauro.c

src/mame/drivers/sbugger.c

src/mame/drivers/scobra.c

src/mame/drivers/sderby.c

src/mame/drivers/segac2.c

src/mame/drivers/segae.c

src/mame/drivers/segag80r.c

src/mame/drivers/segag80v.c

src/mame/drivers/segahang.c

src/mame/drivers/segald.c

src/mame/drivers/segaorun.c

src/mame/drivers/segas16a.c

src/mame/drivers/segas16b.c

src/mame/drivers/segas18.c

src/mame/drivers/segas24.c

src/mame/drivers/segas32.c

src/mame/drivers/segaxbd.c

src/mame/drivers/segaybd.c

src/mame/drivers/seibuspi.c

src/mame/drivers/seta.c

src/mame/drivers/seta2.c

src/mame/drivers/sfbonus.c

src/mame/drivers/sg1000a.c

src/mame/drivers/shadfrce.c

src/mame/drivers/sigmab98.c

src/mame/drivers/skeetsht.c

src/mame/drivers/slapfght.c

src/mame/drivers/slapshot.c

src/mame/drivers/sleic.c

src/mame/drivers/sms.c

src/mame/drivers/snk.c

src/mame/drivers/snk6502.c

src/mame/drivers/snk68.c

src/mame/drivers/sothello.c

src/mame/drivers/spcforce.c

src/mame/drivers/speedspn.c

src/mame/drivers/speglsht.c

src/mame/drivers/spinb.c

src/mame/drivers/srmp6.c

src/mame/drivers/ssfindo.c

src/mame/drivers/sshangha.c

src/mame/drivers/ssv.c

src/mame/drivers/st_mp100.c

src/mame/drivers/st_mp200.c

src/mame/drivers/stepstag.c

src/mame/drivers/sub.c

src/mame/drivers/subs.c

src/mame/drivers/superqix.c

src/mame/drivers/suprnova.c

src/mame/drivers/system1.c

src/mame/drivers/tagteam.c

src/mame/drivers/taito.c

src/mame/drivers/taito_b.c

src/mame/drivers/taito_f2.c

src/mame/drivers/taito_f3.c

src/mame/drivers/taito_h.c

src/mame/drivers/taito_l.c

src/mame/drivers/taito_x.c

src/mame/drivers/taito_z.c

src/mame/drivers/taitoair.c

src/mame/drivers/taitogn.c

src/mame/drivers/taitojc.c

src/mame/drivers/taitopjc.c

src/mame/drivers/taitosj.c

src/mame/drivers/taitotz.c

src/mame/drivers/tankbatt.c

src/mame/drivers/taotaido.c

src/mame/drivers/tatsumi.c

src/mame/drivers/tbowl.c

src/mame/drivers/techno.c

src/mame/drivers/tecmo.c

src/mame/drivers/tecmosys.c

src/mame/drivers/tempest.c

src/mame/drivers/tetrisp2.c

src/mame/drivers/tigeroad.c

src/mame/drivers/tmmjprd.c

src/mame/drivers/tmnt.c

src/mame/drivers/tnzs.c

src/mame/drivers/toaplan1.c

src/mame/drivers/toaplan2.c

src/mame/drivers/topspeed.c

src/mame/drivers/toypop.c

src/mame/drivers/triforce.c

src/mame/drivers/trvquest.c

src/mame/drivers/tumbleb.c

src/mame/drivers/tunhunt.c

src/mame/drivers/twin16.c

src/mame/drivers/twincobr.c

src/mame/drivers/twinkle.c

src/mame/drivers/undrfire.c

src/mame/drivers/upscope.c

src/mame/drivers/vamphalf.c

src/mame/drivers/vball.c

src/mame/drivers/vd.c

src/mame/drivers/vicdual.c

src/mame/drivers/videopkr.c

src/mame/drivers/vigilant.c

src/mame/drivers/viper.c

src/mame/drivers/vpoker.c

src/mame/drivers/vulgus.c

src/mame/drivers/wallc.c

src/mame/drivers/wardner.c

src/mame/drivers/warpwarp.c

src/mame/drivers/warriorb.c

src/mame/drivers/white_mod.c

src/mame/drivers/whitestar.c

src/mame/drivers/wico.c

src/mame/drivers/williams.c

src/mame/drivers/wiz.c

src/mame/drivers/wpc_95.c

src/mame/drivers/wpc_an.c

src/mame/drivers/wpc_dcs.c

src/mame/drivers/wpc_dot.c

src/mame/drivers/wpc_flip1.c

src/mame/drivers/wpc_flip2.c

src/mame/drivers/wpc_s.c

src/mame/drivers/wwfsstar.c

src/mame/drivers/wwfwfest.c

src/mame/drivers/xmen.c

src/mame/drivers/xorworld.c

src/mame/drivers/xxmissio.c

src/mame/drivers/yunsun16.c

src/mame/drivers/zac_1.c

src/mame/drivers/zac_2.c

src/mame/drivers/zac_proto.c

src/mame/drivers/zaxxon.c

src/mame/drivers/zn.c

src/mame/drivers/zodiack.c

src/mame/etc/jrcrypt.c

src/mame/includes/airbustr.h

src/mame/includes/amiga.h

src/mame/includes/archimds.h

src/mame/includes/dc.h

src/mame/includes/deco32.h

src/mame/includes/flower.h

src/mame/includes/goldstar.h

src/mame/includes/m72.h

src/mame/includes/m92.h

src/mame/includes/megasys1.h

src/mame/includes/model3.h

src/mame/includes/mw8080bw.h

src/mame/includes/namcos22.h

src/mame/includes/naomi.h

src/mame/includes/neogeo.h

src/mame/includes/paradise.h

src/mame/includes/pgm.h

src/mame/includes/psikyo4.h

src/mame/includes/psikyosh.h

src/mame/includes/psx.h

src/mame/includes/segas24.h

src/mame/includes/stv.h

src/mame/includes/superqix.h

src/mame/includes/suprnova.h

src/mame/includes/tagteam.h

src/mame/includes/taito_b.h

src/mame/includes/taitoair.h

src/mame/includes/taitojc.h

src/mame/includes/tecmosys.h

src/mame/includes/tetrisp2.h

src/mame/includes/toaplipt.h

src/mame/includes/williams.h

src/mame/includes/xmen.h

src/mame/machine/amiga.c

src/mame/machine/archimds.c

src/mame/machine/arkanoid.c

src/mame/machine/cd32.c

src/mame/machine/cdi070.c

src/mame/machine/dc.c

src/mame/machine/fddebug.c

src/mame/machine/kaneko16.c

src/mame/machine/maple-dc.c

src/mame/machine/maple-dc.h

src/mame/machine/md_cart.c

src/mame/machine/megadriv.c

src/mame/machine/mie.c

src/mame/machine/mie.h

src/mame/machine/n64.c

src/mame/machine/namco50.c

src/mame/machine/namco51.c

src/mame/machine/namco53.c

src/mame/machine/namco62.c

src/mame/machine/namcos1.c

src/mame/machine/namcos2.c

src/mame/machine/naomi.c

src/mame/machine/naomibd.c

src/mame/machine/neocrypt.c

src/mame/machine/pgmprot.c

src/mame/machine/psx.c

src/mame/machine/s16fd.c

src/mame/machine/scudsp.c

src/mame/machine/scudsp.h

src/mame/machine/seicop.c

src/mame/machine/snes.c

src/mame/machine/steppers.c

src/mame/machine/stvcd.c

src/mame/machine/stvcd.h

src/mame/machine/vectrex.c

src/mame/machine/williams.c

src/mame/mame.lst

src/mame/mame.mak

src/mame/video/1943.c

src/mame/video/archimds.c

src/mame/video/argus.c

src/mame/video/asterix.c

src/mame/video/centiped.c

src/mame/video/cninja.c

src/mame/video/dc.c

src/mame/video/deckarn.c

src/mame/video/deco16ic.c

src/mame/video/deco16ic.h

src/mame/video/deco32.c

src/mame/video/eolith.c

src/mame/video/flower.c

src/mame/video/funworld.c

src/mame/video/glass.c

src/mame/video/goldstar.c

src/mame/video/gridlee.c

src/mame/video/hng64.c

src/mame/video/konicdev.c

src/mame/video/konicdev.h

src/mame/video/lethal.c

src/mame/video/m62.c

src/mame/video/m72.c

src/mame/video/m92.c

src/mame/video/model2.c

src/mame/video/mystston.c

src/mame/video/namcos22.c

src/mame/video/nemesis.c

src/mame/video/ninjakd2.c

src/mame/video/nmk16.c

src/mame/video/paradise.c

src/mame/video/phoenix.c

src/mame/video/psikyo4.c

src/mame/video/psikyosh.c

src/mame/video/rohga.c

src/mame/video/segaic24.c

src/mame/video/seta2.c

src/mame/video/sknsspr.c

src/mame/video/speedspn.c

src/mame/video/stvvdp1.c

src/mame/video/stvvdp2.c

src/mame/video/superqix.c

src/mame/video/tagteam.c

src/mame/video/taito_b.c

src/mame/video/taitoair.c

src/mame/video/taitoic.c

src/mame/video/taitojc.c

src/mame/video/taitosj.c

src/mame/video/tia.c

src/mame/video/toypop.c

src/mame/video/warpwarp.c

src/mame/video/wgp.c

src/mame/video/williams.c

src/mame/video/xmen.c

src/mame/video/ygv608.c

src/mame/video/zac2650.c

src/osd/osdcomm.h

src/osd/sdl/sdl.mak

src/osd/sdl/sdlmain.c

src/osd/sdl/sdlos_os2.c

src/osd/sdl/sdlsync_ntc.c

src/osd/sdl/sdlwork.c

src/osd/sdl/watchdog.c

src/osd/windows/d3dcomm.h

src/osd/windows/d3dhlsl.c

src/osd/windows/d3dhlsl.h

src/osd/windows/debugwin.c

src/osd/windows/drawd3d.c

src/osd/windows/input.c

src/osd/windows/output.c

src/osd/windows/vconv.c

src/osd/windows/video.c

src/osd/windows/winclip.c

src/osd/windows/window.c

src/osd/windows/windows.mak

src/osd/windows/winfile.c

src/osd/windows/winmain.c

src/osd/windows/winmain.h

src/osd/windows/winwork.c

src/tools/chdman.c

src/tools/regrep.c

src/tools/split.c

src/tools/src2html.c

src/tools/tools.mak

src/tools/unidasm.c

src/version.c

whatsnew.txt

Show diffs side-by-side

added added

removed removed

src/emu/cpu/h83002/h8speriph.c

Hitachi H8S/2xxx MCU peripherals

H8S/2241

H8S/2246

H8S/2323

#include "emu.h"

#include "debugger.h"

#include "h8.h"

#include "h8priv.h"

#define VERBOSE_LEVEL ( 0 )

INLINE void ATTR_PRINTF(3,4) verboselog( running_machine &machine, int n_level, const char *s_fmt, ...)

{

if (VERBOSE_LEVEL >= n_level)

{

va_list v;

char buf[32768];

va_start( v, s_fmt);

vsprintf( buf, s_fmt, v);

va_end( v);

logerror( "%s: %s", machine.describe_context( ), buf);

}

const UINT8 H8S_RESET_H8S_IO_224x[0x1C0] = // values from "e602100_h8s2245.pdf"

{

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FE40

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FE50

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FE60

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FE70

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FE80

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FE90

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FEA0

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, // FEB0

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FEC0

0xFF, 0xFF, 0xFF, 0xFF, 0xD0, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FED0

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FEE0

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FEF0

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FF00

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FF10

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FF20

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01, 0x00, 0x00, 0x3F, 0xFF, 0x00, 0x00, // FF30

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FF40

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FF50

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FF60

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x84, 0x00, 0xF2, 0x00, // FF70

0x00, 0xFF, 0x00, 0xFF, 0x84, 0x00, 0xF2, 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x84, 0x00, 0xF2, 0x00, // FF80

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FF90

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FFA0

0x00, 0x00, 0x00, 0x10, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FFB0

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FFC0

0x00, 0xC0, 0x00, 0x00, 0x40, 0xC0, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, // FFD0

0x00, 0xC0, 0x00, 0x00, 0x40, 0xC0, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, // FFE0

0x00, 0xC0, 0x00, 0x00, 0x40, 0xC0, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, // FFF0

};

const UINT8 H8S_RESET_H8S_IO_2323[0x1C0] = // values from "rej09b0220_h8s2329.pdf"

{

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FE40

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FE50

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FE60

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FE70

0x00, 0xC0, 0x00, 0x00, 0x40, 0xC0, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, // FE80

0x00, 0xC0, 0x00, 0x00, 0x40, 0xC0, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, // FE90

0x00, 0xC0, 0x00, 0x00, 0x40, 0xC0, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, // FEA0

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, // FEB0

0x00, 0x00, 0x00, 0x00, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x00, // FEC0

0xFF, 0xFF, 0xFF, 0xFF, 0xD0, 0x3C, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FED0

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FEE0

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FEF0

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FF00

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FF10

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FF20

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01, 0x00, 0x00, 0x3F, 0xFF, 0x00, 0x00, // FF30

0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0xFF, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FF40

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FF50

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FF60

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x84, 0x00, 0xF2, 0x00, // FF70

0x00, 0xFF, 0x00, 0xFF, 0x84, 0x00, 0xF2, 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x84, 0x00, 0xF2, 0x00, // FF80

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FF90

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, // FFA0

0x00, 0x00, 0x00, 0x10, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FFB0

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // FFC0

0x00, 0xC0, 0x00, 0x00, 0x40, 0xC0, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, // FFD0

0x00, 0xC0, 0x00, 0x00, 0x40, 0xC0, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, // FFE0

0x00, 0xC0, 0x00, 0x00, 0x40, 0xC0, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, // FFF0

};

#define SCR_TIE 0x80

#define SCR_RIE 0x40

#define SCR_TE 0x20

100

#define SCR_RE 0x10

101

102

#define SSR_TDRE 0x80

103

#define SSR_RDRF 0x40

104

#define SSR_ORER 0x20

105

#define SSR_FER 0x10

106

#define SSR_PER 0x08

107

#define SSR_TEND 0x04

108

109

#define SMR_CM 0x80

110

#define SMR_CHR 0x40

111

#define SMR_PE 0x20

112

#define SMR_PM 0x10

113

#define SMR_STOP 0x08

114

#define SMR_MP 0x04

115

#define SMR_CKS1 0x02

116

#define SMR_CKS0 0x01

117

118

#define TCSR_CMFB 0x80

119

#define TCSR_CMFA 0x40

120

#define TCSR_OVF 0x20

121

122

#define TCR_CMIEB 0x80

123

#define TCR_CMIEA 0x40

124

#define TCR_OVIE 0x20

125

126

#define TSR_TCFD 0x80

127

#define TSR_TCFU 0x20

128

#define TSR_TCFV 0x10

129

#define TSR_TGFD 0x08

130

#define TSR_TGFC 0x04

131

#define TSR_TGFB 0x02

132

#define TSR_TGFA 0x01

133

134

#define TIER_TCIEU 0x20

135

#define TIER_TCIEV 0x10

136

#define TIER_TGIED 0x08

137

#define TIER_TGIEC 0x04

138

#define TIER_TGIEB 0x02

139

#define TIER_TGIEA 0x01

140

141

#define DTC_MRA_MD_NORMAL 0

142

#define DTC_MRA_MD_REPEAT 1

143

#define DTC_MRA_MD_BLOCK 2

144

145

#define DTC_MRA_SM1 0x80

146

#define DTC_MRA_SM0 0x40

147

#define DTC_MRA_DM1 0x20

148

#define DTC_MRA_DM0 0x10

149

#define DTC_MRA_DTS 0x02

150

151

#define DTC_MRB_CHNE 0x80

152

#define DTC_MRB_DISEL 0x40

153

#define DTC_MRB_CHNS 0x20

154

155

#define DMABCRL_DTME1 0x80

156

#define DMABCRL_DTE1 0x40

157

#define DMABCRL_DTME0 0x20

158

#define DMABCRL_DTE0 0x10

159

#define DMABCRL_DTIE1B 0x08

160

#define DMABCRL_DTIE1A 0x04

161

#define DMABCRL_DTIE0B 0x02

162

#define DMABCRL_DTIE0A 0x01

163

164

#define ADCSR_ADF 0x80

165

#define ADCSR_ADIE 0x40

166

#define ADCSR_ADST 0x20

167

#define ADCSR_SCAN 0x10

168

169

enum

170

{

171

PIN_P10, PIN_P11, PIN_P12, PIN_P13, PIN_P14, PIN_P15, PIN_P16, PIN_P17,

172

PIN_P20, PIN_P21, PIN_P22, PIN_P23, PIN_P24, PIN_P25, PIN_P26, PIN_P27,

173

PIN_P30, PIN_P31, PIN_P32, PIN_P33, PIN_P34, PIN_P35,

174

PIN_P40, PIN_P41, PIN_P42, PIN_P43, PIN_P44, PIN_P45, PIN_P46, PIN_P47,

175

PIN_P50, PIN_P51, PIN_P52, PIN_P53,

176

PIN_P60, PIN_P61, PIN_P62, PIN_P63, PIN_P64, PIN_P65, PIN_P66, PIN_P67,

177

PIN_PA0, PIN_PA1, PIN_PA2, PIN_PA3, PIN_PA4, PIN_PA5, PIN_PA6, PIN_PA7,

178

PIN_PB0, PIN_PB1, PIN_PB2, PIN_PB3, PIN_PB4, PIN_PB5, PIN_PB6, PIN_PB7,

179

PIN_PC0, PIN_PC1, PIN_PC2, PIN_PC3, PIN_PC4, PIN_PC5, PIN_PC6, PIN_PC7,

180

PIN_PD0, PIN_PD1, PIN_PD2, PIN_PD3, PIN_PD4, PIN_PD5, PIN_PD6, PIN_PD7,

181

PIN_PE0, PIN_PE1, PIN_PE2, PIN_PE3, PIN_PE4, PIN_PE5, PIN_PE6, PIN_PE7,

182

PIN_PF0, PIN_PF1, PIN_PF2, PIN_PF3, PIN_PF4, PIN_PF5, PIN_PF6, PIN_PF7,

183

PIN_PG0, PIN_PG1, PIN_PG2, PIN_PG3, PIN_PG4

184

};

185

186

#define PIN_TIOCA0 PIN_P10

187

#define PIN_TIOCB0 PIN_P11

188

#define PIN_TIOCC0 PIN_P12

189

#define PIN_TIOCD0 PIN_P13

190

#define PIN_TIOCA1 PIN_P14

191

#define PIN_TIOCB1 PIN_P15

192

#define PIN_TIOCA2 PIN_P16

193

#define PIN_TIOCB2 PIN_P17

194

195

#define PIN_TCLKA PIN_P12

196

#define PIN_TCLKB PIN_P13

197

#define PIN_TCLKC PIN_P15

198

#define PIN_TCLKD PIN_P17

199

200

#define PIN_TXD0 PIN_P30

201

#define PIN_TXD1 PIN_P31

202

#define PIN_RXD0 PIN_P32

203

#define PIN_RXD1 PIN_P33

204

#define PIN_SCK0 PIN_P34

205

#define PIN_SCK1 PIN_P35

206

207

#define PIN_TIOCA3 PIN_P20

208

#define PIN_TIOCB3 PIN_P21

209

#define PIN_TIOCC3 PIN_P22

210

#define PIN_TIOCD3 PIN_P23

211

#define PIN_TIOCA4 PIN_P24

212

#define PIN_TIOCB4 PIN_P25

213

#define PIN_TIOCA5 PIN_P26

214

#define PIN_TIOCB5 PIN_P27

215

216

#define PIN_TMRI0 PIN_P22

217

#define PIN_TMCI0 PIN_P23

218

#define PIN_TMRI1 PIN_P24

219

#define PIN_TMCI1 PIN_P25

220

#define PIN_TMO0 PIN_P26

221

#define PIN_TMO1 PIN_P27

222

223

const int TPU_0_DIV[] = { 1, 4, 16, 64, 0, 0, 0,0 };

224

const int TPU_1_DIV[] = { 1, 4, 16, 64, 0, 0, 256, 0 };

225

const int TPU_2_DIV[] = { 1, 4, 16, 64, 0, 0, 0, 1024 };

226

const int TPU_3_DIV[] = { 1, 4, 16, 64, 0, 1024, 256, 4096 };

227

const int TPU_4_DIV[] = { 1, 4, 16, 64, 0, 0, 1024, 0 };

228

const int TPU_5_DIV[] = { 1, 4, 16, 64, 0, 0, 256, 0 };

229

230

const int H8S_IO_SMR[] = { H8S_IO_SMR0, H8S_IO_SMR1, H8S_IO_SMR2 };

231

const int H8S_IO_BRR[] = { H8S_IO_BRR0, H8S_IO_BRR1, H8S_IO_BRR2 };

232

const int H8S_IO_SCR[] = { H8S_IO_SCR0, H8S_IO_SCR1, H8S_IO_SCR2 };

233

const int H8S_IO_TDR[] = { H8S_IO_TDR0, H8S_IO_TDR1, H8S_IO_TDR2 };

234

const int H8S_IO_SSR[] = { H8S_IO_SSR0, H8S_IO_SSR1, H8S_IO_SSR2 };

235

const int H8S_IO_RDR[] = { H8S_IO_RDR0, H8S_IO_RDR1, H8S_IO_RDR2 };

236

237

const int H8S_INT_TXI[] = { H8S_INT_TXI0, H8S_INT_TXI1, H8S_INT_TXI2 };

238

const int H8S_INT_RXI[] = { H8S_INT_RXI0, H8S_INT_RXI1, H8S_INT_RXI2 };

239

240

const int H8S_IO_TCORA[] = { H8S_IO_TCORA0, H8S_IO_TCORA1 };

241

const int H8S_IO_TCORB[] = { H8S_IO_TCORB0, H8S_IO_TCORB1 };

242

const int H8S_IO_TCR[] = { H8S_IO_TCR0, H8S_IO_TCR1 };

243

const int H8S_IO_TCNT[] = { H8S_IO_TCNT0, H8S_IO_TCNT1 };

244

const int H8S_IO_TCSR[] = { H8S_IO_TCSR0, H8S_IO_TCSR1 };

245

246

const int H8S_INT_OVI[] = { H8S_INT_OVI0, H8S_INT_OVI1 };

247

const int H8S_INT_CMIA[] = { H8S_INT_CMIA0, H8S_INT_CMIA1 };

248

const int H8S_INT_CMIB[] = { H8S_INT_CMIB0, H8S_INT_CMIB1 };

249

250

const int H8S_IO_TGRA_H[] = { H8S_IO_TGR0A_H, H8S_IO_TGR1A_H, H8S_IO_TGR2A_H, H8S_IO_TGR3A_H, H8S_IO_TGR4A_H, H8S_IO_TGR5A_H };

251

const int H8S_IO_TGRA_L[] = { H8S_IO_TGR0A_L, H8S_IO_TGR1A_L, H8S_IO_TGR2A_L, H8S_IO_TGR3A_L, H8S_IO_TGR4A_L, H8S_IO_TGR5A_L };

252

const int H8S_IO_TGRB_H[] = { H8S_IO_TGR0B_H, H8S_IO_TGR1B_H, H8S_IO_TGR2B_H, H8S_IO_TGR3B_H, H8S_IO_TGR4B_H, H8S_IO_TGR5B_H };

253

const int H8S_IO_TGRB_L[] = { H8S_IO_TGR0B_L, H8S_IO_TGR1B_L, H8S_IO_TGR2B_L, H8S_IO_TGR3B_L, H8S_IO_TGR4B_L, H8S_IO_TGR5B_L };

254

const int H8S_IO_TGRC_H[] = { H8S_IO_TGR0C_H, 0, 0, H8S_IO_TGR3C_H, 0, 0 };

255

const int H8S_IO_TGRC_L[] = { H8S_IO_TGR0C_L, 0, 0, H8S_IO_TGR3C_L, 0, 0 };

256

const int H8S_IO_TGRD_H[] = { H8S_IO_TGR0D_H, 0, 0, H8S_IO_TGR3D_H, 0, 0 };

257

const int H8S_IO_TGRD_L[] = { H8S_IO_TGR0D_L, 0, 0, H8S_IO_TGR3D_L, 0, 0 };

258

const int H8S_IO_TCNT_H[] = { H8S_IO_TCNT0_H, H8S_IO_TCNT1_H, H8S_IO_TCNT2_H, H8S_IO_TCNT3_H, H8S_IO_TCNT4_H, H8S_IO_TCNT5_H };

259

const int H8S_IO_TCNT_L[] = { H8S_IO_TCNT0_L, H8S_IO_TCNT1_L, H8S_IO_TCNT2_L, H8S_IO_TCNT3_L, H8S_IO_TCNT4_L, H8S_IO_TCNT5_L };

260

const int H8S_IO_TIOR_H[] = { H8S_IO_TIOR0_H, H8S_IO_TIOR1, H8S_IO_TIOR2, H8S_IO_TIOR3_H, H8S_IO_TIOR4, H8S_IO_TIOR5 };

261

const int H8S_IO_TIOR_L[] = { H8S_IO_TIOR0_L, 0, 0, H8S_IO_TIOR3_L, 0, 0 };

262

const int H8S_IO_TTCR[] = { H8S_IO_TTCR0, H8S_IO_TTCR1, H8S_IO_TTCR2, H8S_IO_TTCR3, H8S_IO_TTCR4, H8S_IO_TTCR5 };

263

const int H8S_IO_TIER[] = { H8S_IO_TIER0, H8S_IO_TIER1, H8S_IO_TIER2, H8S_IO_TIER3, H8S_IO_TIER4, H8S_IO_TIER5 };

264

const int H8S_IO_TSR[] = { H8S_IO_TSR0, H8S_IO_TSR1, H8S_IO_TSR2, H8S_IO_TSR3, H8S_IO_TSR4, H8S_IO_TSR5 };

265

266

const int H8S_INT_TCIV[] = { H8S_INT_TCI0V, H8S_INT_TCI1V, H8S_INT_TCI2V, H8S_INT_TCI3V, H8S_INT_TCI4V, H8S_INT_TCI5V };

267

const int H8S_INT_TCIU[] = { 0, H8S_INT_TCI1U, H8S_INT_TCI2U, 0, H8S_INT_TCI4U, H8S_INT_TCI5U };

268

const int H8S_INT_TGIA[] = { H8S_INT_TGI0A, H8S_INT_TGI1A, H8S_INT_TGI2A, H8S_INT_TGI3A, H8S_INT_TGI4A, H8S_INT_TGI5A };

269

const int H8S_INT_TGIB[] = { H8S_INT_TGI0B, H8S_INT_TGI1B, H8S_INT_TGI2B, H8S_INT_TGI3B, H8S_INT_TGI4B, H8S_INT_TGI5B };

270

const int H8S_INT_TGIC[] = { H8S_INT_TGI0C, 0, 0, H8S_INT_TGI3C, 0, 0 };

271

const int H8S_INT_TGID[] = { H8S_INT_TGI0D, 0, 0, H8S_INT_TGI3D, 0, 0 };

272

273

const int PIN_TIOCA[] = { PIN_TIOCA0, PIN_TIOCA1, PIN_TIOCA2, PIN_TIOCA3, PIN_TIOCA4, PIN_TIOCA5 };

274

const int PIN_TIOCB[] = { PIN_TIOCB0, PIN_TIOCB1, PIN_TIOCB2, PIN_TIOCB3, PIN_TIOCB4, PIN_TIOCB5 };

275

const int PIN_TIOCC[] = { PIN_TIOCC0, 0, 0, PIN_TIOCC3, 0, 0 };

276

const int PIN_TIOCD[] = { PIN_TIOCD0, 0, 0, PIN_TIOCD3, 0, 0 };

277

278

const int TCR_CCLR_AND[] = { 7, 3, 3, 7, 3, 3 };

279

280

// prototypes

281

282

void h8s_tmr_x_reset( h83xx_state *h8, int x);

283

void h8s_tpu_x_reset( h83xx_state *h8, int x);

284

void h8s_tpu_x_tick( h83xx_state *h8, int x);

285

286

////////////

287

// DTVECR //

288

////////////

289

290

#define DTVECR_ADDR(x) (0x400 + (x << 1))

291

292

///////////////

293

// MEMCONV.H //

294

///////////////

295

296

static TIMER_CALLBACK( h8s_tmr_callback );

297

static TIMER_CALLBACK( h8s_tpu_callback );

298

static TIMER_CALLBACK( h8s_sci_callback );

299

300

/////////////

301

// TIMER.C //

302

/////////////

303

304

UINT16 ptr_read_16( void *ptr)

305

{

306

return (*(((UINT8*)ptr) + 0) << 8) | (*(((UINT8*)ptr) + 1) << 0);

307

}

308

309

void ptr_write_16( void *ptr, UINT16 data)

310

{

311

*(((UINT8*)ptr) + 0) = (data >> 8) & 0xFF;

312

*(((UINT8*)ptr) + 1) = (data >> 0) & 0xFF;

313

}

314

315

int device_icount_min_timer_icount1( h83xx_state *h8, emu_timer *timer)

316

{

317

return (timer->elapsed() * h8->device->unscaled_clock()).as_double();

318

}

319

320

void h8s2xxx_interrupt_request(h83xx_state *h8, UINT32 vecnum)

321

{

322

UINT8 idx, bit;

323

idx = vecnum >> 5;

324

bit = vecnum & 0x1F;

325

h8->irq_req[idx] |= (1 << bit);

326

}

327

328

void h8s_dtce_execute(h83xx_state *h8, UINT32 addr_dtce, UINT8 mask_dtce, UINT32 addr_dtvecr)

329

{

330

UINT32 data[3], dtc_vect, dtc_sar, dtc_dar, cnt, i;

331

UINT8 dtc_mra, dtc_mrb, sz;

332

UINT16 dtc_cra, dtc_crb;

333

// get dtc info

334

dtc_vect = 0xFF0000 | h8->program->read_word(addr_dtvecr);

335

data[0] = h8->program->read_dword( dtc_vect + 0);

336

data[1] = h8->program->read_dword( dtc_vect + 4);

337

data[2] = h8->program->read_dword( dtc_vect + 8);

338

dtc_mra = (data[0] >> 24) & 0xFF;

339

dtc_sar = (data[0] >> 0) & 0xFFFFFF;

340

dtc_mrb = (data[1] >> 24) & 0xFF;

341

dtc_dar = (data[1] >> 0) & 0xFFFFFF;

342

dtc_cra = (data[2] >> 16) & 0xFFFF;

343

dtc_crb = (data[2] >> 0) & 0xFFFF;

344

verboselog( h8->device->machine(), 3, "dtc : vect %08X mra %02X sar %08X mrb %02X dar %08X cra %04X crb %04X\n", dtc_vect, dtc_mra, dtc_sar, dtc_mrb, dtc_dar, dtc_cra, dtc_crb);

345

// execute

346

if ((dtc_mra & 0x0E) != 0x00) fatalerror("H8S: dtc unsupported MRA %x\n", dtc_mra&0x0e);

347

sz = 1 << (dtc_mra & 0x01);

348

cnt = dtc_cra;

349

for (i=0;i<cnt;i++)

350

{

351

if (dtc_sar == H8S_IO_ADDR( H8S_IO_RDR1)) h8->program->write_byte( H8S_IO_ADDR( H8S_IO_SSR1), h8->program->read_byte( H8S_IO_ADDR( H8S_IO_SSR1)) & (~H8S_SSR_TDRE));

352

if (dtc_mra & 0x01) h8->program->write_word( dtc_dar, h8->program->read_word( dtc_sar)); else h8->program->write_byte( dtc_dar, h8->program->read_byte( dtc_sar));

353

if (dtc_dar == H8S_IO_ADDR( H8S_IO_TDR0)) h8->program->write_byte( H8S_IO_ADDR( H8S_IO_SSR0), h8->program->read_byte( H8S_IO_ADDR( H8S_IO_SSR0)) & (~H8S_SSR_TDRE));

354

if (dtc_mra & 0x80) { if (dtc_mra & 0x40) dtc_sar -= sz; else dtc_sar += sz; }

355

if (dtc_mra & 0x20) { if (dtc_mra & 0x10) dtc_dar -= sz; else dtc_dar += sz; }

356

}

357

h8->program->write_byte( addr_dtce, h8->program->read_byte( addr_dtce) & (~mask_dtce));

358

}

359

360

void h8s_dtce_check(h83xx_state *h8, int vecnum)

361

{

362

UINT32 dtce = 0;

363

int bit = 0;

364

// get dtce info

365

switch (vecnum)

366

{

367

// DTCEA

368

case H8S_INT_IRQ0 : dtce = H8S_IO_DTCEA; bit = 7; break;

369

case H8S_INT_IRQ1 : dtce = H8S_IO_DTCEA; bit = 6; break;

370

case H8S_INT_IRQ2 : dtce = H8S_IO_DTCEA; bit = 5; break;

371

case H8S_INT_IRQ3 : dtce = H8S_IO_DTCEA; bit = 4; break;

372

case H8S_INT_IRQ4 : dtce = H8S_IO_DTCEA; bit = 3; break;

373

case H8S_INT_IRQ5 : dtce = H8S_IO_DTCEA; bit = 2; break;

374

case H8S_INT_IRQ6 : dtce = H8S_IO_DTCEA; bit = 1; break;

375

case H8S_INT_IRQ7 : dtce = H8S_IO_DTCEA; bit = 0; break;

376

// DTCEB

377

case H8S_INT_ADI : dtce = H8S_IO_DTCEB; bit = 6; break;

378

case H8S_INT_TGI0A : dtce = H8S_IO_DTCEB; bit = 5; break;

379

case H8S_INT_TGI0B : dtce = H8S_IO_DTCEB; bit = 4; break;

380

case H8S_INT_TGI0C : dtce = H8S_IO_DTCEB; bit = 3; break;

381

case H8S_INT_TGI0D : dtce = H8S_IO_DTCEB; bit = 2; break;

382

case H8S_INT_TGI1A : dtce = H8S_IO_DTCEB; bit = 1; break;

383

case H8S_INT_TGI1B : dtce = H8S_IO_DTCEB; bit = 0; break;

384

// DTCEC

385

case H8S_INT_TGI2A : dtce = H8S_IO_DTCEC; bit = 7; break;

386

case H8S_INT_TGI2B : dtce = H8S_IO_DTCEC; bit = 6; break;

387

// DTCED

388

case H8S_INT_CMIA0 : dtce = H8S_IO_DTCED; bit = 3; break;

389

case H8S_INT_CMIB0 : dtce = H8S_IO_DTCED; bit = 2; break;

390

case H8S_INT_CMIA1 : dtce = H8S_IO_DTCED; bit = 1; break;

391

case H8S_INT_CMIB1 : dtce = H8S_IO_DTCED; bit = 0; break;

392

// DTCEE

393

case H8S_INT_RXI0 : dtce = H8S_IO_DTCEE; bit = 3; break;

394

case H8S_INT_TXI0 : dtce = H8S_IO_DTCEE; bit = 2; break;

395

case H8S_INT_RXI1 : dtce = H8S_IO_DTCEE; bit = 1; break;

396

case H8S_INT_TXI1 : dtce = H8S_IO_DTCEE; bit = 0; break;

397

// DTCEF

398

case H8S_INT_RXI2 : dtce = H8S_IO_DTCEF; bit = 7; break;

399

case H8S_INT_TXI2 : dtce = H8S_IO_DTCEF; bit = 6; break;

400

}

401

// execute

402

if ((dtce != 0) && (h8->per_regs[dtce] & (1 << bit))) h8s_dtce_execute(h8, H8S_IO_ADDR( dtce), (1 << bit), DTVECR_ADDR( vecnum));

403

}

404

405

void h8s_periph_reset(h83xx_state *h8)

406

{

407

const int tpu_max = (h8->device->type() == H8S2323) ? 6 : 3;

408

if ((h8->device->type() == H8S2241) || (h8->device->type() == H8S2246))

409

{

410

memcpy( h8->per_regs, H8S_RESET_H8S_IO_224x, sizeof( h8->per_regs));

411

}

412

else if (h8->device->type() == H8S2323)

413

{

414

memcpy( h8->per_regs, H8S_RESET_H8S_IO_2323, sizeof( h8->per_regs));

415

}

416

for (int i = 0; i < 2; i++) h8s_tmr_x_reset( h8, i);

417

for (int i = 0; i < tpu_max; i++) h8s_tpu_x_reset( h8, i);

418

}

419

420

/////////////////

421

// TIMER 8-BIT //

422

/////////////////

423

424

void h8s_tmr_init(h83xx_state *h8)

425

{

426

for (int i = 0; i < 2; i++)

427

{

428

h8->tmr[i].timer = h8->device->machine().scheduler().timer_alloc(FUNC(h8s_tmr_callback), h8);

429

h8->tmr[i].timer->adjust(attotime::never, i);

430

}

431

}

432

433

void h8s_tmr_x_reset( h83xx_state *h8, int x)

434

{

435

H8S2XXX_TMR *tmr = &h8->tmr[x];

436

tmr->cycles_per_tick = 0;

437

tmr->timer->adjust(attotime::never, x);

438

}

439

440

UINT64 h8s_tmr_x_calculate_ticks( h83xx_state *h8, int x, UINT8 tcnt)

441

{

442

UINT64 cycles1, cycles2;

443

UINT8 tcor;

444

// overflow

445

if (tcnt == 0) cycles1 = 0xFF + 1; else cycles1 = (UINT8)(0xFF - tcnt + 1);

446

// tcora

447

tcor = h8->per_regs[H8S_IO_TCORA[x]];

448

if (tcnt == tcor) cycles2 = 0xFF + 1; else cycles2 = (UINT8)(tcor - tcnt);

449

if ((cycles2 > 0) && (cycles2 < cycles1)) cycles1 = cycles2;

450

// tcorb

451

tcor = h8->per_regs[H8S_IO_TCORB[x]];

452

if (tcnt == tcor) cycles2 = 0xFF + 1; else cycles2 = (UINT8)(tcor - tcnt);

453

if ((cycles2 > 0) && (cycles2 < cycles1)) cycles1 = cycles2;

454

// done

455

return cycles1;

456

}

457

458

void h8s_tmr_x_update( h83xx_state *h8, int x)

459

{

460

H8S2XXX_TMR *tmr = &h8->tmr[x];

461

UINT64 cycles;

462

int div = 0;

463

UINT8 tcr, tcnt;

464

tcr = h8->per_regs[H8S_IO_TCR[x]];

465

switch ((tcr >> 0) & 7)

466

{

467

case 1 : div = 8; break;

468

case 2 : div = 64; break;

469

case 3 : div = 8192; break;

470

// default : OS_MessageBox( NULL, "tmr_x_update", "error", 0); break;

471

}

472

tmr->cycles_per_tick = div;

473

tcnt = h8->per_regs[H8S_IO_TCNT[x]];

474

verboselog( h8->device->machine(), 5, "TMR %d - update (div %d tcnt %02X)\n", x, div, tcnt);

475

// update timer

476

cycles = h8s_tmr_x_calculate_ticks( h8, x, tcnt) * tmr->cycles_per_tick;

477

tmr->timer_cycles = cycles;

478

tmr->timer->adjust(attotime::from_hz(h8->device->unscaled_clock() / cycles), x);

479

}

480

481

UINT8 h8s_tmr_x_calculate_tcnt( h83xx_state *h8, int x)

482

{

483

H8S2XXX_TMR *tmr = &h8->tmr[x];

484

UINT8 tcnt;

485

tcnt = h8->per_regs[H8S_IO_TCNT[x]];

486

if (tmr->timer->enabled())

487

{

488

tcnt = (UINT8)(tcnt + ((device_icount_min_timer_icount1( h8, tmr->timer)) / tmr->cycles_per_tick));

489

}

490

return tcnt;

491

}

492

493

void h8s_tmr_x_start( h83xx_state *h8, int x)

494

{

495

verboselog( h8->device->machine(), 5, "TMR %d - start\n", x);

496

// ...

497

h8s_tmr_x_update( h8, x);

498

}

499

500

void h8s_tmr_x_stop( h83xx_state *h8, int x)

501

{

502

H8S2XXX_TMR *tmr = &h8->tmr[x];

503

UINT8 tcnt;

504

// ...

505

verboselog( h8->device->machine(), 5, "TMR %d - stop\n", x);

506

// calculate tcnt

507

tcnt = h8s_tmr_x_calculate_tcnt( h8, x);

508

// update tcnt

509

h8->per_regs[H8S_IO_TCNT[x]] = tcnt;

510

// disable timer

511

tmr->timer->reset();

512

}

513

514

UINT8 h8s_tmr_x_tcnt_change( h83xx_state *h8, int x, UINT8 tcnt)

515

{

516

UINT8 tcr, tcor;

517

int clear = 0;

518

// ...

519

verboselog( h8->device->machine(), 9, "TMR %d - tmr_x_tcnt_change (%02X)\n", x, tcnt);

520

// ...

521

tcr = h8->per_regs[H8S_IO_TCR[x]];

522

// overflow

523

if (tcnt == 0)

524

{

525

verboselog( h8->device->machine(), 9, "TMR %d - overflow match\n", x);

526

h8->per_regs[H8S_IO_TCSR[x]] |= TCSR_OVF;

527

if ((tcr & TCR_OVIE) != 0)

528

{

529

h8s2xxx_interrupt_request( h8, H8S_INT_OVI[x]);

530

}

531

}

532

// tcora

533

tcor = h8->per_regs[H8S_IO_TCORA[x]];

534

if (tcnt == tcor)

535

{

536

verboselog( h8->device->machine(), 9, "TMR %d - tcora match\n", x);

537

h8->per_regs[H8S_IO_TCSR[x]] |= TCSR_CMFA;

538

if ((tcr & TCR_CMIEA) != 0)

539

{

540

h8s2xxx_interrupt_request( h8, H8S_INT_CMIA[x]);

541

}

542

if (((tcr >> 3) & 3) == 1) // CCLR 1 -> "clear by compare match a"

543

{

544

clear = 1;

545

}

546

}

547

// tcorb

548

tcor = h8->per_regs[H8S_IO_TCORB[x]];

549

if (tcnt == tcor)

550

{

551

verboselog( h8->device->machine(), 9, "TMR %d - tcorb match\n", x);

552

h8->per_regs[H8S_IO_TCSR[x]] |= TCSR_CMFB;

553

if ((tcr & TCR_CMIEB) != 0)

554

{

555

h8s2xxx_interrupt_request( h8, H8S_INT_CMIB[x]);

556

}

557

if (((tcr >> 3) & 3) == 2) // CCLR 2 -> "clear by compare match b"

558

{

559

clear = 1;

560

}

561

}

562

// ...

563

if (clear)

564

{

565

verboselog( h8->device->machine(), 5, "TMR %d - tcnt clear\n", x);

566

tcnt = 0;

567

}

568

// ...

569

return tcnt;

570

}

571

572

void h8s_tmr_x_callback( h83xx_state *h8, int x)

573

{

574

H8S2XXX_TMR *tmr = &h8->tmr[x];

575

UINT64 cycles;

576

UINT8 tcnt;

577

// calculate tcnt

578

tcnt = h8->per_regs[H8S_IO_TCNT[x]];

579

tcnt = (UINT8)(tcnt + tmr->timer_cycles / tmr->cycles_per_tick);

580

// ...

581

tcnt = h8s_tmr_x_tcnt_change( h8, x, tcnt);

582

// update tcnt

583

h8->per_regs[H8S_IO_TCNT[x]] = tcnt;

584

// update timer

585

cycles = h8s_tmr_x_calculate_ticks( h8, x, tcnt) * tmr->cycles_per_tick;

586

tmr->timer_cycles = cycles;

587

tmr->timer->adjust(attotime::from_hz(h8->device->unscaled_clock() / cycles), x);

588

}

589

590

void h8s_tmr_x_write_tcr( h83xx_state *h8, int x, UINT8 data)

591

{

592

UINT8 old_data = h8->per_regs[H8S_IO_TCR[x]];

593

h8->per_regs[H8S_IO_TCR[x]] = data;

594

if ((data & 0x07) != (old_data & 0x07))

595

{

596

if ((data & 0x07) != 0)

597

{

598

h8s_tmr_x_start( h8, x);

599

}

600

else

601

{

602

h8s_tmr_x_stop( h8, x);

603

}

604

}

605

}

606

607

void h8s_tmr_x_write_tcnt( h83xx_state *h8, int x, UINT8 data)

608

{

609

H8S2XXX_TMR *tmr = &h8->tmr[x];

610

h8->per_regs[H8S_IO_TCNT[x]] = data;

611

if (tmr->timer->enabled())

612

{

613

h8s_tmr_x_update( h8, x);

614

}

615

}

616

617

void h8s_tmr_x_write_tcor( h83xx_state *h8, int x)

618

{

619

H8S2XXX_TMR *tmr = &h8->tmr[x];

620

if ((tmr->timer->enabled()) && (tmr->cycles_per_tick != 0))

621

{

622

UINT8 tcnt1, tcnt2;

623

UINT64 cycles;

624

tcnt1 = h8->per_regs[H8S_IO_TCNT[x]];

625

tcnt2 = (UINT8)(tcnt1 + ((device_icount_min_timer_icount1( h8, tmr->timer)) / tmr->cycles_per_tick));

626

cycles = h8s_tmr_x_calculate_ticks( h8, x, tcnt2) * tmr->cycles_per_tick;

627

cycles = cycles + (tcnt2 - tcnt1) * tmr->cycles_per_tick;

628

tmr->timer_cycles = cycles;

629

tmr->timer->adjust(attotime::from_hz(h8->device->unscaled_clock() / cycles), x);

630

}

631

}

632

633

UINT8 h8s_tmr_x_read_tcnt( h83xx_state *h8, int x)

634

{

635

return h8s_tmr_x_calculate_tcnt( h8, x);

636

}

637

638

void h8s_tmr_x_write_tcora( h83xx_state *h8, int x, UINT8 data)

639

{

640

h8->per_regs[H8S_IO_TCORA[x]] = data;

641

h8s_tmr_x_write_tcor( h8, x);

642

}

643

644

void h8s_tmr_x_write_tcorb( h83xx_state *h8, int x, UINT8 data)

645

{

646

h8->per_regs[H8S_IO_TCORB[x]] = data;

647

h8s_tmr_x_write_tcor( h8, x);

648

}

649

650

static TIMER_CALLBACK( h8s_tmr_callback)

651

{

652

h83xx_state *h8 = (h83xx_state *)ptr;

653

h8s_tmr_x_callback( h8, param);

654

}

655

656

//////////////////

657

// TIMER 16-BIT //

658

//////////////////

659

660

void h8s_tpu_init(h83xx_state *h8)

661

{

662

const int tpu_max = (h8->device->type() == H8S2323) ? 6 : 3;

663

for (int i = 0; i < tpu_max; i++)

664

{

665

h8->tpu[i].timer = h8->device->machine().scheduler().timer_alloc(FUNC(h8s_tpu_callback), h8);

666

h8->tpu[i].timer->adjust(attotime::never, i);

667

}

668

}

669

670

void h8s_tpu_x_reset( h83xx_state *h8, int x)

671

{

672

H8S2XXX_TPU *tpu = &h8->tpu[x];

673

tpu->cycles_per_tick = 0;

674

tpu->timer->reset();

675

}

676

677

UINT16 h8s_tpu_x_calculate_tcnt( h83xx_state *h8, int x)

678

{

679

H8S2XXX_TPU *tpu = &h8->tpu[x];

680

UINT16 tcnt;

681

tcnt = ptr_read_16( h8->per_regs + H8S_IO_TCNT_H[x]);

682

if ((tpu->timer->enabled()) && (tpu->cycles_per_tick > 0))

683

{

684

tcnt = (UINT16)(tcnt + ((device_icount_min_timer_icount1( h8, tpu->timer)) / tpu->cycles_per_tick));

685

}

686

return tcnt;

687

}

688

689

UINT64 h8s_tpu_x_calculate_ticks( h83xx_state *h8, int x, UINT16 tcnt)

690

{

691

UINT64 cycles1, cycles2;

692

UINT16 tgr;

693

// overflow

694

if (tcnt == 0) cycles1 = 0xFFFF + 1; else cycles1 = (UINT16)(0xFFFF - tcnt + 1);

695

// tgra

696

tgr = ptr_read_16( h8->per_regs + H8S_IO_TGRA_H[x]);

697

if (tcnt == tgr) cycles2 = 0xFFFF + 1; else cycles2 = (UINT16)(tgr - tcnt);

698

if ((cycles2 > 0) && (cycles2 < cycles1)) cycles1 = cycles2;

699

// tgrb

700

tgr = ptr_read_16( h8->per_regs + H8S_IO_TGRB_H[x]);

701

if (tcnt == tgr) cycles2 = 0xFFFF + 1; else cycles2 = (UINT16)(tgr - tcnt);

702

if ((cycles2 > 0) && (cycles2 < cycles1)) cycles1 = cycles2;

703

// tgrc

704

if ((x == 0) || (x == 3))

705

{

706

tgr = ptr_read_16( h8->per_regs + H8S_IO_TGRC_H[x]);

707

if (tcnt == tgr) cycles2 = 0xFFFF + 1; else cycles2 = (UINT16)(tgr - tcnt);

708

if ((cycles2 > 0) && (cycles2 < cycles1)) cycles1 = cycles2;

709

}

710

// tgrd

711

if ((x == 0) || (x == 3))

712

{

713

tgr = ptr_read_16( h8->per_regs + H8S_IO_TGRD_H[x]);

714

if (tcnt == tgr) cycles2 = 0xFFFF + 1; else cycles2 = (UINT16)(tgr - tcnt);

715

if ((cycles2 > 0) && (cycles2 < cycles1)) cycles1 = cycles2;

716

}

717

// done

718

return cycles1;

719

}

720

721

void h8s_pin_write( h83xx_state *h8, int pin, int data)

722

{

723

switch (pin)

724

{

725

case PIN_TIOCB1 :

726

{

727

UINT8 p1dr;

728

p1dr = h8->per_regs[H8S_IO_P1DR];

729

if (data) p1dr |= H8S_P1_TIOCB1; else p1dr &= ~H8S_P1_TIOCB1;

730

h8->io->write_byte(H8S_IO_ADDR(H8S_IO_P1DR), p1dr);

731

h8->per_regs[H8S_IO_P1DR] = p1dr;

732

}

733

break;

734

}

735

}

736

737

int h8s_pin_read( h83xx_state *h8, int pin)

738

{

739

switch (pin)

740

{

741

case PIN_TIOCB1 : return (h8->per_regs[H8S_IO_P1DR] & H8S_P1_TIOCB1) ? 1 : 0;

742

}

743

return 0;

744

}

745

746

void h8s_tioc_pin_update( h83xx_state *h8, int io, int pin)

747

{

748

switch (io)

749

{

750

case 1 : h8s_pin_write( h8, pin, 0); break;

751

case 2 : h8s_pin_write( h8, pin, 1); break;

752

case 3 : h8s_pin_write( h8, pin, h8s_pin_read( h8, pin) ? 0 : 1); break;

753

case 5 : h8s_pin_write( h8, pin, 0); break;

754

case 6 : h8s_pin_write( h8, pin, 1); break;

755

case 7 : h8s_pin_write( h8, pin, h8s_pin_read( h8, pin) ? 0 : 1); break;

756

}

757

}

758

759

void h8s_tioc_pin_reset( h83xx_state *h8, int io, int pin)

760

{

761

switch (io)

762

{

763

case 1 : h8s_pin_write( h8, pin, 0); break;

764

case 2 : h8s_pin_write( h8, pin, 0); break;

765

case 3 : h8s_pin_write( h8, pin, 0); break;

766

case 5 : h8s_pin_write( h8, pin, 1); break;

767

case 6 : h8s_pin_write( h8, pin, 1); break;

768

case 7 : h8s_pin_write( h8, pin, 1); break;

769

}

770

}

771

772

void h8s_tpu_x_tioc_reset( h83xx_state *h8, int x)

773

{

774

UINT8 tior;

775

int cclr;

776

// ...

777

cclr = (h8->per_regs[H8S_IO_TTCR[x]] >> 5) & TCR_CCLR_AND[x];

778

// tioca & tiocb

779

tior = h8->per_regs[H8S_IO_TIOR_H[x]];

780

if (cclr != 1) h8s_tioc_pin_reset( h8, (tior >> 0) & 0x0F, PIN_TIOCA[x]);

781

if (cclr != 2) h8s_tioc_pin_reset( h8, (tior >> 4) & 0x0F, PIN_TIOCB[x]);

782

// tiocc & tiocd

783

if ((x == 0) || (x == 3))

784

{

785

tior = h8->per_regs[H8S_IO_TIOR_L[x]];

786

if (cclr != 5) h8s_tioc_pin_reset( h8, (tior >> 0) & 0x0F, PIN_TIOCC[x]);

787

if (cclr != 6) h8s_tioc_pin_reset( h8, (tior >> 4) & 0x0F, PIN_TIOCD[x]);

788

}

789

}

790

791

void h8s_tpu_x_overflow( h83xx_state *h8, int x)

792

{

793

if (x == 2)

794

{

795

UINT8 tcr = h8->per_regs[H8S_IO_TTCR[1]];

796

if (((tcr >> 0) & 7) == 7)

797

{

798

h8s_tpu_x_tick( h8, 1);

799

}

800

}

801

if (x == 5)

802

{

803

UINT8 tcr = h8->per_regs[H8S_IO_TTCR[4]];

804

if (((tcr >> 0) & 7) == 7)

805

{

806

h8s_tpu_x_tick( h8, 4);

807

}

808

}

809

}

810

811

UINT16 h8s_tpu_x_tcnt_change( h83xx_state *h8, int x, UINT16 tcnt)

812

{

813

UINT16 tgr;

814

UINT8 tcr, tier, tior;

815

int clear = 0;

816

// ...

817

verboselog( h8->device->machine(), 9, "TPU %d - tpu_x_tcnt_change (%04X)\n", x, tcnt);

818

// ...

819

tcr = h8->per_regs[H8S_IO_TTCR[x]];

820

tier = h8->per_regs[H8S_IO_TIER[x]];

821

// overflow

822

if (tcnt == 0)

823

{

824

verboselog( h8->device->machine(), 9, "TPU %d - overflow match\n", x);

825

h8->per_regs[H8S_IO_TSR[x]] |= TSR_TCFV;

826

if (tier & TIER_TCIEV)

827

{

828

h8s2xxx_interrupt_request( h8, H8S_INT_TCIV[x]);

829

}

830

h8s_tpu_x_overflow( h8, x);

831

}

832

// tgra

833

tgr = ptr_read_16( h8->per_regs + H8S_IO_TGRA_H[x]);

834

if (tcnt == tgr)

835

{

836

verboselog( h8->device->machine(), 9, "TPU %d - tgra match\n", x);

837

h8->per_regs[H8S_IO_TSR[x]] |= TSR_TGFA;

838

if (tier & TIER_TGIEA)

839

{

840

h8s2xxx_interrupt_request( h8, H8S_INT_TGIA[x]);

841

}

842

if (((tcr >> 5) & TCR_CCLR_AND[x]) == 1) // CCLR 1 -> "TCNT cleared by TGRA compare match/input capture"

843

{

844

clear = 1;

845

}

846

else

847

{

848

tior = h8->per_regs[H8S_IO_TIOR_H[x]];

849

h8s_tioc_pin_update( h8, (tior >> 0) & 0x0F, PIN_TIOCA[x]);

850

}

851

}

852

// tgrb

853

tgr = ptr_read_16( h8->per_regs + H8S_IO_TGRB_H[x]);

854

if (tcnt == tgr)

855

{

856

verboselog( h8->device->machine(), 9, "TPU %d - tgrb match\n", x);

857

h8->per_regs[H8S_IO_TSR[x]] |= TSR_TGFB;

858

if (tier & TIER_TGIEB)

859

{

860

h8s2xxx_interrupt_request( h8, H8S_INT_TGIB[x]);

861

}

862

if (((tcr >> 5) & TCR_CCLR_AND[x]) == 2) // CCLR 2 -> "TCNT cleared by TGRB compare match/input capture"

863

{

864

clear = 1;

865

}

866

else

867

{

868

tior = h8->per_regs[H8S_IO_TIOR_H[x]];

869

h8s_tioc_pin_update( h8, (tior >> 4) & 0x0F, PIN_TIOCB[x]);

870

}

871

}

872

// tgrc

873

if ((x == 0) || (x == 3))

874

{

875

tgr = ptr_read_16( h8->per_regs + H8S_IO_TGRC_H[x]);

876

if (tcnt == tgr)

877

{

878

verboselog( h8->device->machine(), 9, "TPU %d - tgrc match\n", x);

879

h8->per_regs[H8S_IO_TSR[x]] |= TSR_TGFC;

880

if (tier & TIER_TGIEC)

881

{

882

h8s2xxx_interrupt_request( h8, H8S_INT_TGIC[x]);

883

}

884

if (((tcr >> 5) & TCR_CCLR_AND[x]) == 5) // CCLR 5 -> "TCNT cleared by TGRC compare match/input capture"

885

{

886

clear = 1;

887

}

888

else

889

{

890

tior = h8->per_regs[H8S_IO_TIOR_L[x]];

891

h8s_tioc_pin_update( h8, (tior >> 0) & 0x0F, PIN_TIOCC[x]);

892

}

893

}

894

}

895

// tgrd

896

if ((x == 0) || (x == 3))

897

{

898

tgr = ptr_read_16( h8->per_regs + H8S_IO_TGRD_H[x]);

899

if (tcnt == tgr)

900

{

901

verboselog( h8->device->machine(), 9, "TPU %d - tgrd match\n", x);

902

h8->per_regs[H8S_IO_TSR[x]] |= TSR_TGFD;

903

if (tier & TIER_TGIED)

904

{

905

h8s2xxx_interrupt_request( h8, H8S_INT_TGID[x]);

906

}

907

if (((tcr >> 5) & TCR_CCLR_AND[x]) == 6) // CCLR 6 -> "TCNT cleared by TGRD compare match/input capture"

908

{

909

clear = 1;

910

}

911

else

912

{

913

tior = h8->per_regs[H8S_IO_TIOR_L[x]];

914

h8s_tioc_pin_update( h8, (tior >> 4) & 0x0F, PIN_TIOCD[x]);

915

}

916

}

917

}

918

// ...

919

if (clear)

920

{

921

verboselog( h8->device->machine(), 9, "TPU %d - tcnt clear\n", x);

922

h8s_tpu_x_tioc_reset( h8, x);

923

tcnt = 0;

924

}

925

// ...

926

return tcnt;

927

}

928

929

void h8s_tpu_x_callback( h83xx_state *h8, int x)

930

{

931

H8S2XXX_TPU *tpu = &h8->tpu[x];

932

UINT64 cycles;

933

UINT16 tcnt;

934

// calculate tcnt

935

tcnt = ptr_read_16( h8->per_regs + H8S_IO_TCNT_H[x]);

936

tcnt = (UINT16)(tcnt + tpu->timer_cycles / tpu->cycles_per_tick);

937

// ...

938

tcnt = h8s_tpu_x_tcnt_change( h8, x, tcnt);

939

// update tcnt

940

ptr_write_16( h8->per_regs + H8S_IO_TCNT_H[x], tcnt);

941

// update timer

942

cycles = h8s_tpu_x_calculate_ticks( h8, x, tcnt) * tpu->cycles_per_tick;

943

tpu->timer_cycles = cycles;

944

tpu->timer->adjust(attotime::from_hz(h8->device->unscaled_clock() / cycles), x);

945

}

946

947

void h8s_tpu_x_tick( h83xx_state *h8, int x)

948

{

949

UINT16 tcnt;

950

// calculate tcnt

951

tcnt = ptr_read_16( h8->per_regs + H8S_IO_TCNT_H[x]);

952

tcnt = (UINT16)(tcnt + 1);

953

// ...

954

tcnt = h8s_tpu_x_tcnt_change( h8, x, tcnt);

955

// update tcnt

956

ptr_write_16( h8->per_regs + H8S_IO_TCNT_H[x], tcnt);

957

}

958

959

int h8s_tpu_x_get_div( h83xx_state *h8, int x)

960

{

961

UINT8 tcr;

962

int tpsc;

963

const int *TPU_X_DIV[] = { TPU_0_DIV, TPU_1_DIV, TPU_2_DIV, TPU_3_DIV, TPU_4_DIV, TPU_5_DIV };

964

tcr = h8->per_regs[H8S_IO_TTCR[x]];

965

tpsc = (tcr >> 0) & 7;

966

return TPU_X_DIV[x][tpsc];

967

}

968

969

void h8s_tpu_x_update( h83xx_state *h8, int x)

970

{

971

H8S2XXX_TPU *tpu = &h8->tpu[x];

972

// ...

973

tpu->cycles_per_tick = h8s_tpu_x_get_div( h8, x);

974

// update timer

975

if (tpu->cycles_per_tick != 0)

976

{

977

UINT16 tcnt;

978

UINT64 cycles;

979

tcnt = ptr_read_16( h8->per_regs + H8S_IO_TCNT_H[x]);

980

cycles = h8s_tpu_x_calculate_ticks( h8, x, tcnt) * tpu->cycles_per_tick;

981

tpu->timer_cycles = cycles;

982

tpu->timer->adjust(attotime::from_hz(h8->device->unscaled_clock() / cycles), x);

983

}

984

else

985

{

986

tpu->timer->reset();

987

}

988

}

989

990

void h8s_tpu_x_start( h83xx_state *h8, int x)

991

{

992

verboselog( h8->device->machine(), 5, "TPU %d - start\n", x);

993

// ...

994

h8s_tpu_x_update( h8, x);

995

}

996

997

void h8s_tpu_x_stop( h83xx_state *h8, int x)

998

{

999

H8S2XXX_TPU *tpu = &h8->tpu[x];

1000

UINT16 tcnt;

1001

// ...

1002

verboselog( h8->device->machine(), 5, "TPU %d - stop\n", x);

1003

// calculate tcnt

1004

tcnt = h8s_tpu_x_calculate_tcnt( h8, x);

1005

// update tcnt

1006

ptr_write_16( h8->per_regs + H8S_IO_TCNT_H[x], tcnt);

1007

// disable timer

1008

tpu->timer->reset();

1009

}

1010

1011

UINT16 h8s_tpu_x_read_tcnt( h83xx_state *h8, int x)

1012

{

1013

return h8s_tpu_x_calculate_tcnt( h8, x);

1014

}

1015

1016

void h8s_tpu_x_write_tcnt( h83xx_state *h8, int x, UINT16 data)

1017

{

1018

H8S2XXX_TPU *tpu = &h8->tpu[x];

1019

verboselog( h8->device->machine(), 9, "TPU %d - write tcnt (%04X)\n", x, data);

1020

ptr_write_16( h8->per_regs + H8S_IO_TCNT_H[x], data);

1021

if (tpu->timer->enabled())

1022

{

1023

h8s_tpu_x_update( h8, x);

1024

}

1025

}

1026

1027

void h8s_tpu_x_write_tgr( h83xx_state *h8, int x)

1028

{

1029

H8S2XXX_TPU *tpu = &h8->tpu[x];

1030

if ((tpu->timer->enabled()) && (tpu->cycles_per_tick != 0))

1031

{

1032

UINT16 tcnt1, tcnt2;

1033

UINT64 cycles;

1034

tcnt1 = ptr_read_16( h8->per_regs + H8S_IO_TCNT_H[x]);

1035

tcnt2 = (UINT16)(tcnt1 + ((device_icount_min_timer_icount1( h8, tpu->timer)) / tpu->cycles_per_tick));

1036

cycles = h8s_tpu_x_calculate_ticks( h8, x, tcnt2) * tpu->cycles_per_tick;

1037

cycles = cycles + (tcnt2 - tcnt1) * tpu->cycles_per_tick;

1038

tpu->timer_cycles = cycles;

1039

tpu->timer->adjust(attotime::from_hz(h8->device->unscaled_clock() / cycles), x);

1040

}

1041

}

1042

1043

void h8s_tpu_x_write_tgra( h83xx_state *h8, int x, UINT16 data)

1044

{

1045

verboselog( h8->device->machine(), 9, "TPU %d - write tgra (%04X)\n", x, data);

1046

ptr_write_16( h8->per_regs + H8S_IO_TGRA_H[x], data);

1047

h8s_tpu_x_write_tgr( h8, x);

1048

}

1049

1050

void h8s_tpu_x_write_tgrb( h83xx_state *h8, int x, UINT16 data)

1051

{

1052

verboselog( h8->device->machine(), 9, "TPU %d - write tgrb (%04X)\n", x, data);

1053

ptr_write_16( h8->per_regs + H8S_IO_TGRB_H[x], data);

1054

h8s_tpu_x_write_tgr( h8, x);

1055

}

1056

1057

void h8s_tpu_x_write_tgrc( h83xx_state *h8, int x, UINT16 data)

1058

{

1059

verboselog( h8->device->machine(), 9, "TPU %d - write tgrc (%04X)\n", x, data);

1060

ptr_write_16( h8->per_regs + H8S_IO_TGRC_H[x], data);

1061

h8s_tpu_x_write_tgr( h8, x);

1062

}

1063

1064

void h8s_tpu_x_write_tgrd( h83xx_state *h8, int x, UINT16 data)

1065

{

1066

verboselog( h8->device->machine(), 9, "TPU %d - write tgrd (%04X)\n", x, data);

1067

ptr_write_16( h8->per_regs + H8S_IO_TGRD_H[x], data);

1068

h8s_tpu_x_write_tgr( h8, x);

1069

}

1070

1071

void h8s_tpu_x_write_tior( h83xx_state *h8, int x)

1072

{

1073

UINT8 tstr;

1074

tstr = h8->per_regs[H8S_IO_TSTR];

1075

if ((tstr & (1 << x)) == 0)

1076

{

1077

h8s_tpu_x_tioc_reset( h8, x);

1078

}

1079

}

1080

1081

void h8s_tpu_0_write_tior_h( h83xx_state *h8, UINT8 data)

1082

{

1083

h8->per_regs[H8S_IO_TIOR0_H] = data;

1084

h8s_tpu_x_write_tior( h8, 0);

1085

}

1086

1087

void h8s_tpu_0_write_tior_l( h83xx_state *h8, UINT8 data)

1088

{

1089

h8->per_regs[H8S_IO_TIOR0_L] = data;

1090

h8s_tpu_x_write_tior( h8, 0);

1091

}

1092

1093

void h8s_tpu_1_write_tior( h83xx_state *h8, UINT8 data)

1094

{

1095

h8->per_regs[H8S_IO_TIOR1] = data;

1096

h8s_tpu_x_write_tior( h8, 1);

1097

}

1098

1099

void h8s_tpu_2_write_tior( h83xx_state *h8, UINT8 data)

1100

{

1101

h8->per_regs[H8S_IO_TIOR2] = data;

1102

h8s_tpu_x_write_tior( h8, 2);

1103

}

1104

1105

void h8s_tpu_3_write_tior_h( h83xx_state *h8, UINT8 data)

1106

{

1107

h8->per_regs[H8S_IO_TIOR3_H] = data;

1108

h8s_tpu_x_write_tior( h8, 3);

1109

}

1110

1111

void h8s_tpu_3_write_tior_l( h83xx_state *h8, UINT8 data)

1112

{

1113

h8->per_regs[H8S_IO_TIOR3_L] = data;

1114

h8s_tpu_x_write_tior( h8, 3);

1115

}

1116

1117

void h8s_tpu_4_write_tior( h83xx_state *h8, UINT8 data)

1118

{

1119

h8->per_regs[H8S_IO_TIOR4] = data;

1120

h8s_tpu_x_write_tior( h8, 4);

1121

}

1122

1123

void h8s_tpu_5_write_tior( h83xx_state *h8, UINT8 data)

1124

{

1125

h8->per_regs[H8S_IO_TIOR5] = data;

1126

h8s_tpu_x_write_tior( h8, 5);

1127

}

1128

1129

void h8s_tpu_write_tstr( h83xx_state *h8, UINT8 data)

1130

{

1131

const int tpu_max = (h8->device->type() == H8S2323) ? 6 : 3;

1132

UINT8 old_data = h8->per_regs[H8S_IO_TSTR];

1133

int i;

1134

h8->per_regs[H8S_IO_TSTR] = data;

1135

for (i = 0; i < tpu_max; i++)

1136

{

1137

if ((data & (1 << i)) != (old_data & (1 << i)))

1138

{

1139

if ((data & (1 << i)) != 0)

1140

{

1141

h8s_tpu_x_start( h8, i);

1142

}

1143

else

1144

{

1145

h8s_tpu_x_stop( h8, i);

1146

}

1147

}

1148

}

1149

}

1150

1151

static TIMER_CALLBACK( h8s_tpu_callback)

1152

{

1153

h83xx_state *h8 = (h83xx_state *)ptr;

1154

h8s_tpu_x_callback( h8, param);

1155

}

1156

1157

/////////////////////////////////

1158

// SERIAL CONTROLLER INTERFACE //

1159

/////////////////////////////////

1160

1161

typedef struct

1162

{

1163

UINT32 reg_smr, reg_brr, reg_scr, reg_tdr, reg_ssr, reg_rdr;

1164

UINT32 reg_pdr, reg_port;

1165

UINT8 port_mask_sck, port_mask_txd, port_mask_rxd;

1166

UINT8 int_tx, int_rx;

1167

} H8S_SCI_ENTRY;

1168

1169

const H8S_SCI_ENTRY H8S_SCI_TABLE[] =

1170

{

1171

// SCI 0

1172

{

1173

H8S_IO_SMR0, H8S_IO_BRR0, H8S_IO_SCR0, H8S_IO_TDR0, H8S_IO_SSR0, H8S_IO_RDR0,

1174

H8S_IO_P3DR, H8S_IO_PORT3,

1175

H8S_P3_SCK0, H8S_P3_TXD0, H8S_P3_RXD0,

1176

H8S_INT_TXI0, H8S_INT_RXI0

1177

1178

// SCI 1

1179

{

1180

H8S_IO_SMR1, H8S_IO_BRR1, H8S_IO_SCR1, H8S_IO_TDR1, H8S_IO_SSR1, H8S_IO_RDR1,

1181

H8S_IO_P3DR, H8S_IO_PORT3,

1182

H8S_P3_SCK1, H8S_P3_TXD1, H8S_P3_RXD1,

1183

H8S_INT_TXI1, H8S_INT_RXI1

1184

1185

// SCI 2

1186

{

1187

H8S_IO_SMR2, H8S_IO_BRR2, H8S_IO_SCR2, H8S_IO_TDR2, H8S_IO_SSR2, H8S_IO_RDR2,

1188

H8S_IO_P5DR, H8S_IO_PORT5,

1189

H8S_P5_SCK2, H8S_P5_TXD2, H8S_P5_RXD2,

1190

H8S_INT_TXI2, H8S_INT_RXI2

1191

}

1192

};

1193

1194

const H8S_SCI_ENTRY *h8s_sci_entry( int num)

1195

{

1196

return &H8S_SCI_TABLE[num];

1197

}

1198

1199

void h8s_sci_init(h83xx_state *h8)

1200

{

1201

int i;

1202

for (i=0;i<3;i++)

1203

{

1204

h8->sci[i].timer = h8->device->machine().scheduler().timer_alloc(FUNC(h8s_sci_callback), h8);

1205

h8->sci[i].timer->adjust(attotime::never, i);

1206

}

1207

}

1208

1209

static TIMER_CALLBACK(h8s_sci_callback)

1210

{

1211

h83xx_state *h8 = (h83xx_state *)ptr;

1212

verboselog( h8->device->machine(), 7, "h8s_sci_callback (%d)\n", param);

1213

}

1214

1215

void h8s_sci_start(h83xx_state *h8, int num)

1216

{

1217

#if 0

1218

h8->sci[num].timer->adjust(h8->sci[num].bitrate, num);

1219

#endif

1220

}

1221

1222

void h8s_sci_stop(h83xx_state *h8, int num)

1223

{

1224

h8->sci[num].timer->adjust(attotime::never, num);

1225

}

1226

1227

void h8s_sci_execute(h83xx_state *h8, int num)

1228

{

1229

UINT8 scr, tdr, ssr, rdr, tsr, rsr, pdr, port;

1230

int i;

1231

const H8S_SCI_ENTRY *info = h8s_sci_entry( num);

1232

verboselog( h8->device->machine(), 5, "h8s_sci_execute(%d)\n", num);

1233

// load regs

1234

scr = h8->per_regs[info->reg_scr];

1235

tdr = h8->per_regs[info->reg_tdr];

1236

ssr = h8->per_regs[info->reg_ssr];

1237

rdr = h8->per_regs[info->reg_rdr];

1238

tsr = 0;

1239

rsr = 0;

1240

pdr = h8->per_regs[info->reg_pdr] & (~info->port_mask_sck);

1241

// move byte from TDR to TSR

1242

if (scr & H8S_SCR_TE)

1243

{

1244

tsr = tdr;

1245

ssr |= H8S_SSR_TDRE;

1246

}

1247

// generate transmit data empty interrupt

1248

if ((scr & H8S_SCR_TIE) && (ssr & H8S_SSR_TDRE)) h8s2xxx_interrupt_request(h8, info->int_tx);

1249

// transmit/receive bits

1250

for (i=0;i<8;i++)

1251

{

1252

// write bit

1253

if (scr & H8S_SCR_TE)

1254

{

1255

if (tsr & (1 << i)) pdr = pdr | info->port_mask_txd; else pdr = pdr & (~info->port_mask_txd);

1256

h8->io->write_byte( H8S_IO_ADDR( info->reg_pdr), pdr);

1257

}

1258

// clock high to low

1259

h8->io->write_byte( H8S_IO_ADDR( info->reg_pdr), pdr | info->port_mask_sck);

1260

h8->io->write_byte( H8S_IO_ADDR( info->reg_pdr), pdr);

1261

// read bit

1262

if (scr & H8S_SCR_RE)

1263

{

1264

port = h8->io->read_byte(H8S_IO_ADDR( info->reg_port));

1265

if (port & info->port_mask_rxd) rsr = rsr | (1 << i);

1266

}

1267

}

1268

// move byte from RSR to RDR

1269

if (scr & H8S_SCR_RE)

1270

{

1271

rdr = rsr;

1272

//ssr |= H8S_SSR_RDRF;

1273

}

1274

// generate receive data full interrupt

1275

if ((scr & H8S_SCR_RIE) && (ssr & H8S_SSR_RDRF)) h8s2xxx_interrupt_request(h8, info->int_rx);

1276

// save regs

1277

h8->per_regs[info->reg_scr] = scr;

1278

h8->per_regs[info->reg_tdr] = tdr;

1279

h8->per_regs[info->reg_ssr] = ssr;

1280

h8->per_regs[info->reg_rdr] = rdr;

1281

}

1282

1283

const double SCR_CKE[] = { 0.5, 2, 8, 32 }; // = 2 ^ ((2 * cke) - 1)

1284

const int SMR_MODE[] = { 64, 8 };

1285

1286

void h8s_sci_rate(h83xx_state *h8, int num)

1287

{

1288

UINT8 brr, scr, smr, cke, mode;

1289

UINT32 bitrate;

1290

const H8S_SCI_ENTRY *info = h8s_sci_entry( num);

1291

// read regs

1292

brr = h8->per_regs[info->reg_brr];

1293

scr = h8->per_regs[info->reg_scr];

1294

smr = h8->per_regs[info->reg_smr];

1295

verboselog( h8->device->machine(), 2, "BRR %02X SCR %02X SMR %02X\n", brr, scr, smr);

1296

// calculate bitrate

1297

cke = (scr >> 0) & 3;

1298

mode = (smr >> 7) & 1;

1299

bitrate = (UINT32)((h8->device->unscaled_clock() / (brr + 1)) / (SMR_MODE[mode] * SCR_CKE[cke]));

1300

verboselog( h8->device->machine(), 2, "SCI%d bitrate %d\n", num, bitrate);

1301

// store bitrate

1302

h8->sci[num].bitrate = bitrate;

1303

}

1304

1305

////////////////////////////

1306

// INTERNAL I/O REGISTERS //

1307

////////////////////////////

1308

1309

void h8s_onchip_reg_write_8(h83xx_state *h8, int offset, UINT8 data)

1310

{

1311

verboselog( h8->device->machine(), 9, "%08X | %08X <- %02X\n", h8->ppc, H8S_IO_ADDR(offset), data);

1312

switch (offset)

1313

{

1314

// SCI 0

1315

case H8S_IO_SSR0 : h8->per_regs[offset] = data; if ((data & H8S_SSR_TDRE) == 0) h8s_sci_execute(h8, 0); break;

1316

case H8S_IO_SCR0 : h8->per_regs[offset] = data; if (data & H8S_SCR_TIE) h8s2xxx_interrupt_request(h8, h8s_sci_entry(0)->int_tx); break;

1317

case H8S_IO_BRR0 : h8->per_regs[offset] = data; h8s_sci_rate(h8, 0); h8s_sci_start(h8, 0); break;

1318

// SCI 1

1319

case H8S_IO_SSR1 : h8->per_regs[offset] = data; if ((data & H8S_SSR_TDRE) == 0) h8s_sci_execute(h8, 1); break;

1320

case H8S_IO_SCR1 : h8->per_regs[offset] = data; if (data & H8S_SCR_RIE) h8s2xxx_interrupt_request(h8, h8s_sci_entry(1)->int_rx); break;

1321

case H8S_IO_BRR1 : h8->per_regs[offset] = data; h8s_sci_rate(h8, 1); h8s_sci_start(h8, 1); break;

1322

// SCI 2

1323

case H8S_IO_SSR2 : h8->per_regs[offset] = data; if ((data & H8S_SSR_TDRE) == 0) h8s_sci_execute(h8, 2); break;

1324

case H8S_IO_SCR2 : h8->per_regs[offset] = data; if (data & H8S_SCR_TIE) h8s2xxx_interrupt_request(h8, h8s_sci_entry(2)->int_tx); break;

1325

case H8S_IO_BRR2 : h8->per_regs[offset] = data; h8s_sci_rate(h8, 2); h8s_sci_start(h8, 2); break;

1326

// TMR 0

1327

case H8S_IO_TCR0 : h8s_tmr_x_write_tcr( h8, 0, data); break;

1328

case H8S_IO_TCNT0 : h8s_tmr_x_write_tcnt( h8, 0, data); break;

1329

case H8S_IO_TCORA0 : h8s_tmr_x_write_tcora( h8, 0, data); break;

1330

case H8S_IO_TCORB0 : h8s_tmr_x_write_tcorb( h8, 0, data); break;

1331

// TMR 1

1332

case H8S_IO_TCR1 : h8s_tmr_x_write_tcr( h8, 1, data); break;

1333

case H8S_IO_TCNT1 : h8s_tmr_x_write_tcnt( h8, 1, data); break;

1334

case H8S_IO_TCORA1 : h8s_tmr_x_write_tcora( h8, 1, data); break;

1335

case H8S_IO_TCORB1 : h8s_tmr_x_write_tcorb( h8, 1, data); break;

1336

// ports

1337

case H8S_IO_P1DR : case H8S_IO_P2DR : case H8S_IO_P3DR : case H8S_IO_P4DR : case H8S_IO_P5DR :

1338

case H8S_IO_PADR : case H8S_IO_PBDR : case H8S_IO_PCDR : case H8S_IO_PDDR : case H8S_IO_PEDR :

1339

case H8S_IO_PFDR : h8->per_regs[offset] = data; h8->io->write_byte( H8S_IO_ADDR( offset), data); break;

1340

// ...

1341

case H8S_IO_PFDDR : h8->per_regs[offset] = data; h8->io->write_byte( H8S_IO_ADDR( offset), data); break;

1342

// TPU

1343

case H8S_IO_TSTR : h8s_tpu_write_tstr( h8, data); break;

1344

// DMA

1345

case H8S_IO_DMABCRL :

1346

{

1347

h8->per_regs[offset] = data;

1348

if (h8->device->type() == H8S2323)

1349

{

1350

if ((data & 0x40) && (data & 0x80))

1351

{

1352

UINT32 i, dma_src, dma_dst;

1353

UINT16 dma_cnt, dma_con;

1354

int sz;

1355

dma_src = h8->program->read_dword( H8S_IO_ADDR(H8S_IO_MAR1AH));

1356

dma_dst = h8->program->read_dword( H8S_IO_ADDR(H8S_IO_MAR1BH));

1357

dma_cnt = h8->program->read_word( H8S_IO_ADDR(H8S_IO_ETCR1A));

1358

dma_con = h8->program->read_word( H8S_IO_ADDR(H8S_IO_DMACR1A));

1359

sz = (dma_con & 0x8000) ? 2 : 1;

1360

for (i=0;i<dma_cnt;i++)

1361

{

1362

if (dma_con & 0x8000) h8->program->write_word( dma_dst, h8->program->read_word( dma_src)); else h8->program->write_byte( dma_dst, h8->program->read_byte( dma_src));

1363

if (dma_con & 0x2000) { if (dma_con & 0x4000) dma_src -= sz; else dma_src += sz; }

1364

if (dma_con & 0x0020) { if (dma_con & 0x0040) dma_dst -= sz; else dma_dst += sz; }

1365

}

1366

h8->per_regs[H8S_IO_DMABCRL] &= ~0x40;

1367

}

1368

}

1369

}

1370

break;

1371

// ...

1372

default :

1373

{

1374

h8->per_regs[offset] = data;

1375

}

1376

break;

1377

}

1378

}

1379

1380

void h8s_onchip_reg_write_16(h83xx_state *h8, int offset, UINT16 data)

1381

{

1382

verboselog( h8->device->machine(), 9, "%08X | %08X <- %04X\n", h8->ppc, H8S_IO_ADDR(offset), data);

1383

switch (offset)

1384

{

1385

// TPU 0

1386

case H8S_IO_TCNT0_H : h8s_tpu_x_write_tcnt( h8, 0, data); break;

1387

case H8S_IO_TGR0A_H : h8s_tpu_x_write_tgra( h8, 0, data); break;

1388

case H8S_IO_TGR0B_H : h8s_tpu_x_write_tgrb( h8, 0, data); break;

1389

case H8S_IO_TGR0C_H : h8s_tpu_x_write_tgrc( h8, 0, data); break;

1390

case H8S_IO_TGR0D_H : h8s_tpu_x_write_tgrd( h8, 0, data); break;

1391

// TPU 1

1392

case H8S_IO_TCNT1_H : h8s_tpu_x_write_tcnt( h8, 1, data); break;

1393

case H8S_IO_TGR1A_H : h8s_tpu_x_write_tgra( h8, 1, data); break;

1394

case H8S_IO_TGR1B_H : h8s_tpu_x_write_tgrb( h8, 1, data); break;

1395

// TPU 2

1396

case H8S_IO_TCNT2_H : h8s_tpu_x_write_tcnt( h8, 2, data); break;

1397

case H8S_IO_TGR2A_H : h8s_tpu_x_write_tgra( h8, 2, data); break;

1398

case H8S_IO_TGR2B_H : h8s_tpu_x_write_tgrb( h8, 2, data); break;

1399

// TPU 3

1400

case H8S_IO_TCNT3_H : if (h8->device->type() == H8S2323) h8s_tpu_x_write_tcnt( h8, 3, data); break;

1401

case H8S_IO_TGR3A_H : if (h8->device->type() == H8S2323) h8s_tpu_x_write_tgra( h8, 3, data); break;

1402

case H8S_IO_TGR3B_H : if (h8->device->type() == H8S2323) h8s_tpu_x_write_tgrb( h8, 3, data); break;

1403

case H8S_IO_TGR3C_H : if (h8->device->type() == H8S2323) h8s_tpu_x_write_tgrc( h8, 3, data); break;

1404

case H8S_IO_TGR3D_H : if (h8->device->type() == H8S2323) h8s_tpu_x_write_tgrd( h8, 3, data); break;

1405

// TPU 4

1406

case H8S_IO_TCNT4_H : if (h8->device->type() == H8S2323) h8s_tpu_x_write_tcnt( h8, 4, data); break;

1407

case H8S_IO_TGR4A_H : if (h8->device->type() == H8S2323) h8s_tpu_x_write_tgra( h8, 4, data); break;

1408

case H8S_IO_TGR4B_H : if (h8->device->type() == H8S2323) h8s_tpu_x_write_tgrb( h8, 4, data); break;

1409

// TPU 5

1410

case H8S_IO_TCNT5_H : if (h8->device->type() == H8S2323) h8s_tpu_x_write_tcnt( h8, 5, data); break;

1411

case H8S_IO_TGR5A_H : if (h8->device->type() == H8S2323) h8s_tpu_x_write_tgra( h8, 5, data); break;

1412

case H8S_IO_TGR5B_H : if (h8->device->type() == H8S2323) h8s_tpu_x_write_tgrb( h8, 5, data); break;

1413

// ...

1414

default :

1415

{

1416

h8s_onchip_reg_write_8( h8, offset + 0, (data >> 8) & 0xFF);

1417

h8s_onchip_reg_write_8( h8, offset + 1, (data >> 0) & 0xFF);

1418

}

1419

break;

1420

}

1421

}

1422

1423

UINT8 h8s_onchip_reg_read_8(h83xx_state *h8, int offset)

1424

{

1425

UINT8 data;

1426

switch (offset)

1427

{

1428

// SCI 0

1429

case H8S_IO_SSR0 : data = H8S_SSR_TDRE | H8S_SSR_TEND; break;

1430

case H8S_IO_RDR0 : data = h8->io->read_byte( H8S_IO_ADDR( offset)); break;

1431

// SCI 1

1432

case H8S_IO_SSR1 : data = H8S_SSR_TDRE | H8S_SSR_TEND; break;

1433

// SCI 2

1434

case H8S_IO_SSR2 :

1435

{

1436

data = h8->per_regs[offset];

1437

if (!(h8->per_regs[H8S_IO_SCR2] & H8S_SCR_TE)) data |= H8S_SSR_TDRE;

1438

}

1439

break;

1440

// ports

1441

case H8S_IO_PORT1 : case H8S_IO_PORT2 : case H8S_IO_PORT3 : case H8S_IO_PORT4 : case H8S_IO_PORT5 :

1442

case H8S_IO_PORTA : case H8S_IO_PORTB : case H8S_IO_PORTC : case H8S_IO_PORTD : case H8S_IO_PORTE :

1443

case H8S_IO_PORTF : data = h8->io->read_byte( H8S_IO_ADDR( offset)); break;

1444

// ...

1445

case H8S_IO_P3DR : data = 0; break; // todo: without this cybiko hangs

1446

// TMR 0

1447

case H8S_IO_TCNT0 : data = h8s_tmr_x_read_tcnt( h8, 0); break;

1448

// TMR 1

1449

case H8S_IO_TCNT1 : data = h8s_tmr_x_read_tcnt( h8, 1); break;

1450

// ...

1451

// default

1452

default : data = h8->per_regs[offset]; break;

1453

}

1454

verboselog( h8->device->machine(), 9, "%08X | %08X -> %02X\n", h8->ppc, H8S_IO_ADDR(offset), data);

1455

return data;

1456

}

1457

1458

UINT16 h8s_onchip_reg_read_16(h83xx_state *h8, int offset)

1459

{

1460

UINT16 data = 0;

1461

switch (offset)

1462

{

1463

case H8S_IO_TCNT0_H : data = h8s_tpu_x_read_tcnt( h8, 0); break;

1464

case H8S_IO_TCNT1_H : data = h8s_tpu_x_read_tcnt( h8, 1); break;

1465

case H8S_IO_TCNT2_H : data = h8s_tpu_x_read_tcnt( h8, 2); break;

1466

case H8S_IO_TCNT3_H : if (h8->device->type() == H8S2323) data = h8s_tpu_x_read_tcnt( h8, 3); break;

1467

case H8S_IO_TCNT4_H : if (h8->device->type() == H8S2323) data = h8s_tpu_x_read_tcnt( h8, 4); break;

1468

case H8S_IO_TCNT5_H : if (h8->device->type() == H8S2323) data = h8s_tpu_x_read_tcnt( h8, 5); break;

1469

default :

1470

{

1471

UINT8 b[2];

1472

b[0] = h8s_onchip_reg_read_8( h8, offset + 0);

1473

b[1] = h8s_onchip_reg_read_8( h8, offset + 1);

1474

data = (b[0] << 8) | (b[1] << 0);

1475

}

1476

break;

1477

}

1478

verboselog( h8->device->machine(), 9, "%08X | %08X -> %04X\n", h8->ppc, H8S_IO_ADDR(offset), data);

1479

return data;

1480

}

1481

1482

void h8s2241_per_regs_write_8(h83xx_state *h8, int offset, UINT8 data)

1483

{

1484

h8s_onchip_reg_write_8(h8, offset, data);

1485

}

1486

1487

UINT8 h8s2241_per_regs_read_8(h83xx_state *h8, int offset)

1488

{

1489

return h8s_onchip_reg_read_8(h8, offset);

1490

}

1491

1492

void h8s2241_per_regs_write_16(h83xx_state *h8, int offset, UINT16 data)

1493

{

1494

h8s_onchip_reg_write_16(h8, offset, data);

1495

}

1496

1497

UINT16 h8s2241_per_regs_read_16(h83xx_state *h8, int offset)

1498

{

1499

return h8s_onchip_reg_read_16(h8, offset);

1500

}

1501

1502

void h8s2246_per_regs_write_8(h83xx_state *h8, int offset, UINT8 data)

1503

{

1504

h8s_onchip_reg_write_8(h8, offset, data);

1505

}

1506

1507

UINT8 h8s2246_per_regs_read_8(h83xx_state *h8, int offset)

1508

{

1509

return h8s_onchip_reg_read_8(h8, offset);

1510

}

1511

1512

void h8s2246_per_regs_write_16(h83xx_state *h8, int offset, UINT16 data)

1513

{

1514

h8s_onchip_reg_write_16(h8, offset, data);

1515

}

1516

1517

UINT16 h8s2246_per_regs_read_16(h83xx_state *h8, int offset)

1518

{

1519

return h8s_onchip_reg_read_16(h8, offset);

1520

}

1521

1522

void h8s2323_per_regs_write_8(h83xx_state *h8, int offset, UINT8 data)

1523

{

1524

h8s_onchip_reg_write_8(h8, offset, data);

1525

}

1526

1527

UINT8 h8s2323_per_regs_read_8(h83xx_state *h8, int offset)

1528

{

1529

return h8s_onchip_reg_read_8(h8, offset);

1530

}

1531

1532

void h8s2323_per_regs_write_16(h83xx_state *h8, int offset, UINT16 data)

1533

{

1534

h8s_onchip_reg_write_16(h8, offset, data);

1535

}

1536

1537

UINT16 h8s2323_per_regs_read_16(h83xx_state *h8, int offset)

1538

{

1539

return h8s_onchip_reg_read_16(h8, offset);

1540

}

Older »