19
19
#define PTEA 0x200D /* FF000034 */
20
20
#define QACR0 0x200E /* FF000038 */
21
21
#define QACR1 0x200F /* FF00003C */
22
#define PRR 0x2011 /* FF000044 */
22
23
#define BARA 0x2400 /* FF200000 */
23
24
#define BAMRA 0x2401 /* FF200004 */
24
25
#define BBRA 0x2402 /* FF200008 */
48
49
#define GPIOIC 0x3012 /* FF800048 */
49
50
#define SDMR2 0x3200 /* FF900000 */
50
51
#define SDMR3 0x3280 /* FF940000 */
51
#define SAR0 0x3400 /* FFA00000 */
52
#define DAR0 0x3401 /* FFA00004 */
53
#define DMATCR0 0x3402 /* FFA00008 */
54
#define CHCR0 0x3403 /* FFA0000C */
55
#define SAR1 0x3404 /* FFA00010 */
56
#define DAR1 0x3405 /* FFA00014 */
57
#define DMATCR1 0x3406 /* FFA00018 */
58
#define CHCR1 0x3407 /* FFA0001C */
59
#define SAR2 0x3408 /* FFA00020 */
60
#define DAR2 0x3409 /* FFA00024 */
61
#define DMATCR2 0x340A /* FFA00028 */
62
#define CHCR2 0x340B /* FFA0002C */
63
#define SAR3 0x340C /* FFA00030 */
64
#define DAR3 0x340D /* FFA00034 */
65
#define DMATCR3 0x340E /* FFA00038 */
66
#define CHCR3 0x340F /* FFA0003C */
67
#define DMAOR 0x3410 /* FFA00040 */
52
#define SH4_SAR0_ADDR 0x3400 /* FFA00000 */
53
#define SH4_DAR0_ADDR 0x3401 /* FFA00004 */
54
#define SH4_DMATCR0_ADDR 0x3402 /* FFA00008 */
55
#define SH4_CHCR0_ADDR 0x3403 /* FFA0000C */
56
#define SH4_SAR1_ADDR 0x3404 /* FFA00010 */
57
#define SH4_DAR1_ADDR 0x3405 /* FFA00014 */
58
#define SH4_DMATCR1_ADDR 0x3406 /* FFA00018 */
59
#define SH4_CHCR1_ADDR 0x3407 /* FFA0001C */
60
#define SH4_SAR2_ADDR 0x3408 /* FFA00020 */
61
#define SH4_DAR2_ADDR 0x3409 /* FFA00024 */
62
#define SH4_DMATCR2_ADDR 0x340A /* FFA00028 */
63
#define SH4_CHCR2_ADDR 0x340B /* FFA0002C */
64
#define SH4_SAR3_ADDR 0x340C /* FFA00030 */
65
#define SH4_DAR3_ADDR 0x340D /* FFA00034 */
66
#define SH4_DMATCR3_ADDR 0x340E /* FFA00038 */
67
#define SH4_CHCR3_ADDR 0x340F /* FFA0003C */
68
#define SH4_DMAOR_ADDR 0x3410 /* FFA00040 */
68
69
#define SAR4 0x3414 /* FFA00050 */
69
70
#define DAR4 0x3415 /* FFA00054 */
70
71
#define DMATCR4 0x3416 /* FFA00058 */
122
123
#define TCOR4 0x205 /* FE100014 */
123
124
#define TCNT4 0x206 /* FE100018 */
124
125
#define TCR4 0x207 /* FE10001C */
125
#define TOCR 0x3B00 /* FFD80000 */
126
#define TSTR 0x3B01 /* FFD80004 */
127
#define TCOR0 0x3B02 /* FFD80008 */
128
#define TCNT0 0x3B03 /* FFD8000C */
129
#define TCR0 0x3B04 /* FFD80010 */
130
#define TCOR1 0x3B05 /* FFD80014 */
131
#define TCNT1 0x3B06 /* FFD80018 */
132
#define TCR1 0x3B07 /* FFD8001C */
133
#define TCOR2 0x3B08 /* FFD80020 */
134
#define TCNT2 0x3B09 /* FFD80024 */
135
#define TCR2 0x3B0A /* FFD80028 */
136
#define TCPR2 0x3B0B /* FFD8002C */
126
#define SH4_TOCR_ADDR 0x3B00 /* FFD80000 */
127
#define SH4_TSTR_ADDR 0x3B01 /* FFD80004 */
128
#define SH4_TCOR0_ADDR 0x3B02 /* FFD80008 */
129
#define SH4_TCNT0_ADDR 0x3B03 /* FFD8000C */
130
#define SH4_TCR0_ADDR 0x3B04 /* FFD80010 */
131
#define SH4_TCOR1_ADDR 0x3B05 /* FFD80014 */
132
#define SH4_TCNT1_ADDR 0x3B06 /* FFD80018 */
133
#define SH4_TCR1_ADDR 0x3B07 /* FFD8001C */
134
#define SH4_TCOR2_ADDR 0x3B08 /* FFD80020 */
135
#define SH4_TCNT2_ADDR 0x3B09 /* FFD80024 */
136
#define SH4_TCR2_ADDR 0x3B0A /* FFD80028 */
137
#define SH4_TCPR2_ADDR 0x3B0B /* FFD8002C */
137
138
#define SCSMR1 0x3C00 /* FFE00000 */
138
139
#define SCBRR1 0x3C01 /* FFE00004 */
139
140
#define SCSCR1 0x3C02 /* FFE00008 */
157
158
#define SDINT 0x3E05 /* FFF00014 */
158
159
#define SIZEREGS 15878
163
#define MMUCR_LRUI 0xfc000000
164
#define MMUCR_URB 0x00fc0000
165
#define MMUCR_URC 0x0000fc00
166
#define MMUCR_SQMD 0x00000200
167
#define MMUCR_SV 0x00000100
168
#define MMUCR_TI 0x00000004
169
#define MMUCR_AT 0x00000001
172
#define PVR_SH7091 0x040205c1
173
#define PVR_SH7750 0x04020500 // from TN-SH7-361B/E
174
#define PVR_SH7750S 0x04020600
175
#define PVR_SH7750R 0x04050000
176
#define PRR_SH7750R 0x00000100
177
#define PVR_SH7751 0x04110000
178
#define PVR_SH7751R 0x04050000
179
#define PRR_SH7751R 0x00000110
160
181
#endif /* __SH4REGS_H__ */
added
removed
src/emu/cpu/sh4/sh4regs.h
