1
#define ADDRESS_MAP_MODERN
6
DEVICE_ADDRESS_MAP_START(amap, 32, naomi_g1_device)
7
AM_RANGE(0x04, 0x07) AM_READWRITE(sb_gdstar_r, sb_gdstar_w)
8
AM_RANGE(0x08, 0x0b) AM_READWRITE(sb_gdlen_r, sb_gdlen_w)
9
AM_RANGE(0x0c, 0x0f) AM_READWRITE(sb_gddir_r, sb_gddir_w)
10
AM_RANGE(0x14, 0x17) AM_READWRITE(sb_gden_r, sb_gden_w)
11
AM_RANGE(0x18, 0x1b) AM_READWRITE(sb_gdst_r, sb_gdst_w)
12
AM_RANGE(0x80, 0x83) AM_WRITE(sb_g1rrc_w)
13
AM_RANGE(0x84, 0x87) AM_WRITE(sb_g1rwc_w)
14
AM_RANGE(0x88, 0x8b) AM_WRITE(sb_g1frc_w)
15
AM_RANGE(0x8c, 0x8f) AM_WRITE(sb_g1fwc_w)
16
AM_RANGE(0x90, 0x93) AM_WRITE(sb_g1crc_w)
17
AM_RANGE(0x94, 0x97) AM_WRITE(sb_g1cwc_w)
18
AM_RANGE(0xa0, 0xa3) AM_WRITE(sb_g1gdrc_w)
19
AM_RANGE(0xa4, 0xa7) AM_WRITE(sb_g1gdwc_w)
20
AM_RANGE(0xb0, 0xb3) AM_READ(sb_g1sysm_r)
21
AM_RANGE(0xb4, 0xb7) AM_WRITE(sb_g1crdyc_w)
22
AM_RANGE(0xb8, 0xbb) AM_WRITE(sb_gdapro_w)
23
AM_RANGE(0xf4, 0xf7) AM_READ(sb_gdstard_r)
24
AM_RANGE(0xf8, 0xfb) AM_READ(sb_gdlend_r)
27
naomi_g1_device::naomi_g1_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock)
28
: device_t(mconfig, type, name, tag, owner, clock)
33
void naomi_g1_device::static_set_maincpu_tag(device_t &device, const char *maincpu_tag)
35
naomi_g1_device &naomi_g1 = downcast<naomi_g1_device &>(device);
36
naomi_g1.maincpu_tag = maincpu_tag;
39
void naomi_g1_device::static_set_irq_cb(device_t &device, void (*irq_cb)(running_machine &))
41
naomi_g1_device &naomi_g1 = downcast<naomi_g1_device &>(device);
42
naomi_g1.irq_cb = irq_cb;
45
void naomi_g1_device::device_start()
47
cpu = machine().device<sh4_device>(maincpu_tag);
48
timer = timer_alloc(G1_TIMER_ID);
50
save_item(NAME(gdstar));
51
save_item(NAME(gdlen));
52
save_item(NAME(gddir));
53
save_item(NAME(gden));
54
save_item(NAME(gdst));
57
void naomi_g1_device::device_reset()
66
void naomi_g1_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
68
timer.adjust(attotime::never);
76
READ32_MEMBER(naomi_g1_device::sb_gdstar_r)
81
WRITE32_MEMBER(naomi_g1_device::sb_gdstar_w)
83
COMBINE_DATA(&gdstar);
84
logerror("G1: gdstar_w %08x @ %08x\n", data, mem_mask);
87
READ32_MEMBER(naomi_g1_device::sb_gdlen_r)
92
WRITE32_MEMBER(naomi_g1_device::sb_gdlen_w)
95
logerror("G1: gdlen_w %08x @ %08x\n", data, mem_mask);
98
READ32_MEMBER(naomi_g1_device::sb_gddir_r)
103
WRITE32_MEMBER(naomi_g1_device::sb_gddir_w)
105
COMBINE_DATA(&gddir);
107
logerror("G1: gddir_w %08x @ %08x\n", data, mem_mask);
110
READ32_MEMBER(naomi_g1_device::sb_gden_r)
115
WRITE32_MEMBER(naomi_g1_device::sb_gden_w)
119
logerror("G1: gden_w %08x @ %08x\n", data, mem_mask);
122
READ32_MEMBER(naomi_g1_device::sb_gdst_r)
127
WRITE32_MEMBER(naomi_g1_device::sb_gdst_w)
132
logerror("G1: gdst_w %08x @ %08x\n", data, mem_mask);
133
if(!old && gdst && gden) {
139
// Deunan says round up to 32, doc says complete with zeroes.
140
// Virtua Tennis requires one of the two to boot
141
// We'll go with DK for now.
143
// In any case, low bit is ignored
144
len = (len + 30) & ~30;
146
bool to_mainram = true;
150
dma_get_position(base, limit, to_mainram);
154
UINT32 tlen = limit > len ? len : limit;
155
dma(base, adr, tlen, to_mainram);
161
while(len && to_mainram) {
162
unsigned char zero[32];
163
memset(zero, 0, sizeof(zero));
164
UINT32 tlen = len > 32 ? 32 : len;
165
dma(zero, adr, tlen, to_mainram);
170
timer->adjust(attotime::from_usec(500));
174
WRITE32_MEMBER(naomi_g1_device::sb_g1rrc_w)
176
logerror("G1: g1rrc_w %08x @ %08x\n", data, mem_mask);
179
WRITE32_MEMBER(naomi_g1_device::sb_g1rwc_w)
181
logerror("G1: g1rwc_w %08x @ %08x\n", data, mem_mask);
184
WRITE32_MEMBER(naomi_g1_device::sb_g1crc_w)
186
logerror("G1: g1crc_w %08x @ %08x\n", data, mem_mask);
189
WRITE32_MEMBER(naomi_g1_device::sb_g1cwc_w)
191
logerror("G1: g1cwc_w %08x @ %08x\n", data, mem_mask);
194
WRITE32_MEMBER(naomi_g1_device::sb_g1frc_w)
196
logerror("G1: g1frc_w %08x @ %08x\n", data, mem_mask);
199
WRITE32_MEMBER(naomi_g1_device::sb_g1fwc_w)
201
logerror("G1: g1fwc_w %08x @ %08x\n", data, mem_mask);
204
WRITE32_MEMBER(naomi_g1_device::sb_g1gdrc_w)
206
logerror("G1: g1gdrc_w %08x @ %08x\n", data, mem_mask);
209
WRITE32_MEMBER(naomi_g1_device::sb_g1gdwc_w)
211
logerror("G1: g1gdwc_w %08x @ %08x\n", data, mem_mask);
214
READ32_MEMBER(naomi_g1_device::sb_g1sysm_r)
216
logerror("G1: g1sysm_r @ %08x\n", mem_mask);
220
WRITE32_MEMBER(naomi_g1_device::sb_g1crdyc_w)
222
logerror("G1: g1crdyc_w %08x @ %08x\n", data, mem_mask);
225
WRITE32_MEMBER(naomi_g1_device::sb_gdapro_w)
227
logerror("G1: gdapro_w %08x @ %08x\n", data, mem_mask);
230
READ32_MEMBER(naomi_g1_device::sb_gdstard_r)
232
logerror("G1: gdstard_r @ %08x\n", mem_mask);
236
READ32_MEMBER(naomi_g1_device::sb_gdlend_r)
238
logerror("G1: gdlend_r @ %08x\n", mem_mask);
242
void naomi_g1_device::dma(void *dma_ptr, UINT32 main_adr, UINT32 size, bool to_mainram)
246
ddt.destination = main_adr;
248
ddt.source = main_adr;
249
ddt.buffer = dma_ptr;
250
ddt.length = size >> 5;
252
ddt.direction = to_mainram;
255
sh4_dma_ddt(cpu, &ddt);