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Copyright (C) Intel Corp. 2006. All Rights Reserved.
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Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
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develop this 3D driver.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice (including the
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next paragraph) shall be included in all copies or substantial
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portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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**********************************************************************/
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* Keith Whitwell <keith@tungstengraphics.com>
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#include "main/glheader.h"
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#include "main/macros.h"
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#include "main/enums.h"
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#include "program/program.h"
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#include "intel_batchbuffer.h"
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#include "brw_defines.h"
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#include "brw_context.h"
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* Allocate registers for GS.
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* If sol_program is true, then:
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* - The thread will be spawned with the "SVBI Payload Enable" bit set, so GRF
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* 1 needs to be set aside to hold the streamed vertex buffer indices.
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* - The thread will need to use the destination_indices register.
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static void brw_gs_alloc_regs( struct brw_gs_compile *c,
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/* Register usage is static, precompute here:
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c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
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/* Streamed vertex buffer indices */
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c->reg.SVBI = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
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/* Payload vertices plus space for more generated vertices:
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for (j = 0; j < nr_verts; j++) {
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c->reg.vertex[j] = brw_vec4_grf(i, 0);
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c->reg.header = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
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c->reg.temp = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
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c->reg.destination_indices =
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retype(brw_vec4_grf(i++, 0), BRW_REGISTER_TYPE_UD);
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c->prog_data.urb_read_length = c->nr_regs;
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c->prog_data.total_grf = i;
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* Set up the initial value of c->reg.header register based on c->reg.R0.
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* The following information is passed to the GS thread in R0, and needs to be
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* included in the first URB_WRITE or FF_SYNC message sent by the GS:
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* - DWORD 0 [31:0] handle info (Gen4 only)
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* - DWORD 5 [7:0] FFTID
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* - DWORD 6 [31:0] Debug info
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* - DWORD 7 [31:0] Debug info
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* This function sets up the above data by copying by copying the contents of
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* R0 to the header register.
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static void brw_gs_initialize_header(struct brw_gs_compile *c)
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struct brw_compile *p = &c->func;
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brw_MOV(p, c->reg.header, c->reg.R0);
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* Overwrite DWORD 2 of c->reg.header with the given immediate unsigned value.
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* In URB_WRITE messages, DWORD 2 contains the fields PrimType, PrimStart,
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* PrimEnd, Increment CL_INVOCATIONS, and SONumPrimsWritten, many of which we
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* need to be able to update on a per-vertex basis.
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static void brw_gs_overwrite_header_dw2(struct brw_gs_compile *c,
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struct brw_compile *p = &c->func;
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brw_MOV(p, get_element_ud(c->reg.header, 2), brw_imm_ud(dw2));
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* Overwrite DWORD 2 of c->reg.header with the primitive type from c->reg.R0.
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* When the thread is spawned, GRF 0 contains the primitive type in bits 4:0
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* of DWORD 2. URB_WRITE messages need the primitive type in bits 6:2 of
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* DWORD 2. So this function extracts the primitive type field, bitshifts it
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* appropriately, and stores it in c->reg.header.
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static void brw_gs_overwrite_header_dw2_from_r0(struct brw_gs_compile *c)
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struct brw_compile *p = &c->func;
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brw_AND(p, get_element_ud(c->reg.header, 2), get_element_ud(c->reg.R0, 2),
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brw_SHL(p, get_element_ud(c->reg.header, 2),
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get_element_ud(c->reg.header, 2), brw_imm_ud(2));
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* Apply an additive offset to DWORD 2 of c->reg.header.
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* This is used to set/unset the "PrimStart" and "PrimEnd" flags appropriately
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static void brw_gs_offset_header_dw2(struct brw_gs_compile *c, int offset)
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struct brw_compile *p = &c->func;
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brw_ADD(p, get_element_d(c->reg.header, 2), get_element_d(c->reg.header, 2),
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* Emit a vertex using the URB_WRITE message. Use the contents of
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* c->reg.header for the message header, and the registers starting at \c vert
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* for the vertex data.
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* If \c last is true, then this is the last vertex, so no further URB space
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* should be allocated, and this message should end the thread.
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* If \c last is false, then a new URB entry will be allocated, and its handle
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* will be stored in DWORD 0 of c->reg.header for use in the next URB_WRITE
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static void brw_gs_emit_vue(struct brw_gs_compile *c,
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struct brw_compile *p = &c->func;
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bool allocate = !last;
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/* Copy the vertex from vertn into m1..mN+1:
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brw_copy8(p, brw_message_reg(1), vert, c->nr_regs);
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/* Send each vertex as a seperate write to the urb. This is
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* different to the concept in brw_sf_emit.c, where subsequent
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* writes are used to build up a single urb entry. Each of these
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* writes instantiates a seperate urb entry, and a new one must be
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* allocated each time.
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allocate ? c->reg.temp
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: retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
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c->nr_regs + 1, /* msg length */
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allocate ? 1 : 0, /* response length */
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allocate ? 0 : 1, /* eot */
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1, /* writes_complete */
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BRW_URB_SWIZZLE_NONE);
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brw_MOV(p, get_element_ud(c->reg.header, 0),
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get_element_ud(c->reg.temp, 0));
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* De-allocate the URB entry that was previously allocated to this thread
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* (without writing any vertex data to it), and terminate the thread. This is
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* used to implement RASTERIZER_DISCARD functionality.
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static void brw_gs_terminate(struct brw_gs_compile *c)
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struct brw_compile *p = &c->func;
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retype(brw_null_reg(), BRW_REGISTER_TYPE_UD), /* dest */
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c->reg.header, /* src0 */
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false, /* allocate */
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0, /* response_length */
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true, /* writes_complete */
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BRW_URB_SWIZZLE_NONE);
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* Send an FF_SYNC message to ensure that all previously spawned GS threads
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* have finished sending primitives down the pipeline, and to allocate a URB
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* entry for the first output vertex. Only needed when intel->needs_ff_sync
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* This function modifies c->reg.header: in DWORD 1, it stores num_prim (which
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* is needed by the FF_SYNC message), and in DWORD 0, it stores the handle to
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* the allocated URB entry (which will be needed by the URB_WRITE meesage that
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static void brw_gs_ff_sync(struct brw_gs_compile *c, int num_prim)
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struct brw_compile *p = &c->func;
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brw_MOV(p, get_element_ud(c->reg.header, 1), brw_imm_ud(num_prim));
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1, /* response length */
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brw_MOV(p, get_element_ud(c->reg.header, 0),
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get_element_ud(c->reg.temp, 0));
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void brw_gs_quads( struct brw_gs_compile *c, struct brw_gs_prog_key *key )
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struct intel_context *intel = &c->func.brw->intel;
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brw_gs_alloc_regs(c, 4, false);
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brw_gs_initialize_header(c);
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/* Use polygons for correct edgeflag behaviour. Note that vertex 3
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* is the PV for quads, but vertex 0 for polygons:
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if (intel->needs_ff_sync)
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brw_gs_ff_sync(c, 1);
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brw_gs_overwrite_header_dw2(
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c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
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| URB_WRITE_PRIM_START));
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brw_gs_emit_vue(c, c->reg.vertex[0], 0);
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brw_gs_overwrite_header_dw2(
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c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
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brw_gs_emit_vue(c, c->reg.vertex[1], 0);
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brw_gs_emit_vue(c, c->reg.vertex[2], 0);
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brw_gs_overwrite_header_dw2(
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c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
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| URB_WRITE_PRIM_END));
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brw_gs_emit_vue(c, c->reg.vertex[3], 1);
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brw_gs_emit_vue(c, c->reg.vertex[3], 0);
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brw_gs_overwrite_header_dw2(
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c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
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brw_gs_emit_vue(c, c->reg.vertex[0], 0);
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brw_gs_emit_vue(c, c->reg.vertex[1], 0);
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brw_gs_overwrite_header_dw2(
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c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
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| URB_WRITE_PRIM_END));
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brw_gs_emit_vue(c, c->reg.vertex[2], 1);
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void brw_gs_quad_strip( struct brw_gs_compile *c, struct brw_gs_prog_key *key )
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struct intel_context *intel = &c->func.brw->intel;
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brw_gs_alloc_regs(c, 4, false);
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brw_gs_initialize_header(c);
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if (intel->needs_ff_sync)
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brw_gs_ff_sync(c, 1);
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brw_gs_overwrite_header_dw2(
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c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
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| URB_WRITE_PRIM_START));
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brw_gs_emit_vue(c, c->reg.vertex[0], 0);
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brw_gs_overwrite_header_dw2(
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c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
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brw_gs_emit_vue(c, c->reg.vertex[1], 0);
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brw_gs_emit_vue(c, c->reg.vertex[2], 0);
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brw_gs_overwrite_header_dw2(
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c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
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| URB_WRITE_PRIM_END));
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brw_gs_emit_vue(c, c->reg.vertex[3], 1);
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brw_gs_emit_vue(c, c->reg.vertex[2], 0);
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brw_gs_overwrite_header_dw2(
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c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
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brw_gs_emit_vue(c, c->reg.vertex[3], 0);
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brw_gs_emit_vue(c, c->reg.vertex[0], 0);
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brw_gs_overwrite_header_dw2(
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c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
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| URB_WRITE_PRIM_END));
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brw_gs_emit_vue(c, c->reg.vertex[1], 1);
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void brw_gs_lines( struct brw_gs_compile *c )
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struct intel_context *intel = &c->func.brw->intel;
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brw_gs_alloc_regs(c, 2, false);
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brw_gs_initialize_header(c);
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if (intel->needs_ff_sync)
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brw_gs_ff_sync(c, 1);
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brw_gs_overwrite_header_dw2(
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c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
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| URB_WRITE_PRIM_START));
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brw_gs_emit_vue(c, c->reg.vertex[0], 0);
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brw_gs_overwrite_header_dw2(
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c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
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| URB_WRITE_PRIM_END));
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brw_gs_emit_vue(c, c->reg.vertex[1], 1);
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* Generate the geometry shader program used on Gen6 to perform stream output
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* (transform feedback).
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gen6_sol_program(struct brw_gs_compile *c, struct brw_gs_prog_key *key,
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unsigned num_verts, bool check_edge_flags)
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struct brw_compile *p = &c->func;
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c->prog_data.svbi_postincrement_value = num_verts;
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brw_gs_alloc_regs(c, num_verts, true);
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brw_gs_initialize_header(c);
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if (key->num_transform_feedback_bindings > 0) {
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unsigned vertex, binding;
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struct brw_reg destination_indices_uw =
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vec8(retype(c->reg.destination_indices, BRW_REGISTER_TYPE_UW));
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/* Note: since we use the binding table to keep track of buffer offsets
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* and stride, the GS doesn't need to keep track of a separate pointer
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* into each buffer; it uses a single pointer which increments by 1 for
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* each vertex. So we use SVBI0 for this pointer, regardless of whether
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* transform feedback is in interleaved or separate attribs mode.
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* Make sure that the buffers have enough room for all the vertices.
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brw_ADD(p, get_element_ud(c->reg.temp, 0),
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get_element_ud(c->reg.SVBI, 0), brw_imm_ud(num_verts));
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brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_LE,
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get_element_ud(c->reg.temp, 0),
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get_element_ud(c->reg.SVBI, 4));
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brw_IF(p, BRW_EXECUTE_1);
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/* Compute the destination indices to write to. Usually we use SVBI[0]
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* + (0, 1, 2). However, for odd-numbered triangles in tristrips, the
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* vertices come down the pipeline in reversed winding order, so we need
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* to flip the order when writing to the transform feedback buffer. To
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* ensure that flatshading accuracy is preserved, we need to write them
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* in order SVBI[0] + (0, 2, 1) if we're using the first provoking
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* vertex convention, and in order SVBI[0] + (1, 0, 2) if we're using
387
* the last provoking vertex convention.
389
* Note: since brw_imm_v can only be used in instructions in
390
* packed-word execution mode, and SVBI is a double-word, we need to
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* first move the appropriate immediate constant ((0, 1, 2), (0, 2, 1),
392
* or (1, 0, 2)) to the destination_indices register, and then add SVBI
393
* using a separate instruction. Also, since the immediate constant is
394
* expressed as packed words, and we need to load double-words into
395
* destination_indices, we need to intersperse zeros to fill the upper
396
* halves of each double-word.
398
brw_MOV(p, destination_indices_uw,
399
brw_imm_v(0x00020100)); /* (0, 1, 2) */
400
if (num_verts == 3) {
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/* Get primitive type into temp register. */
402
brw_AND(p, get_element_ud(c->reg.temp, 0),
403
get_element_ud(c->reg.R0, 2), brw_imm_ud(0x1f));
405
/* Test if primitive type is TRISTRIP_REVERSE. We need to do this as
406
* an 8-wide comparison so that the conditional MOV that follows
407
* moves all 8 words correctly.
409
brw_CMP(p, vec8(brw_null_reg()), BRW_CONDITIONAL_EQ,
410
get_element_ud(c->reg.temp, 0),
411
brw_imm_ud(_3DPRIM_TRISTRIP_REVERSE));
413
/* If so, then overwrite destination_indices_uw with the appropriate
416
brw_MOV(p, destination_indices_uw,
417
brw_imm_v(key->pv_first ? 0x00010200 /* (0, 2, 1) */
418
: 0x00020001)); /* (1, 0, 2) */
419
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
421
brw_ADD(p, c->reg.destination_indices,
422
c->reg.destination_indices, get_element_ud(c->reg.SVBI, 0));
424
/* For each vertex, generate code to output each varying using the
425
* appropriate binding table entry.
427
for (vertex = 0; vertex < num_verts; ++vertex) {
428
/* Set up the correct destination index for this vertex */
429
brw_MOV(p, get_element_ud(c->reg.header, 5),
430
get_element_ud(c->reg.destination_indices, vertex));
432
for (binding = 0; binding < key->num_transform_feedback_bindings;
434
unsigned char vert_result =
435
key->transform_feedback_bindings[binding];
436
unsigned char slot = c->vue_map.vert_result_to_slot[vert_result];
437
/* From the Sandybridge PRM, Volume 2, Part 1, Section 4.5.1:
439
* "Prior to End of Thread with a URB_WRITE, the kernel must
440
* ensure that all writes are complete by sending the final
441
* write as a committed write."
444
binding == key->num_transform_feedback_bindings - 1 &&
445
vertex == num_verts - 1;
446
struct brw_reg vertex_slot = c->reg.vertex[vertex];
447
vertex_slot.nr += slot / 2;
448
vertex_slot.subnr = (slot % 2) * 16;
449
/* gl_PointSize is stored in VERT_RESULT_PSIZ.w. */
450
vertex_slot.dw1.bits.swizzle = vert_result == VERT_RESULT_PSIZ
451
? BRW_SWIZZLE_WWWW : key->transform_feedback_swizzles[binding];
452
brw_set_access_mode(p, BRW_ALIGN_16);
453
brw_MOV(p, stride(c->reg.header, 4, 4, 1),
454
retype(vertex_slot, BRW_REGISTER_TYPE_UD));
455
brw_set_access_mode(p, BRW_ALIGN_1);
457
final_write ? c->reg.temp : brw_null_reg(), /* dest */
459
c->reg.header, /* src0 */
460
SURF_INDEX_SOL_BINDING(binding), /* binding_table_index */
461
final_write); /* send_commit_msg */
466
/* Now, reinitialize the header register from R0 to restore the parts of
467
* the register that we overwrote while streaming out transform feedback
470
brw_gs_initialize_header(c);
472
/* Finally, wait for the write commit to occur so that we can proceed to
473
* other things safely.
475
* From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
477
* The write commit does not modify the destination register, but
478
* merely clears the dependency associated with the destination
479
* register. Thus, a simple “mov” instruction using the register as a
480
* source is sufficient to wait for the write commit to occur.
482
brw_MOV(p, c->reg.temp, c->reg.temp);
485
brw_gs_ff_sync(c, 1);
487
/* If RASTERIZER_DISCARD is enabled, we have nothing further to do, so
488
* release the URB that was just allocated, and terminate the thread.
490
if (key->rasterizer_discard) {
495
brw_gs_overwrite_header_dw2_from_r0(c);
498
brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_START | URB_WRITE_PRIM_END);
499
brw_gs_emit_vue(c, c->reg.vertex[0], true);
502
brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_START);
503
brw_gs_emit_vue(c, c->reg.vertex[0], false);
504
brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_END - URB_WRITE_PRIM_START);
505
brw_gs_emit_vue(c, c->reg.vertex[1], true);
508
if (check_edge_flags) {
509
/* Only emit vertices 0 and 1 if this is the first triangle of the
510
* polygon. Otherwise they are redundant.
512
brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
513
brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
514
get_element_ud(c->reg.R0, 2),
515
brw_imm_ud(BRW_GS_EDGE_INDICATOR_0));
516
brw_IF(p, BRW_EXECUTE_1);
518
brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_START);
519
brw_gs_emit_vue(c, c->reg.vertex[0], false);
520
brw_gs_offset_header_dw2(c, -URB_WRITE_PRIM_START);
521
brw_gs_emit_vue(c, c->reg.vertex[1], false);
522
if (check_edge_flags) {
524
/* Only emit vertex 2 in PRIM_END mode if this is the last triangle
525
* of the polygon. Otherwise leave the primitive incomplete because
526
* there are more polygon vertices coming.
528
brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
529
brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
530
get_element_ud(c->reg.R0, 2),
531
brw_imm_ud(BRW_GS_EDGE_INDICATOR_1));
532
brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
534
brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_END);
535
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
536
brw_gs_emit_vue(c, c->reg.vertex[2], true);