2
* Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
3
* Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
4
* Copyright (c) 1999-2003 by Hewlett-Packard Company. All rights reserved.
7
* THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
8
* OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
10
* Permission is hereby granted to use or copy this program
11
* for any purpose, provided the above notices are retained on all copies.
12
* Permission to modify the code and to distribute modified code is granted,
13
* provided the above notices are retained, and a notice that the code was
14
* modified is included with the above copyright notice.
18
#include "../read_ordered.h"
20
#include "../test_and_set_t_is_ao_t.h" /* Probably suboptimal */
22
/* NEC LE-IT: ARMv6 is the first architecture providing support for simple LL/SC
23
* A data memory barrier must be raised via CP15 command (see documentation).
25
* ARMv7 is compatible to ARMv6 but has a simpler command for issuing a
26
* memory barrier (DMB). Raising it via CP15 should still work as told me by the
27
* support engineers. If it turns out to be much quicker than we should implement
28
* custom code for ARMv7 using the asm { dmb } command.
30
* If only a single processor is used, we can define AO_UNIPROCESSOR
31
* and do not need to access CP15 for ensuring a DMB
34
/* NEC LE-IT: gcc has no way to easily check the arm architecture
35
* but defines only one of __ARM_ARCH_x__ to be true */
36
#if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_7__)
40
#ifndef AO_UNIPROCESSOR
41
/* issue an data memory barrier (keeps ordering of memory transactions */
42
/* before and after this operation) */
44
__asm__ __volatile__("mcr p15,0,%0,c7,c10,5" :"=&r"(dest) : : "memory");
48
#define AO_HAVE_nop_full
50
/* NEC LE-IT: AO_t load is simple reading */
52
AO_load(volatile AO_t *addr)
54
/* Cast away the volatile for architectures like IA64 where */
55
/* volatile adds barrier semantics. */
56
return (*(AO_t *)addr);
60
/* NEC LE-IT: atomic "store" - according to ARM documentation this is
61
* the only safe way to set variables also used in LL/SC environment.
62
* A direct write won't be recognized by the LL/SC construct on the _same_ CPU.
63
* Support engineers response for behaviour of ARMv6:
66
===================================
69
-----------------------------------
73
-----------------------------------
77
-----------------------------------
79
* ARMv7 behaves similar, see documentation CortexA8 TRM, point 8.5
81
* HB: I think this is only a problem if interrupt handlers do not clear
82
* the reservation, as they almost certainly should. Probably change this back
85
AO_INLINE void AO_store(volatile AO_t *addr, AO_t value)
89
__asm__ __volatile__("@AO_store\n"
91
" strex %0, %2, [%1]\n"
95
: "r" (addr), "r"(value)
100
/* NEC LE-IT: replace the SWAP as recommended by ARM:
102
"Applies to: ARM11 Cores
103
Though the SWP instruction will still work with ARM V6 cores, it is
104
recommended to use the new V6 synchronization instructions. The SWP
105
instruction produces ‘locked’ read and write accesses which are atomic,
106
i.e. another operation cannot be done between these locked accesses which
107
ties up external bus (AHB,AXI) bandwidth and can increase worst case
108
interrupt latencies. LDREX,STREX are more flexible, other instructions can
109
be done between the LDREX and STREX accesses.
113
AO_test_and_set(volatile AO_TS_t *addr) {
118
__asm__ __volatile__("@AO_test_and_set\n"
119
"1: ldrex %0, [%2]\n"
120
" strex %1, %3, [%2]\n"
123
: "=&r"(oldval),"=&r"(tmp)
130
#define AO_HAVE_test_and_set
132
/* NEC LE-IT: fetch and add for ARMv6 */
134
AO_fetch_and_add(volatile AO_t *p, AO_t incr)
136
unsigned long tmp,tmp2;
139
__asm__ __volatile__("@AO_fetch_and_add\n"
140
"1: ldrex %0, [%4]\n" /* get original */
141
" add %2, %3, %0\n" /* sum up */
142
" strex %1, %2, [%4]\n" /* store them */
145
: "=&r"(result),"=&r"(tmp),"=&r"(tmp2)
152
#define AO_HAVE_fetch_and_add
154
/* NEC LE-IT: fetch and add1 for ARMv6 */
156
AO_fetch_and_add1(volatile AO_t *p)
158
unsigned long tmp,tmp2;
161
__asm__ __volatile__("@AO_fetch_and_add1\n"
162
"1: ldrex %0, [%3]\n" /* get original */
163
" add %1, %0, #1\n" /* increment */
164
" strex %2, %1, [%3]\n" /* store them */
167
: "=&r"(result), "=&r"(tmp), "=&r"(tmp2)
174
#define AO_HAVE_fetch_and_add1
176
/* NEC LE-IT: fetch and sub for ARMv6 */
178
AO_fetch_and_sub1(volatile AO_t *p)
180
unsigned long tmp,tmp2;
183
__asm__ __volatile__("@ AO_fetch_and_sub1\n"
184
"1: ldrex %0, [%3]\n" /* get original */
185
" sub %1, %0, #1\n" /* increment */
186
" strex %2, %1, [%3]\n" /* store them */
189
: "=&r"(result), "=&r"(tmp), "=&r"(tmp2)
196
#define AO_HAVE_fetch_and_sub1
198
/* NEC LE-IT: compare and swap */
199
/* Returns nonzero if the comparison succeeded. */
201
AO_compare_and_swap(volatile AO_t *addr,
202
AO_t old_val, AO_t new_val)
206
__asm__ __volatile__("@ AO_compare_and_swap\n"
207
"1: ldrex %1, [%2]\n" /* get original */
208
" mov %0, #2\n" /* store a flag */
209
" teq %1, %3\n" /* see if match */
210
" strexeq %0, %4, [%2]\n" /* store new one if matched */
212
" beq 1b\n" /* if update failed, repeat */
213
" eor %0, %0, #2\n" /* if succeded, return 2, else 0 */
214
: "=&r"(result), "=&r"(tmp)
215
: "r"(addr), "r"(old_val), "r"(new_val)
220
#define AO_HAVE_compare_and_swap
223
/* pre ARMv6 architecures ... */
225
/* I found a slide set that, if I read it correctly, claims that */
226
/* Loads followed by either a Load or Store are ordered, but nothing */
228
/* It appears that SWP is the only simple memory barrier. */
229
#include "../all_atomic_load_store.h"
231
AO_INLINE AO_TS_VAL_t
232
AO_test_and_set_full(volatile AO_TS_t *addr) {
234
/* SWP on ARM is very similar to XCHG on x86. */
235
/* The first operand is the result, the second the value */
236
/* to be stored. Both registers must be different from addr. */
237
/* Make the address operand an early clobber output so it */
238
/* doesn't overlap with the other operands. The early clobber*/
239
/* on oldval is neccessary to prevent the compiler allocating */
240
/* them to the same register if they are both unused. */
241
__asm__ __volatile__("swp %0, %2, [%3]"
242
: "=&r"(oldval), "=&r"(addr)
248
#define AO_HAVE_test_and_set_full
250
#endif // __ARM_ARCH_x
added
removed
libatomic_ops-1.2/src/atomic_ops/sysdeps/gcc/arm.h
