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* Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
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* Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
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* Copyright (c) 1999-2003 by Hewlett-Packard Company. All rights reserved.
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* THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
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* OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
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* Permission is hereby granted to use or copy this program
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* for any purpose, provided the above notices are retained on all copies.
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* Permission to modify the code and to distribute modified code is granted,
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* provided the above notices are retained, and a notice that the code was
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* modified is included with the above copyright notice.
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* Some of the machine specific code was borrowed from our GC distribution.
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/* The following really assume we have a 486 or better. Unfortunately */
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/* gcc doesn't define a suitable feature test macro based on command */
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/* We should perhaps test dynamically. */
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#include "../all_aligned_atomic_load_store.h"
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/* Real X86 implementations, except for some old WinChips, appear */
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/* to enforce ordering between memory operations, EXCEPT that a later */
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/* read can pass earlier writes, presumably due to the visible */
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/* presence of store buffers. */
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/* We ignore both the WinChips, and the fact that the official specs */
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/* seem to be much weaker (and arguably too weak to be usable). */
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#include "../ordered_except_wr.h"
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#include "../test_and_set_t_is_char.h"
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#include "../standard_ao_double_t.h"
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#if defined(AO_USE_PENTIUM4_INSTRS)
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__asm__ __volatile__("mfence" : : : "memory");
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#define AO_HAVE_nop_full
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/* We could use the cpuid instruction. But that seems to be slower */
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/* than the default implementation based on test_and_set_full. Thus */
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/* we omit that bit of misinformation here. */
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/* As far as we can tell, the lfence and sfence instructions are not */
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/* currently needed or useful for cached memory accesses. */
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/* Really only works for 486 and later */
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AO_fetch_and_add_full (volatile AO_t *p, AO_t incr)
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__asm__ __volatile__ ("lock; xaddq %0, %1" :
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"=r" (result), "=m" (*p) : "0" (incr), "m" (*p)
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#define AO_HAVE_fetch_and_add_full
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AO_INLINE unsigned char
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AO_char_fetch_and_add_full (volatile unsigned char *p, unsigned char incr)
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__asm__ __volatile__ ("lock; xaddb %0, %1" :
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"=q" (result), "=m" (*p) : "0" (incr), "m" (*p)
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#define AO_HAVE_char_fetch_and_add_full
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AO_INLINE unsigned short
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AO_short_fetch_and_add_full (volatile unsigned short *p, unsigned short incr)
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unsigned short result;
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__asm__ __volatile__ ("lock; xaddw %0, %1" :
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"=r" (result), "=m" (*p) : "0" (incr), "m" (*p)
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#define AO_HAVE_short_fetch_and_add_full
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AO_INLINE unsigned short
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AO_int_fetch_and_add_full (volatile unsigned int *p, unsigned int incr)
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__asm__ __volatile__ ("lock; xaddl %0, %1" :
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"=r" (result), "=m" (*p) : "0" (incr), "m" (*p)
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#define AO_HAVE_int_fetch_and_add_full
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/* Really only works for 486 and later */
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AO_or_full (volatile AO_t *p, AO_t incr)
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__asm__ __volatile__ ("lock; orq %1, %0" :
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"=m" (*p) : "r" (incr), "m" (*p) : "memory");
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#define AO_HAVE_or_full
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AO_INLINE AO_TS_VAL_t
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AO_test_and_set_full(volatile AO_TS_t *addr)
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unsigned char oldval;
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/* Note: the "xchg" instruction does not need a "lock" prefix */
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__asm__ __volatile__("xchgb %0, %1"
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: "=q"(oldval), "=m"(*addr)
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: "0"(0xff), "m"(*addr) : "memory");
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return (AO_TS_VAL_t)oldval;
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#define AO_HAVE_test_and_set_full
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/* Returns nonzero if the comparison succeeded. */
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AO_compare_and_swap_full(volatile AO_t *addr,
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AO_t old, AO_t new_val)
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__asm__ __volatile__("lock; cmpxchgq %3, %0; setz %1"
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: "=m"(*addr), "=q"(result)
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: "m"(*addr), "r" (new_val), "a"(old) : "memory");
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#define AO_HAVE_compare_and_swap_full
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#ifdef AO_CMPXCHG16B_AVAILABLE
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/* NEC LE-IT: older AMD Opterons are missing this instruction.
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* On these machines SIGILL will be thrown. Define AO_CASDOUBLE_MISSING
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* to have an emulated (lock based) version available */
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/* HB: Changed this to not define either by default. There are
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* enough machines and tool chains around on which cmpxchg16b
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* doesn't work. And the emulation is unsafe by our usual rules.
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* Hoewever both are clearly useful in certain cases.
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AO_compare_double_and_swap_double_full(volatile AO_double_t *addr,
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AO_t old_val1, AO_t old_val2,
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AO_t new_val1, AO_t new_val2)
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__asm__ __volatile__("lock; cmpxchg16b %0; setz %1"
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: "=m"(*addr), "=q"(result)
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"b" (new_val2) : "memory");
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#define AO_HAVE_compare_double_and_swap_double_full
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/* this one provides spinlock based emulation of CAS implemented in */
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/* atomic_ops.c. We probably do not want to do this here, since it is */
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/* not attomic with respect to other kinds of updates of *addr. On the */
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/* other hand, this may be a useful facility on occasion. */
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#ifdef AO_WEAK_DOUBLE_CAS_EMULATION
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int AO_compare_double_and_swap_double_emulation(volatile AO_double_t *addr,
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AO_t old_val1, AO_t old_val2,
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AO_t new_val1, AO_t new_val2);
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AO_compare_double_and_swap_double_full(volatile AO_double_t *addr,
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AO_t old_val1, AO_t old_val2,
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AO_t new_val1, AO_t new_val2)
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return AO_compare_double_and_swap_double_emulation(addr,
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#define AO_HAVE_compare_double_and_swap_double_full
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#endif /* AO_WEAK_DOUBLE_CAS_EMULATION */
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#endif /* AO_CMPXCHG16B_AVAILABLE */
added
removed
libatomic_ops-1.2/src/atomic_ops/sysdeps/gcc/x86_64.h
