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* Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
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* Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
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* Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P.
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* THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
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* OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
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* Permission is hereby granted to use or copy this program
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* for any purpose, provided the above notices are retained on all copies.
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* Permission to modify the code and to distribute modified code is granted,
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* provided the above notices are retained, and a notice that the code was
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* modified is included with the above copyright notice.
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/* FIXME. Incomplete. No support for 64 bits. */
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/* Memory model documented at http://www-106.ibm.com/developerworks/ */
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/* eserver/articles/archguide.html and (clearer) */
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/* http://www-106.ibm.com/developerworks/eserver/articles/powerpc.html. */
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/* There appears to be no implicit ordering between any kind of */
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/* independent memory references. */
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/* Architecture enforces some ordering based on control dependence. */
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/* I don't know if that could help. */
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/* Data-dependent loads are always ordered. */
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/* Based on the above references, eieio is intended for use on */
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/* uncached memory, which we don't support. It does not order loads */
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/* from cached memory. */
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/* Thanks to Maged Michael, Doug Lea, and Roger Hoover for helping to */
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/* track some of this down and correcting my misunderstandings. -HB */
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#include "../all_aligned_atomic_load_store.h"
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#include "../test_and_set_t_is_ao_t.h"
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/* There seems to be no byte equivalent of lwarx, so this */
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/* may really be what we want, at least in the 32-bit case. */
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__asm__ __volatile__("sync" : : : "memory");
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#define AO_HAVE_nop_full
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/* lwsync apparently works for everything but a StoreLoad barrier. */
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__asm__ __volatile__("lwsync" : : : "memory");
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#define AO_nop_write() AO_lwsync()
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#define AO_HAVE_nop_write
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#define AO_nop_read() AO_lwsync()
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#define AO_HAVE_nop_read
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/* We explicitly specify load_acquire, since it is important, and can */
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/* be implemented relatively cheaply. It could be implemented */
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/* with an ordinary load followed by a lwsync. But the general wisdom */
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/* seems to be that a data dependent branch followed by an isync is */
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/* cheaper. And the documentation is fairly explicit that this also */
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/* has acquire semantics. */
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/* ppc64 uses ld not lwz */
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#if defined(__powerpc64__) || defined(__ppc64__) || defined(__64BIT__)
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AO_load_acquire(volatile AO_t *addr)
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/* FIXME: We should get gcc to allocate one of the condition */
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/* registers. I always got "impossible constraint" when I */
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/* tried the "y" constraint. */
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__asm__ __volatile__ (
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: "m"(*addr) : "memory", "cc");
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AO_load_acquire(volatile AO_t *addr)
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/* FIXME: We should get gcc to allocate one of the condition */
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/* registers. I always got "impossible constraint" when I */
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/* tried the "y" constraint. */
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__asm__ __volatile__ (
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: "m"(*addr) : "memory", "cc");
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#define AO_HAVE_load_acquire
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/* We explicitly specify store_release, since it relies */
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/* on the fact that lwsync is also a LoadStore barrier. */
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AO_store_release(volatile AO_t *addr, AO_t value)
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#define AO_HAVE_load_acquire
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/* This is similar to the code in the garbage collector. Deleting */
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/* this and having it synthesized from compare_and_swap would probably */
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/* only cost us a load immediate instruction. */
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#if defined(__powerpc64__) || defined(__ppc64__) || defined(__64BIT__)
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/* Completely untested. And we should be using smaller objects anyway. */
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AO_INLINE AO_TS_VAL_t
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AO_test_and_set(volatile AO_TS_t *addr) {
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unsigned long oldval;
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unsigned long temp = 1; /* locked value */
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__asm__ __volatile__(
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"1:ldarx %0,0,%1\n" /* load and reserve */
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"cmpdi %0, 0\n" /* if load is */
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"bne 2f\n" /* non-zero, return already set */
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"stdcx. %2,0,%1\n" /* else store conditional */
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"bne- 1b\n" /* retry if lost reservation */
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"2:\n" /* oldval is zero if we set */
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: "r"(addr), "r"(temp)
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return (AO_TS_VAL_t)oldval;
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AO_INLINE AO_TS_VAL_t
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AO_test_and_set(volatile AO_TS_t *addr) {
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int temp = 1; /* locked value */
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__asm__ __volatile__(
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"1:lwarx %0,0,%1\n" /* load and reserve */
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"cmpwi %0, 0\n" /* if load is */
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"bne 2f\n" /* non-zero, return already set */
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"stwcx. %2,0,%1\n" /* else store conditional */
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"bne- 1b\n" /* retry if lost reservation */
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"2:\n" /* oldval is zero if we set */
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: "r"(addr), "r"(temp)
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return (AO_TS_VAL_t)oldval;
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#define AO_have_test_and_set
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AO_INLINE AO_TS_VAL_t
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AO_test_and_set_acquire(volatile AO_TS_t *addr) {
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AO_TS_VAL_t result = AO_test_and_set(addr);
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#define AO_HAVE_test_and_set_acquire
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AO_INLINE AO_TS_VAL_t
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AO_test_and_set_release(volatile AO_TS_t *addr) {
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return AO_test_and_set(addr);
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#define AO_HAVE_test_and_set_release
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AO_INLINE AO_TS_VAL_t
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AO_test_and_set_full(volatile AO_TS_t *addr) {
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result = AO_test_and_set(addr);
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#define AO_HAVE_test_and_set_full
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#if defined(__powerpc64__) || defined(__ppc64__) || defined(__64BIT__)
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/* FIXME: Completely untested. */
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AO_compare_and_swap(volatile AO_t *addr, AO_t old, AO_t new_val) {
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__asm__ __volatile__(
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"1:ldarx %0,0,%2\n" /* load and reserve */
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"cmpd %0, %4\n" /* if load is not equal to */
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"bne 2f\n" /* old, fail */
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"stdcx. %3,0,%2\n" /* else store conditional */
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"bne- 1b\n" /* retry if lost reservation */
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"li %1,1\n" /* result = 1; */
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: "=&r"(oldval), "=&r"(result)
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: "r"(addr), "r"(new_val), "r"(old), "1"(result)
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AO_compare_and_swap(volatile AO_t *addr, AO_t old, AO_t new_val) {
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__asm__ __volatile__(
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"1:lwarx %0,0,%2\n" /* load and reserve */
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"cmpw %0, %4\n" /* if load is not equal to */
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"bne 2f\n" /* old, fail */
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"stwcx. %3,0,%2\n" /* else store conditional */
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"bne- 1b\n" /* retry if lost reservation */
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"li %1,1\n" /* result = 1; */
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: "=&r"(oldval), "=&r"(result)
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: "r"(addr), "r"(new_val), "r"(old), "1"(result)
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#define AO_HAVE_compare_and_swap
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AO_compare_and_swap_acquire(volatile AO_t *addr, AO_t old, AO_t new_val) {
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int result = AO_compare_and_swap(addr, old, new_val);
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#define AO_HAVE_compare_and_swap_acquire
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AO_compare_and_swap_release(volatile AO_t *addr, AO_t old, AO_t new_val) {
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return AO_compare_and_swap(addr, old, new_val);
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#define AO_HAVE_compare_and_swap_release
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AO_compare_and_swap_full(volatile AO_t *addr, AO_t old, AO_t new_val) {
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result = AO_compare_and_swap(addr, old, new_val);
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#define AO_HAVE_compare_and_swap_full
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/* FIXME: We should also implement fetch_and_add and or primitives */
added
removed
libatomic_ops-1.2/src/atomic_ops/sysdeps/gcc/powerpc.h
