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//=======================================================================
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// T1/E1 PCI card with failover DS1x1F card Driver
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// Ver: 2.14 Date: 17.Jan.2007
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// Mark Spencer <markster@digium.com>
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// Matthew Fredrickson <creslin@digium.com>
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// William Meadows <wmeadows@digium.com>
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// Copyright (c)2006,2007 TCDG Corp.
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// All rights reserved.
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// http://www.tc-dg.net
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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//=======================================================================
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/spinlock.h>
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#ifdef STANDALONE_ZAPATA
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#include <linux/zaptel.h>
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#define WC_MAX_CARDS 32
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#define OFS_FALC 0x0000 // pci address space offset for FALC registers 256 * 32 bit words (only 8 LSB used)
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#define OFS_TDM_WR 0x0800 // pci address space offset for TDM media shift register buffers 8 * 32 bit words
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#define OFS_TDM_RD 0x0900 // pci address space offset for TDM media shift register buffers 8 * 32 bit words
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#define OFS_CTRL 0x1000 // pci address space offset for card control register 1 * 32 bit
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#define OFS_CLK 0x1004 // pci address space offset for card clock / h.100 register 1 * 32 bit
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#define FLAG_STARTED 0x01
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#define FLAG_SENDINGYELLOW 0x04
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#define MODE_SW -1 // mode controlled by DIP switch
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#define MODE_T1 0x01 // T1 mode bit.0 = T1
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#define MODE_E1 0x02 // E1 mode bit.1 = E1
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#define MODE_UE1 0x82 // unchannelized E1 bit.7 = unchannelized
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#define MODE_J1 0x41 // J1 mode bit.6 = j1mode
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#define DS1_SET_REL 7 // new MAINT commands for controlling the bypass relay and monitoring, hot-standby
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#define DS1_SET_RXMON 9
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#define DS1_CLR_RXMON 10
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#define DS1_SET_TXEN 11
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#define DS1_CLR_TXEN 12
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//======================================= Control register bit definitions ================================
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#define CTRL_LOFF 0x0000 // All LED off
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#define CTRL_LGRN 0x0001 // Green LED control bit
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#define CTRL_LRED 0x0002 // Red LED control bit
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#define CTRL_REL 0x0004 // bypass relay L = bypass H = normal operation
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#define CTRL_TEST 0x0008 // relay presence test bit L = normal operation H= presence test
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#define CTRL_FRST 0x0010 // Falc reset bit L = normal operation H = Falc Reset
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#define CTRL_INTA 0x0100 // Interrupt acknowledge bit writing a '1' resets IRQ and IRM
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#define CTRL_IRQ 0x0100 // Interrupt request bit
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#define CTRL_IRM 0x0400 // Interrupt missed bit = previous interrupt has not yet been serviced when new one was triggered
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#define CTRL_RELI 0x0800 // relay presence bit H = no relay L = relay present (valid only when CTRL_TEST = H)
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#define CTRL_SW1 0x1000 // DIP switch #1
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#define CTRL_SW2 0x2000 // DIP switch #2
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#define CTRL_SW3 0x4000 // DIP switch #3
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#define CTRL_SW4 0x8000 // DIP switch #4
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//==================================== FALC-56 PEF-2256 register definitions ===============================
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#define FR_CEC1L 0x54
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#define FR_CEC1H 0x55
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#define FR_CEC2L 0x58
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#define FR_CEC2H 0x59
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#define FR_CEC3L 0x5a
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#define FR_CEC3H 0x5b
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#define FR_RSA6S 0x61
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#define FR_CMDR2 0x87
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#define FR_CMDR3 0x88
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#define FR_CMDR4 0x89
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#define FR_MODE2 0x8e
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#define FR_MODE3 0x8f
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#define FR_RSIS2 0x99
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#define FR_RSIS3 0x9b
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#define FR_XFIFO2 0x9c
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#define FR_RFIFO2 0x9c
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#define FR_XFIFO3 0x9e
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#define FR_RFIFO3 0x9e
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#define FR_TSBS1 0xa1
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#define FR_TSBS2 0xa2
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#define FR_TSBS3 0xa3
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//========================================================================================================
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unsigned int pci[NUM_PCI];
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unsigned char regs[NUM_REGS];
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#define WCT4_GET_REGS _IOW (ZT_CODE, 60, struct t4_regs)
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static int clrtab[] = {0x80,0x40,0x20,0x10,0x8,0x4,0x2,0x1};
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static char name[] = {"ds1x1f"};
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int spanflags; // Span flags
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unsigned char txsigs[16]; // Copy of tx sig registers
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int alarmcount; // How much red alarm we've seen
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unsigned int intcount;
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int prescaler; // interrupt divider
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unsigned char ledtestreg;
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void * cnaddr; // PCI and driver related parameters
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unsigned long iostart;
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unsigned long cnstart;
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struct resource * cres;
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struct resource * ires;
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unsigned char txchunkptr; // pointer for rd/wr audiosamples
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unsigned char rxchunkptr;
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unsigned char ec_chunk1[32][ZT_CHUNKSIZE]; // echocanceller memory buffers
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unsigned char ec_chunk2[32][ZT_CHUNKSIZE];
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struct zt_span span; // Span
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struct zt_chan chans[32]; // Channels
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// module paramter variables
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static int debug = 0; // defines debug modes 0,1,2
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static int cardmode = -1; // forces card into T1, E1, J1, UE1 mode , -1 = use DIP switches
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static int alarmdebounce = 0;
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static int loopback = 0;
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static int frames = -1; // sets the size of the cards framebuffer 1-8 frames (preferred are 1,2,4,8)
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static int extclk = -1; // controls the clock synchronization via H.100 bus connector
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static int monitor = 0; // monitor = 3 puts the card in a Hi-Z mode and enabling it to monitor T1/E1 traffic
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static struct t1 *cards[WC_MAX_CARDS];
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static inline void start_alarm(struct t1 *wc)
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static int ds1_open(struct zt_chan *chan)
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struct t1 *wc = chan->pvt;
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try_module_get(THIS_MODULE);
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//-------------------------------------------------------------------------------------------------------------------------------------------
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static inline unsigned int led_write_reg(struct t1 *wc, unsigned int val) // write to the cards 32 bit control register
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x = (ioread32(wc->ioaddr + OFS_CTRL) & 0xfc) | (val & 0x03); // combine LED content with all other register data
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iowrite32(x, wc->ioaddr + OFS_CTRL); // write back register content
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//-------------------------------------------------------------------------------------------------------------------------------------------
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static inline unsigned int ctrl_set_reg(struct t1 *wc, unsigned int val) // set bits in control register
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x = (ioread32(wc->ioaddr + OFS_CTRL) & 0xff) | val; // OR newcontent with all other register data
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iowrite32(x, wc->ioaddr + OFS_CTRL); // write back register content
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//-------------------------------------------------------------------------------------------------------------------------------------------
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static inline unsigned int ctrl_clr_reg(struct t1 *wc, unsigned int val) // clear bits in control register
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x = (ioread32(wc->ioaddr + OFS_CTRL) & 0xff) & (val ^ 0xff); // OR newcontent with all other register data
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iowrite32(x, wc->ioaddr + OFS_CTRL); // write back register content
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//-------------------------------------------------------------------------------------------------------------------------------------------
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static inline unsigned int ctrl_write_reg(struct t1 *wc, unsigned int val) // write to the cards 32 bit control register
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iowrite32(val, wc->ioaddr + OFS_CTRL); // write back register content
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//-------------------------------------------------------------------------------------------------------------------------------------------
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static inline unsigned int ctrl_read_reg(struct t1 *wc) // read control register
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return (ioread32(wc->ioaddr + OFS_CTRL)); // return content of control register
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//-------------------------------------------------------------------------------------------------------------------------------------------
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static inline unsigned int clk_write_reg(struct t1 *wc, unsigned int val) // write to the cards 32 bit clock/ h.100 bus register
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iowrite32(val, wc->ioaddr + OFS_CLK); // write back register content
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//-------------------------------------------------------------------------------------------------------------------------------------------
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static inline unsigned int clk_read_reg(struct t1 *wc) // read clock / h.100 bus register
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return (ioread32(wc->ioaddr + OFS_CLK)); // return content of control register
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//-------------------------------------------------------------------------------------------------------------------------------------------
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static inline unsigned int __t1_framer_in(struct t1 *wc, const unsigned int reg) // read a Falc framer register
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int loc = ((reg & 0x00ff) << 2) + OFS_FALC; // FALC registers are on doubleword boundaries
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return ((ioread32(wc->ioaddr + loc)) & 0xff); // return only the 8 lsb
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static inline unsigned int t1_framer_in(struct t1 *wc, const unsigned int addr) // spinlock wrapper
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spin_lock_irqsave(&wc->lock, flags);
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ret = __t1_framer_in(wc, addr);
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spin_unlock_irqrestore(&wc->lock, flags);
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static inline void __t1_framer_out(struct t1 *wc, const unsigned int reg, const unsigned int val) // write to Falc framer register
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int loc = ((reg & 0x00ff) << 2) + OFS_FALC; // FALC registers are on doubleword boundaries
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iowrite32(val, wc->ioaddr + loc); // write to register
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ret = (ioread32(wc->ioaddr + loc)) & 0xff; // for debugging read back register content
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if (ret == val) // check if write was successful
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printk("Wrote: %02x to Adr: %02x \n", val, reg); // and print on the console
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printk("Wrote: %02x to Adr: %02x but read back: %02x !!!\n", val, reg, ret); // print results on the console
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static inline void t1_framer_out(struct t1 *wc, const unsigned int addr, const unsigned int value) // spinlock wrapper
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spin_lock_irqsave(&wc->lock, flags);
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__t1_framer_out(wc, addr, value);
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spin_unlock_irqrestore(&wc->lock, flags);
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//-------------------------------------------------------------------------------------------------------------------------------------------
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static void ds1_release(struct t1 *wc)
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zt_unregister(&wc->span);
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printk("Freed a DS1x1F card\n");
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static int ds1_close(struct zt_chan *chan)
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struct t1 *wc = chan->pvt;
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module_put(THIS_MODULE);
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if (!wc->usecount) // If we're dead, release us now
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//----------------------------------------------------------------------------------------------------------------------------------------
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// HARDWARE INTERRUPT CONTROL Enable / Disable
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static void ds1_enable_interrupts(struct t1 *wc) // enable 8 kHz TDM interrupts from the pci card
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iowrite32(0x00000001, wc->cnaddr + 0x1ec); // enable internal interrupt
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ctrl_set_reg(wc, CTRL_INTA); // clear interrupt status bit
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printk("Enabled interrupts!\n");
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static void ds1_disable_interrupts(struct t1 *wc) // disable all interrupts from the card
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ctrl_set_reg(wc, CTRL_INTA); // clear interrupt status bit
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iowrite32(0x00000000, wc->cnaddr + 0x1ec); // disable internal interrupt
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printk("Disabled interrupts!\n");
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//----------------------------------------------------------------------------------------------------------------------------------------
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static void __ds1_set_clear(struct t1 *wc) // SELECT CLEAR CHANNEL MODE - FOR T1 ONLY
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for (i=0; i<8; i++) // go through channel 0-7
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if (wc->span.chans[i ].flags & ZT_FLAG_CLEAR) // check if this channel is marked Clear channel
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__t1_framer_out(wc, FR_CCB1, val); // write register CCB1
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for (i=0; i<8; i++) // go through channel 8-15
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if (wc->span.chans[i+ 8].flags & ZT_FLAG_CLEAR) // check if this channel is marked Clear channel
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__t1_framer_out(wc, FR_CCB2, val); // write register CCB2
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for (i=0; i<8; i++) // go through channel 16-23
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if (wc->span.chans[i+16].flags & ZT_FLAG_CLEAR) // check if this channel is marked Clear channel
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__t1_framer_out(wc, FR_CCB3, val); // write register CCB3
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//----------------------------------------------------------------------------------------------------------------------------------------
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static int ds1_ioctl(struct zt_chan *chan, unsigned int cmd, unsigned long data)
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for (x=0; x<NUM_PCI; x++)
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regs.pci[x] = (ioread32(wc->ioaddr + (x << 2)));
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for (x=0; x<NUM_REGS; x++)
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regs.regs[x] = t1_framer_in(wc, x);
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if (copy_to_user((struct t4_regs *)data, ®s, sizeof(regs)))
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case DS1_SET_REL: // Turn on failover relay - normal operation
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ctrl_set_reg (wc, CTRL_REL);
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case DS1_CLR_REL: // turn off failover relay - bypass
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ctrl_clr_reg (wc, CTRL_REL);
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case DS1_SET_RXMON: // Enable receiver Hi-Z monitor mode
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__t1_framer_out(wc, FR_LIM2,__t1_framer_in(wc, FR_LIM2) & 0xFD); // LIM2: turn off AS1
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case DS1_CLR_RXMON: // Set receiver to normal 100 Ohm impedance
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__t1_framer_out(wc, FR_LIM2,__t1_framer_in(wc, FR_LIM2) | 0x02); // LIM2: turn on AS1
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case DS1_SET_TXEN: // Enable transmitter - normal operation
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__t1_framer_out(wc, FR_LIM2,__t1_framer_in(wc, FR_XPM2) & 0xBF); // XPM2: turn on line drivers
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case DS1_CLR_TXEN: // Disable transmitter - set to Hi-Z
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__t1_framer_out(wc, FR_LIM2,__t1_framer_in(wc, FR_XPM2) | 0x40); // XPM2: turn off line drivers
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static int ds1_maint(struct zt_span *span, int cmd)
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struct t1 *wc = span->pvt;
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if (wc->spantype == MODE_E1)
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printk("XXX Turn off local and remote loops E1 XXX\n");
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case ZT_MAINT_LOCALLOOP:
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printk("XXX Turn on local loopback E1 XXX\n");
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case ZT_MAINT_REMOTELOOP:
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printk("XXX Turn on remote loopback E1 XXX\n");
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case ZT_MAINT_LOOPUP:
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printk("XXX Send loopup code E1 XXX\n");
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case ZT_MAINT_LOOPDOWN:
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printk("XXX Send loopdown code E1 XXX\n");
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case ZT_MAINT_LOOPSTOP:
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printk("XXX Stop sending loop codes E1 XXX\n");
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ctrl_set_reg (wc, CTRL_REL);
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printk("XXX Turn off E1 bypass XXX\n");
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ctrl_clr_reg (wc, CTRL_REL);
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printk("XXX Turn on E1 bypass XXX\n");
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printk("DS1x1F: Unknown E1 maintainance command: %d\n", cmd);
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printk("XXX Turn off local and remote loops T1 XXX\n");
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case ZT_MAINT_LOCALLOOP:
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printk("XXX Turn on local loop and no remote loop XXX\n");
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case ZT_MAINT_REMOTELOOP:
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printk("XXX Turn on remote loopup XXX\n");
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case ZT_MAINT_LOOPUP:
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t1_framer_out(wc, FR_FMR5, 0x50); /* FMR5: Nothing but RBS mode */
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case ZT_MAINT_LOOPDOWN:
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t1_framer_out(wc, FR_FMR5, 0x60); /* FMR5: Nothing but RBS mode */
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case ZT_MAINT_LOOPSTOP:
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t1_framer_out(wc, FR_FMR5, 0x40); /* FMR5: Nothing but RBS mode */
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ctrl_set_reg (wc, CTRL_REL);
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printk("XXX Turn off T1 bypass XXX\n");
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ctrl_clr_reg (wc, CTRL_REL);
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printk("XXX Turn on T1 bypass XXX\n");
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printk("DS1x1F: Unknown T1 maintainance command: %d\n", cmd);
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static int ds1_rbsbits(struct zt_chan *chan, int bits)
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struct t1 *wc = chan->pvt;
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printk("Setting CAS signalling bits to: %d for ch: %s\n", bits, chan->name);
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spin_lock_irqsave(&wc->lock, flags);
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if (wc->spantype == MODE_E1) // E1 CAS (R2) signalling
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if (chan->chanpos == 16) // channel 16 is the signalling channel even for CAS
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spin_unlock_irqrestore(&wc->lock, flags);
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return 0; // so leave it alone
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n = chan->chanpos - 1;
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if (chan->chanpos > 15) // move everything above channel 16 one down
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m = (n / 15) << 2; // we have to write one nibble with new bits
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c &= (0xf << m); // while keeping the other nibble as is
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c |= (bits & 0xf) << (4 - m);
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__t1_framer_out(wc,FR_XS2 + b,c); // In E1 mode XS1 is not used for CAS signalling
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else // T1 or J1 CAS mode
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if (wc->span.lineconfig & ZT_CONFIG_D4) // Old D4 framin selected
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n = chan->chanpos - 1;
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m = ((3 - (n % 4)) << 1); // D4 only uses 2 CAS bits per channel
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c &= ~(0x3 << m); // do the nibble thing
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c |= ((bits >> 2) & 0x3) << m;
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// output them to the chip */
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__t1_framer_out(wc,FR_XS1 + b ,c); // since there are only 2 bits per channel
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__t1_framer_out(wc,FR_XS6 + b ,c); // write them into the CAS registers twice
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if (wc->span.lineconfig & ZT_CONFIG_ESF) // ESF = CAS 4 bits per channel
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n = chan->chanpos - 1;
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m = ((n % 2) << 2); // do the nibble thing
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c |= (bits & 0xf) << (4 - m);
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// output them to the chip
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__t1_framer_out(wc,FR_XS1 + b,c); // write only once
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spin_unlock_irqrestore(&wc->lock, flags);
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printk("Finished setting CAS signalling bits\n");
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static void __t1_check_sigbits(struct t1 *wc) // read the current CAS bits from framerchip
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if (!(wc->span.flags & ZT_FLAG_RUNNING))
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if (wc->spantype == MODE_E1) // E1 CAS mode selected
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for (i = 0; i < 15; i++) // do this in 16 steps
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a = __t1_framer_in(wc, FR_RS2 + i); // RS1 is not used for CAS bits
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if (!(wc->span.chans[i+16].sig & ZT_SIG_CLEAR)) // get lower nibble = channel+16
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if (wc->span.chans[i+16].rxsig != rxs)
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zt_rbsbits(&wc->span.chans[i+16], rxs);
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rxs = (a >> 4) & 0xf; // get upper nibble = channel +0
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if (!(wc->span.chans[i].sig & ZT_SIG_CLEAR))
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if (wc->span.chans[i].rxsig != rxs)
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zt_rbsbits(&wc->span.chans[i], rxs);
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else // T1 or J1 mode selected
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if (wc->span.lineconfig & ZT_CONFIG_D4) // D4 framing selected
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{ // D4 uses only 2 CAS bits per channel
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for (i = 0; i < 24; i+=4) // do it in 6 steps
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a = __t1_framer_in(wc, FR_RS1 + (i>>2));
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rxs = (a & 0x3) << 2; // get bits.0 and .1 = channel +3
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if (!(wc->span.chans[i+3].sig & ZT_SIG_CLEAR))
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if (wc->span.chans[i+3].rxsig != rxs)
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zt_rbsbits(&wc->span.chans[i+3], rxs);
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rxs = (a & 0xc); // get bits.2 and .3 = channel +2
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if (!(wc->span.chans[i+2].sig & ZT_SIG_CLEAR))
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if (wc->span.chans[i+2].rxsig != rxs)
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zt_rbsbits(&wc->span.chans[i+2], rxs);
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rxs = (a >> 2) & 0xc; // get bits.4 and .5 = channel +1
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if (!(wc->span.chans[i+1].sig & ZT_SIG_CLEAR))
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if (wc->span.chans[i+1].rxsig != rxs)
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zt_rbsbits(&wc->span.chans[i+1], rxs);
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rxs = (a >> 4) & 0xc; // get bits.6 and .7 = channel +0
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if (!(wc->span.chans[i].sig & ZT_SIG_CLEAR))
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if (wc->span.chans[i].rxsig != rxs)
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zt_rbsbits(&wc->span.chans[i], rxs);
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else // ESF framing uses 4 CAS bits per channel
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for (i = 0; i < 24; i+=2) // do this in 12 steps
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a = __t1_framer_in(wc, FR_RS1 + (i>>1));
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rxs = (a & 0xf); // get lower nibble = channel +1
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if (!(wc->span.chans[i+1].sig & ZT_SIG_CLEAR))
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if (wc->span.chans[i+1].rxsig != rxs)
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zt_rbsbits(&wc->span.chans[i+1], rxs);
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rxs = (a >> 4) & 0xf; // get upper nibble = channel +0
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if (!(wc->span.chans[i].sig & ZT_SIG_CLEAR))
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if (wc->span.chans[i].rxsig != rxs)
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zt_rbsbits(&wc->span.chans[i], rxs);
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static void t4_serial_setup(struct t1 *wc)
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switch (wc->spantype)
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case MODE_E1: // E1 mode
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printk("DS1x1F: Setting global parameters for E1 \n");
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case MODE_UE1: // NEW - Unframed E1 mode
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printk("DS1x1F: Setting global parameters for Unchannelized E1 \n");
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case MODE_J1: // J1 mode
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printk("DS1x1F: Setting global parameters for J1 \n");
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default: // All others default to T1
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printk("DS1x1F: Setting global parameters for T1 \n");
910
RC = 0x000; // Rt = 4 x 125 ns cycle
911
XC = 0x004; // Xt = 0 x 125 nS cycles
913
t1_framer_out(wc, FR_GPC1, 0xe0); // GPC1: Multiplex mode enabled, FSC is output, active low, RCLK from channel 0
914
t1_framer_out(wc, FR_IPC, 0x05); // IPC: Interrupt push/pull active low
916
t1_framer_out(wc, FR_GCM1, 0x66);
917
t1_framer_out(wc, FR_GCM2, 0x0e);
918
t1_framer_out(wc, FR_GCM3, 0x3f);
919
t1_framer_out(wc, FR_GCM4, 0x0f);
920
t1_framer_out(wc, FR_GCM5, 0x04);
921
t1_framer_out(wc, FR_GCM6, 0x3c);
922
t1_framer_out(wc, FR_GCM7, 0x9c);
923
t1_framer_out(wc, FR_GCM8, 0x90);
925
t1_framer_out(wc, FR_GCR, 0x40); // GCR: Interrupt on Activation/Deactivation of AIX, LOS
926
t1_framer_out(wc, FR_SIC1, 0x82); // SIC1: 2.048 Mhz clock/bus, double buffer receive / transmit, byte interleaved
927
t1_framer_out(wc, FR_SIC2, 0x00); // SIC2: No FFS, no center receive eliastic buffer, phase 0
928
t1_framer_out(wc, FR_SIC3, 0x08); // SIC3: Edges for capture tx latches with rising edge / rx changes with falling edge
929
t1_framer_out(wc, FR_CMR1, 0x30); // CMR1: RCLK is at 8.192 Mhz dejittered
930
t1_framer_out(wc, FR_CMR2, 0x25); // CMR2: sync and clock for tx and rx provided by FALC
932
t1_framer_out(wc, FR_XC0, 0x00 | ((XC >> 8) & 0x07)); // XC0: Normal operation of Sa-bits
933
t1_framer_out(wc, FR_XC1, XC & 0xff); // XC1: tx offset
935
t1_framer_out(wc, FR_RC0, 0x00 | ((RC >> 8) & 0x07)); // RC0: rx offset
936
t1_framer_out(wc, FR_RC1, RC & 0xff); // RC1:
938
// ------------- Configure ports ---------------
939
t1_framer_out(wc, FR_PC1, 0x10); // PC1: FMR/SPYX output/input on RPA/XPA
940
t1_framer_out(wc, FR_PC2, 0x65); // PC2: unused
941
t1_framer_out(wc, FR_PC3, 0x65); // PC3: unused
942
t1_framer_out(wc, FR_PC4, 0x35); // PC4: unused
943
t1_framer_out(wc, FR_PC5, 0x33); // PC5: XMFS active low, SCLKR is input, RCLK is output
944
t1_framer_out(wc, FR_PC6, 0x01); // PC6: CLK1 is Tx Clock output, CLK2 is 2.048 Mhz from DCO-R
946
t1_framer_out(wc, FR_LCR1, 0x00); // Clear LCR1
948
printk("DS1x1F: Successfully initialized card\n");
952
static void __t1_configure_t1(struct t1 *wc, int lineconfig, int txlevel)
954
char *mode, *frame, *lcode;
958
__t1_framer_out(wc, FR_FMR1, 0xbc); // FMR1: Mode 1, T1 mode, CRC on for ESF, 2.048 Mhz system data rate, no XAIS
960
switch (monitor) // module parameter monitor
963
as1 = 0x00; // Tx = normal / Rx = Hi-Z
968
as1 = 0x02; // Tx = Hi-Z / Rx = 100 Ohm
973
as1 = 0x00; // Tx = Hi-Z / Rx = Hi-Z
977
default: // Tx = normal / Rx = 100 Ohm
983
/* Configure line interface */
984
if (lineconfig & ZT_CONFIG_AMI)
987
__t1_framer_out(wc, FR_FMR0, 0xa0);
992
__t1_framer_out(wc, FR_FMR0, 0xf0);
995
if (!(lineconfig & ZT_CONFIG_D4) && !(lineconfig & ZT_CONFIG_ESF)) // support for F4 4 frame format
999
__t1_framer_out(wc, FR_FMR2, 0x26);
1001
__t1_framer_out(wc, FR_FMR2, 0x22);
1003
if (wc->spantype == MODE_J1)
1004
__t1_framer_out(wc, FR_FMR4, 0x1d);
1006
__t1_framer_out(wc, FR_FMR4, 0x0d);
1009
if (!(lineconfig & ZT_CONFIG_D4) && (lineconfig & ZT_CONFIG_ESF)) // standard ESF 24 frame format
1014
__t1_framer_out(wc, FR_FMR2, 0xe6);
1016
__t1_framer_out(wc, FR_FMR2, 0xe2);
1018
if (wc->spantype == MODE_J1)
1019
__t1_framer_out(wc, FR_FMR4, 0x1e);
1021
__t1_framer_out(wc, FR_FMR4, 0x0e);
1024
if ((lineconfig & ZT_CONFIG_D4) && !(lineconfig & ZT_CONFIG_ESF)) // standard D4 12 frame format
1028
__t1_framer_out(wc, FR_FMR2, 0x26);
1030
__t1_framer_out(wc, FR_FMR2, 0x22);
1032
if (wc->spantype == MODE_J1)
1033
__t1_framer_out(wc, FR_FMR4, 0x1c);
1035
__t1_framer_out(wc, FR_FMR4, 0x0c);
1038
if ((lineconfig & ZT_CONFIG_D4) && (lineconfig & ZT_CONFIG_ESF)) // support for SLC96 framing mode used in TR-08 circuits
1042
__t1_framer_out(wc, FR_FMR2, 0x26);
1044
__t1_framer_out(wc, FR_FMR2, 0x22);
1046
if (wc->spantype == MODE_J1)
1047
__t1_framer_out(wc, FR_FMR4, 0x1f);
1049
__t1_framer_out(wc, FR_FMR4, 0x0f);
1053
__t1_framer_out(wc, FR_FMR5, 0x40); // FMR5: Enable RBS mode */
1055
__t1_framer_out(wc, FR_LIM1, 0xf8); // LIM1: Clear data in case of LOS, Set receiver threshold (0.5V), No remote loop, no DRS
1056
__t1_framer_out(wc, FR_LIM0, 0x08); // LIM0: Enable auto long haul mode, no local loop (must be set after LIM1)
1058
__t1_framer_out(wc, FR_CMDR, 0x50); // CMDR: Reset the receiver and transmitter line interface
1059
__t1_framer_out(wc, FR_CMDR, 0x00); // CMDR: Reset the receiver and transmitter line interface
1061
__t1_framer_out(wc, FR_PCD, 0x0a); // PCD: LOS after 176 consecutive "zeros"
1062
__t1_framer_out(wc, FR_PCR, 0x15); // PCR: 22 "ones" clear LOS
1064
if (wc->spantype == MODE_J1)
1067
__t1_framer_out(wc, FR_RC0, 0x80); // J1 overide
1074
switch (txlevel) // Set Tx pulse mask + Rx line build out
1077
__t1_framer_out(wc, FR_LIM2, 0xe1 | as1); // LIM2: LBO=3, RST=50%, LOS1=1
1078
__t1_framer_out(wc, FR_XPM0, 0x07); // XPM0
1079
__t1_framer_out(wc, FR_XPM1, 0x01); // XPM1
1080
__t1_framer_out(wc, FR_XPM2, 0x00 | xlt); // XPM2
1084
__t1_framer_out(wc, FR_LIM2, 0xa1 | as1); // LIM2: LBO=2, RST=50%, LOS1=1
1085
__t1_framer_out(wc, FR_XPM0, 0x8c); // XPM0
1086
__t1_framer_out(wc, FR_XPM1, 0x11); // XPM1
1087
__t1_framer_out(wc, FR_XPM2, 0x01 | xlt); // XPM2
1091
__t1_framer_out(wc, FR_LIM2, 0x61 | as1); // LIM2: LBO=1, RST=50%, LOS1=1
1092
__t1_framer_out(wc, FR_XPM0, 0x8c); // XPM0
1093
__t1_framer_out(wc, FR_XPM1, 0x01); // XPM1
1094
__t1_framer_out(wc, FR_XPM2, 0x00 | xlt); // XPM2
1098
__t1_framer_out(wc, FR_LIM2, 0x21 | as1); // LIM2: LBO=0, RST=50%, LOS1=1
1099
__t1_framer_out(wc, FR_XPM0, 0xd7); // XPM0
1100
__t1_framer_out(wc, FR_XPM1, 0x22); // XPM1
1101
__t1_framer_out(wc, FR_XPM2, 0x01 | xlt); // XPM2
1106
printk("DS1x1F: Configured Mode: %s Framing: %s Linecode: %s\n", mode, frame, lcode);
1110
static void __t1_configure_e1(struct t1 *wc, int lineconfig)
1112
unsigned int fmr2, fmr1;
1113
unsigned int cas = 0;
1115
char *frame, *lcode;
1119
fmr1 = 0x44; /* FMR1: E1 mode, Automatic force resync, PCM30 mode, 2.048 Mhz backplane, no XAIS */
1120
fmr2 = 0x03; /* FMR2: Auto transmit remote alarm, auto loss of multiframe recovery, no payload loopback */
1122
switch (monitor) // module parameter monitor
1125
as1 = 0x00; // Tx = normal / Rx = Hi-Z
1130
as1 = 0x02; // Tx = Hi-Z / Rx = 100 Ohm
1135
as1 = 0x00; // Tx = Hi-Z / Rx = Hi-Z
1139
default: // Tx = normal / Rx = 100 Ohm
1146
if (wc->spantype == MODE_UE1)
1152
if (lineconfig & ZT_CONFIG_CRC4)
1154
fmr1 |= 0x08; /* CRC4 transmit */
1155
fmr2 |= 0xc0; /* CRC4 receive */
1159
__t1_framer_out(wc, FR_FMR1, fmr1);
1160
__t1_framer_out(wc, FR_FMR2, fmr2);
1163
if (lineconfig & ZT_CONFIG_AMI) /* Configure line interface */
1166
__t1_framer_out(wc, FR_FMR0, 0xa0);
1171
__t1_framer_out(wc, FR_FMR0, 0xf0);
1174
if (lineconfig & ZT_CONFIG_CCS)
1184
if (wc->spantype == MODE_UE1)
1185
__t1_framer_out(wc, FR_LOOP, 0x40);
1187
__t1_framer_out(wc, FR_LIM1, 0xf0); // LIM1: Clear data in case of LOS, Set receiver threshold (0.5V), No remote loop, no DRS
1188
__t1_framer_out(wc, FR_LIM0, 0x08); // LIM0: Enable auto long haul mode, no local loop (must be after LIM1)
1190
__t1_framer_out(wc, FR_CMDR, 0x50); // CMDR: Reset the receiver and transmitter line interface
1191
__t1_framer_out(wc, FR_CMDR, 0x00); // CMDR: Reset the receiver and transmitter line interface
1193
// Condition receive line interface for E1 after reset
1194
__t1_framer_out(wc, 0xbb, 0x17);
1195
__t1_framer_out(wc, 0xbc, 0x55);
1196
__t1_framer_out(wc, 0xbb, 0x97);
1197
__t1_framer_out(wc, 0xbb, 0x11);
1198
__t1_framer_out(wc, 0xbc, 0xaa);
1199
__t1_framer_out(wc, 0xbb, 0x91);
1200
__t1_framer_out(wc, 0xbb, 0x12);
1201
__t1_framer_out(wc, 0xbc, 0x55);
1202
__t1_framer_out(wc, 0xbb, 0x92);
1203
__t1_framer_out(wc, 0xbb, 0x0c);
1204
__t1_framer_out(wc, 0xbb, 0x00);
1205
__t1_framer_out(wc, 0xbb, 0x8c);
1207
__t1_framer_out(wc, FR_LIM2, 0x20 | as1); // LIM2: 50% peak amplitude is a "1"
1208
__t1_framer_out(wc, FR_PCD, 0x0a); // PCD: LOS after 176 consecutive "zeros"
1209
__t1_framer_out(wc, FR_PCR, 0x15); // PCR: 22 "ones" clear LOS
1211
__t1_framer_out(wc, FR_XSW, 0x9f); // XSW: Spare bits all to 1
1213
if (wc->spantype == MODE_UE1)
1214
__t1_framer_out(wc, FR_XSP, 0x3c );
1216
__t1_framer_out(wc, FR_XSP, 0x1c | cas); // XSP: E-bit set when async. AXS auto, XSIF to 1
1218
// Generate pulse mask for E1
1219
__t1_framer_out(wc, FR_XPM0, 0x54); // XPM0
1220
__t1_framer_out(wc, FR_XPM1, 0x02); // XPM1
1221
__t1_framer_out(wc, FR_XPM2, 0x00 | xlt); // XPM2
1223
if (wc->spantype == MODE_UE1)
1224
printk("DS1x1F: Configured Mode: E1-Unchannelized Framing: %s Linecode: %s\n", frame, lcode);
1226
printk("DS1x1F: Configured Mode: E1%s Framing: %s Linecode: %s\n", crc4, frame, lcode);
1229
//-----------------------------------------------------------------------------------------------------------------------------------------
1232
static void ds1_framer_start(struct t1 *wc, struct zt_span *span)
1234
int alreadyrunning = wc->span.flags & ZT_FLAG_RUNNING;
1235
unsigned long flags;
1237
spin_lock_irqsave(&wc->lock, flags);
1239
if (wc->spantype & MODE_E1)
1240
{ // configure in E1/ UE1 mode
1241
__t1_configure_e1(wc, span->lineconfig);
1244
{ // configure in T1 / J1 mode
1245
__t1_configure_t1(wc, span->lineconfig, span->txlevel);
1246
__ds1_set_clear(wc);
1249
if (!alreadyrunning)
1250
wc->span.flags |= ZT_FLAG_RUNNING;
1252
spin_unlock_irqrestore(&wc->lock, flags);
1256
static int ds1_startup(struct zt_span *span)
1258
struct t1 *wc = span->pvt;
1260
int alreadyrunning = span->flags & ZT_FLAG_RUNNING;
1261
// initialize the start value for the entire chunk of last ec buffer
1262
// Reset framer with proper parameters and start
1263
ds1_framer_start(wc, span);
1264
printk("Calling startup (flags is %d)\n", span->flags);
1266
ctrl_write_reg(wc, CTRL_REL | CTRL_LRED); // now enable the relay
1269
if (!alreadyrunning)
1270
{ // Only if we're not already going
1271
ds1_enable_interrupts(wc);
1272
span->flags |= ZT_FLAG_RUNNING;
1278
static int ds1_shutdown(struct zt_span *span)
1280
struct t1 *wc = span->pvt;
1281
unsigned long flags;
1283
spin_lock_irqsave(&wc->lock, flags);
1285
__t1_framer_out(wc, FR_GCR, 0x41); // GCR: Interrupt on Activation/Deactivation of AIX, LOS
1287
ds1_disable_interrupts(wc);
1289
ctrl_write_reg(wc, CTRL_LRED); // turn off relay and turn on RED LED only
1291
span->flags &= ~ZT_FLAG_RUNNING;
1292
spin_unlock_irqrestore(&wc->lock, flags);
1297
static int ds1_chanconfig(struct zt_chan *chan, int sigtype)
1299
struct t1 *wc = chan->pvt;
1300
unsigned long flags;
1301
int alreadyrunning = chan->span->flags & ZT_FLAG_RUNNING;
1303
spin_lock_irqsave(&wc->lock, flags);
1305
if (alreadyrunning && (wc->spantype != MODE_E1))
1306
__ds1_set_clear(wc);
1308
spin_unlock_irqrestore(&wc->lock, flags);
1313
static int ds1_spanconfig(struct zt_span *span, struct zt_lineconfig *lc)
1315
span->lineconfig = lc->lineconfig;
1316
span->txlevel = lc->lbo;
1318
/* Do we want to SYNC on receive or not */
1319
/* If already running, apply changes immediately */
1320
if (span->flags & ZT_FLAG_RUNNING)
1321
return ds1_startup(span);
1327
static int ds1_software_init(struct t1 *wc)
1329
int x; /* Find position */
1331
for (x = 0; x < WC_MAX_CARDS; x++)
1340
if (x >= WC_MAX_CARDS)
1343
t4_serial_setup(wc);
1346
sprintf(wc->span.name, "WCT1/%d" , wc->num);
1347
sprintf(wc->span.desc, "%s Card %d", wc->variety, wc->num);
1349
wc->span.spanconfig = ds1_spanconfig;
1350
wc->span.chanconfig = ds1_chanconfig;
1351
wc->span.startup = ds1_startup;
1352
wc->span.shutdown = ds1_shutdown;
1353
wc->span.rbsbits = ds1_rbsbits;
1354
wc->span.maint = ds1_maint;
1355
wc->span.open = ds1_open;
1356
wc->span.close = ds1_close;
1358
switch (wc->spantype)
1361
wc->span.channels = 32;
1365
wc->span.channels = 31;
1369
wc->span.channels = 24;
1373
wc->span.chans = wc->chans;
1374
wc->span.flags = ZT_FLAG_RBS;
1375
wc->span.linecompat = ZT_CONFIG_AMI | ZT_CONFIG_B8ZS | ZT_CONFIG_D4 | ZT_CONFIG_ESF;
1376
wc->span.ioctl = ds1_ioctl;
1379
if (wc->spantype & MODE_E1)
1380
wc->span.deflaw = ZT_LAW_ALAW;
1382
wc->span.deflaw = ZT_LAW_MULAW;
1384
init_waitqueue_head(&wc->span.maintq);
1386
for (x=0;x<wc->span.channels;x++)
1388
sprintf(wc->chans[x].name, "WCT1/%d/%d", wc->num, x + 1);
1389
wc->chans[x].sigcap = ZT_SIG_EM | ZT_SIG_CLEAR | ZT_SIG_EM_E1 |
1390
ZT_SIG_FXSLS | ZT_SIG_FXSGS |
1391
ZT_SIG_FXSKS | ZT_SIG_FXOLS | ZT_SIG_DACS_RBS |
1392
ZT_SIG_FXOGS | ZT_SIG_FXOKS | ZT_SIG_CAS | ZT_SIG_SF;
1393
wc->chans[x].pvt = wc;
1394
wc->chans[x].chanpos = x + 1;
1397
if (zt_register(&wc->span, 0))
1399
printk("Unable to register span with zaptel\n");
1406
static inline void __handle_leds(struct t1 *wc)
1412
if (wc->blinktimer >= 4000)
1415
oldreg = wc->ledtestreg;
1417
if (wc->span.alarms & ZT_ALARM_RED) // RED alarm active
1418
{ // LOS = loss of signal
1419
if (wc->blinktimer < 50)
1420
wc->ledtestreg = CTRL_LRED;
1422
wc->ledtestreg = CTRL_LOFF;
1424
if (wc->blinktimer >= 200) // very fast flickering
1430
if (wc->span.alarms & ZT_ALARM_YELLOW) // YELLOW ALARM = RED LED flashing
1431
{ // other side can't see our signal
1432
if (wc->blinktimer < 250)
1433
wc->ledtestreg = CTRL_LRED;
1435
wc->ledtestreg = CTRL_LOFF;
1437
if (wc->blinktimer >= 500) // flashing
1442
if (wc->span.alarms & ZT_ALARM_BLUE) // BLUE ALARM
1443
{ // T1 failure in front of a repeater down the line
1444
if (wc->blinktimer < 250)
1445
wc->ledtestreg = CTRL_LGRN; // GREEN LED flashing
1447
wc->ledtestreg = CTRL_LOFF;
1449
if (wc->blinktimer >= 500) // flashing
1454
if (wc->blinktimer < 150) // slow winking green led heartbeat
1455
wc->ledtestreg = CTRL_LOFF;
1457
wc->ledtestreg = CTRL_LGRN; // GREEN LED on most of the time
1462
if (oldreg != wc->ledtestreg) // only when some bits have changed
1463
led_write_reg(wc, wc->ledtestreg); // write LED bits 0,1
1467
//====================================== SEND MEDIA DATA =====================================
1468
static void ds1_media(struct t1 *wc)
1470
int x,y,ty,ry,shift;
1474
frm = (clk_read_reg(wc) & 0x07) + 1; // see how many frames are to be read by card
1476
ty = wc->txchunkptr;
1477
ry = wc->rxchunkptr;
1480
for (y = 0; y < frm; y++)
1484
if (ty >= ZT_CHUNKSIZE)
1487
zt_transmit(&wc->span);
1490
rx = ioread32(wc->ioaddr + OFS_TDM_RD + 0 + reg); // read in first 4 channels
1491
tx = 0xff; // FALC-56 uses TS0 for sync purposes only
1493
for (x=1; x<=wc->span.channels; x++)
1497
iowrite32(tx, wc->ioaddr + OFS_TDM_WR + x - 4 + reg); // write 4 bytes (channels) of pcm data
1499
rx = ioread32(wc->ioaddr + OFS_TDM_RD + x + reg);
1502
shift = ((x % 4) << 3);
1503
tx |= (wc->chans[x-1].writechunk[ty] & 0xff) << shift;
1504
wc->chans[x-1].readchunk [ry] = (rx >> shift) & 0xff;
1507
iowrite32(tx, wc->ioaddr + OFS_TDM_WR + (x & 0xfc) + reg); // write 4 bytes (channels) of pcm data
1512
if (ry >= ZT_CHUNKSIZE)
1516
for (x=0; x<wc->span.channels; x++) // handle echocanceller memory fill
1518
zt_ec_chunk(&wc->chans[x], wc->chans[x].readchunk, wc->ec_chunk2[x]);
1520
memcpy(wc->ec_chunk2[x], wc->ec_chunk1[x] , ZT_CHUNKSIZE);
1521
memcpy(wc->ec_chunk1[x], wc->chans[x].writechunk, ZT_CHUNKSIZE);
1524
zt_receive(&wc->span);
1528
wc->txchunkptr = ty;
1529
wc->rxchunkptr = ry;
1534
//===============================================================================================================================================================================
1537
static void __t1_check_alarms(struct t1 *wc)
1543
if (!(wc->span.flags & ZT_FLAG_RUNNING))
1546
c = __t1_framer_in(wc, FR_FRS0);
1547
d = __t1_framer_in(wc, FR_FRS1);
1549
/* Assume no alarms */
1552
/* And consider only carrier alarms */
1553
wc->span.alarms &= (ZT_ALARM_RED | ZT_ALARM_BLUE | ZT_ALARM_NOTOPEN);
1555
if (wc->spantype & MODE_E1)
1558
{ /* No multiframe found, force RAI high after 400ms only if we haven't found a multiframe since last loss of frame */
1559
if (!(wc->spanflags & FLAG_NMF))
1561
__t1_framer_out(wc, FR_FMR4, 0x9f | 0x20); /* FMR4: Force RAI High */
1562
wc->spanflags |= FLAG_NMF;
1563
printk("NMF workaround on!\n");
1566
__t1_framer_out(wc, FR_FMR2, 0xc3); /* Reset to CRC4 mode */
1567
__t1_framer_out(wc, FR_FMR0, 0xf2); /* Force Resync */
1568
__t1_framer_out(wc, FR_FMR0, 0xf0); /* Force Resync */
1574
if ((wc->spanflags & FLAG_NMF))
1576
__t1_framer_out(wc, FR_FMR4, 0x9f); /* FMR4: Clear forced RAI */
1577
wc->spanflags &= ~FLAG_NMF;
1578
printk("NMF workaround off!\n");
1584
{ /* Detect loopup code if we're not sending one */
1585
if ((!wc->span.mainttimer) && (d & 0x08))
1587
if ((wc->loopupcnt++ > 80) && (wc->span.maintstat != ZT_MAINT_REMOTELOOP)) // Loop-up code detected
1589
__t1_framer_out(wc, FR_LIM0, 0x08); // LIM0: Disable any local loop
1590
__t1_framer_out(wc, FR_LIM1, 0xf6); // LIM1: Enable remote loop
1592
wc->span.maintstat = ZT_MAINT_REMOTELOOP; // maintainance status = REMOTELOOP
1598
/* Same for loopdown code */
1599
if ((!wc->span.mainttimer) && (d & 0x10))
1600
{ /* Loop-down code detected */
1601
if ((wc->loopdowncnt++ > 80) && (wc->span.maintstat == ZT_MAINT_REMOTELOOP))
1603
__t1_framer_out(wc, FR_LIM0, 0x08); /* LIM0: Disable any local loop */
1604
__t1_framer_out(wc, FR_LIM1, 0xf0); /* LIM1: Disable remote loop */
1605
wc->span.maintstat = ZT_MAINT_NONE;
1609
wc->loopdowncnt = 0;
1612
if (wc->span.lineconfig & ZT_CONFIG_NOTOPEN)
1614
for (x=0,j=0;x < wc->span.channels;x++)
1616
if ((wc->span.chans[x].flags & ZT_FLAG_OPEN) || (wc->span.chans[x].flags & ZT_FLAG_NETDEV))
1621
alarms |= ZT_ALARM_NOTOPEN;
1626
if (wc->alarmcount >= alarmdebounce)
1628
if (!(wc->spantype & 0x80))
1629
alarms |= ZT_ALARM_RED;
1638
alarms |= ZT_ALARM_BLUE;
1640
/* Keep track of recovering */
1641
if ((!alarms) && wc->span.alarms)
1642
wc->alarmtimer = ZT_ALARMSETTLE_TIME;
1645
alarms |= ZT_ALARM_RECOVER;
1647
/* If receiving alarms, go into Yellow alarm state */
1648
if (alarms && !(wc->spanflags & FLAG_SENDINGYELLOW))
1651
printk("DS1x1F: Setting yellow alarm\n");
1652
/* We manually do yellow alarm to handle RECOVER and NOTOPEN, otherwise it's auto anyway */
1653
fmr4 = __t1_framer_in(wc, FR_FMR4);
1654
__t1_framer_out(wc, FR_FMR4, fmr4 | 0x20);
1656
wc->spanflags |= FLAG_SENDINGYELLOW;
1660
if ((!alarms) && (wc->spanflags & FLAG_SENDINGYELLOW))
1663
printk("DS1x1F: Clearing yellow alarm\n");
1664
// We manually do yellow alarm to handle RECOVER
1665
fmr4 = __t1_framer_in(wc, FR_FMR4);
1666
__t1_framer_out(wc, FR_FMR4, fmr4 & ~0x20);
1668
wc->spanflags &= ~FLAG_SENDINGYELLOW;
1671
// Re-check the timing source when we enter/leave alarm, not withstanding yellow alarm
1672
if ((c & 0x10) && !(wc->spantype & 0x80))
1673
alarms |= ZT_ALARM_YELLOW;
1675
if (wc->span.mainttimer || wc->span.maintstat)
1676
alarms |= ZT_ALARM_LOOPBACK;
1678
wc->span.alarms = alarms;
1679
zt_alarm_notify(&wc->span);
1683
static void __ds1_do_counters(struct t1 *wc)
1687
if (!--wc->alarmtimer)
1689
wc->span.alarms &= ~(ZT_ALARM_RECOVER);
1690
zt_alarm_notify(&wc->span);
1695
///--------------------------------------------------------------------------------------------------------------------------------
1696
ZAP_IRQ_HANDLER(ds1_interrupt)
1698
struct t1 *wc = dev_id;
1699
unsigned long flags;
1703
x = ctrl_read_reg(wc); // read statusregister
1705
if (!(x & CTRL_IRQ))
1708
ctrl_set_reg(wc, CTRL_INTA); // clear the interrupt flag
1710
if (!wc->intcount && debug)
1711
printk("DS1x1F: Got interrupt\n");
1713
if (x & CTRL_IRM) // we missed at least one interrupt
1714
printk("DS1x1F: Missed an Interrupt !!!\n");
1716
ds1_media(wc); // handle media / audio- buffers
1718
x = clk_read_reg(wc) & 0x07; // get the current frame buffer setting
1720
spin_lock_irqsave(&wc->lock, flags);
1722
y = wc->prescaler - 1;
1729
// Count down timers
1730
__ds1_do_counters(wc);
1734
x = wc->intcount & 0x0f; // Do some things that we don't have to do very often
1742
__t1_check_sigbits(wc);
1744
case 4: // Check alarms 1/4 as frequently
1745
if (!(wc->intcount & 0x30))
1746
__t1_check_alarms(wc);
1752
spin_unlock_irqrestore(&wc->lock, flags);
1754
return IRQ_RETVAL(1);
1757
static int memory_test(struct t1 *wc, int pattern)
1762
for (x=0; x<31; x++) // clear out tx tdm memory to FF
1764
iowrite32 (pattern, wc->ioaddr + OFS_TDM_WR + (8 * x) );
1766
y = ioread32( wc->ioaddr + OFS_TDM_WR + (8 * x) );
1772
printk("DS1x1F: TDM tx memory failure %08x / %08x @ %02x LSB\n", pattern, y, x);
1776
printk("DS1x1F: TDM tx memory OK %08x / %08x @ %02x LSB\n", pattern, y, x);
1778
iowrite32 (pattern, wc->ioaddr + OFS_TDM_RD + (8 * x));
1780
y = ioread32( wc->ioaddr + OFS_TDM_RD + (8 * x));
1786
printk("DS1x1F: TDM rx memory failure %08x / %08x @ %02x MSB\n", pattern, y, x);
1790
printk("DS1x1F: TDM rx memory OK %08x / %08x @ %02x MSB\n", pattern, y, x);
1798
//--------------------------------------------------------------------------------------------------------------------------------------
1799
static int ds1_hardware_init(struct t1 *wc)
1801
unsigned int vstr, wid;
1804
if (frames < 1) // setting frames = 0 autoadjust to current ZT_CHUNKSIZE
1805
frames = ZT_CHUNKSIZE;
1807
if (frames > 8) // maximum framebuffer size is 8 frames
1810
if (extclk == -1) // extclk not specified by parameter
1812
x = ctrl_read_reg(wc); // read DIP switch
1813
extclk = (x >> 14) & 0x03; // SW 3-4 => clock selection
1816
switch (extclk) // external / H.100 bus clocking options
1818
case 1: // clock derived from H.100 bus if available
1819
x = 0x30 | (frames - 1);
1822
case 2: // this card is bus clock master
1823
x = 0x20 | (frames - 1);
1826
default: // all other cases - internally clocked / no clk output
1831
clk_write_reg (wc, x); // no loopback
1833
mdelay(10); // wait for 10 msec. for FDET settle time
1835
x = clk_read_reg(wc);
1840
printk("DS1x1F: Clocking: Busmaster Framebuffer: %d frames\n",(x & 0x07) + 1);
1845
printk("DS1x1F: Clocking: External ( clock present on bus) Framebuffer: %d frames\n",(x & 0x07) + 1);
1847
printk("DS1x1F: Clocking: (External) no clock present on bus Framebuffer: %d frames\n",(x & 0x07) + 1);
1851
printk("DS1x1F: Clocking: Internal Framebuffer: %d frames\n",(x & 0x07) + 1);
1855
ctrl_write_reg(wc, CTRL_INTA | CTRL_TEST | CTRL_FRST);
1857
mdelay(10); // wait for 10 msec.
1859
x = ctrl_read_reg(wc); // read in the controlregister
1861
ctrl_write_reg(wc, CTRL_LRED);
1863
mdelay(1); // wait for 1 msec.
1866
wc->spantype = cardmode; // read in spanmode paramter
1868
switch (x & 0x3000) // check if SW-1 and SW-2
1871
wc->spantype = MODE_T1; // OFF - OFF = T1
1875
wc->spantype = MODE_J1; // OFF - ON = J1
1879
wc->spantype = MODE_UE1; // ON - OFF = unchannelized E1
1883
wc->spantype = MODE_E1; // ON - ON = E1
1888
printk("DS1x1 Board Ver: %01x.%01x SW=%01x-%01x-%01x-%01x [%x]\n",(x>>28),((x>>20)&0xf),((x>>15)&1),((x>>14)&1),((x>>13)&1),((x>>12)&1),x);
1890
printk("DS1x1F Board Ver: %01x.%01x SW=%01x-%01x-%01x-%01x [%x]\n",(x>>28),((x>>20)&0xf),((x>>15)&1),((x>>14)&1),((x>>13)&1),((x>>12)&1),x);
1892
vstr = t1_framer_in(wc ,FR_VSTR); // identify FALC framer chip version
1893
wid = t1_framer_in(wc ,FR_WID );
1898
printk("FALC PEF-2256 Ver: 2.2 detected\n");
1900
printk("FALC PEF-2256 Ver: 2.1 detected\n");
1904
if ((wid & 0x03) == 0x03)
1905
printk("!!! WARNING !!! Old FALC PEB-2256 Ver: 1.2 detected\n");
1907
printk("!!! WARNING !!! FALC Version unknown: VSTR: %02x WID: %02x\n", vstr, wid);
1910
ds1_disable_interrupts(wc);
1914
if (memory_test (wc, 0x5555aaaa)) x = 1;
1915
if (memory_test (wc, 0x01234567)) x = 1;
1916
if (memory_test (wc, 0xaaaa5555)) x = 1;
1917
if (memory_test (wc, 0x76543210)) x = 1;
1920
printk("DS1x1F: Card TDM memory test failed !!!\n");
1922
printk("DS1x1F: Card TDM memory test completed.\n");
1924
ds1_enable_interrupts(wc);
1932
static int __devinit ds1_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1938
if (pci_enable_device(pdev))
1940
printk (KERN_ALERT "DS1x1F: PCI enable failed\n");
1941
pci_disable_device (pdev);
1946
wc = kmalloc(sizeof(struct t1), GFP_KERNEL);
1948
printk("Trying to init an DS1x1F\n");
1952
memset(wc, 0x0, sizeof(struct t1)); // initialize structure with 0x00
1953
spin_lock_init(&wc->lock);
1955
wc->cnstart = pci_resource_start(pdev, 0); // read the assigned memory resources for region 0
1956
end = pci_resource_end (pdev, 0);
1957
wc->cnlen = end - wc->cnstart + 1;
1958
wc->cres = request_mem_region(wc->cnstart,wc->cnlen,name);
1959
wc->cnaddr = ioremap_nocache (wc->cnstart,wc->cnlen );
1962
printk (KERN_INFO "Config resources = [0x%lx-0x%lx] (%ld) \n", wc->cnstart, end, wc->cnlen);
1964
wc->iostart = pci_resource_start(pdev, 2); // read the assigned memory resources for region 2
1965
end = pci_resource_end (pdev, 2);
1966
wc->iolen = end - wc->iostart + 1;
1967
wc->ires = request_mem_region(wc->iostart,wc->iolen,name);
1968
wc->ioaddr = ioremap_nocache (wc->iostart,wc->iolen );
1971
printk (KERN_INFO "I/O resources = [0x%lx-0x%lx] (%ld) \n", wc->iostart, end, wc->iolen);
1975
pci_set_drvdata(pdev, wc); // keep track of our device - i.e. for later removal
1977
if (request_irq(pdev->irq, ds1_interrupt, ZAP_IRQ_SHARED_DISABLED, "ds1x1f", wc))
1979
printk("DS1x1F: Unable to request IRQ %d\n", pdev->irq);
1984
ds1_hardware_init(wc); // Initialize hardware
1986
wc->variety = "DS1x1F T1/E1-card"; // We now know which version of card we have
1987
ds1_software_init(wc); // Misc. software stuff
1989
printk("Found an: %s\n", wc->variety);
1994
printk (KERN_ALERT "DS1x1F: failed to allocate memory\n");
2002
static void __devexit ds1_remove(struct pci_dev *pdev)
2004
struct t1 *wc = pci_get_drvdata(pdev);
2009
ds1_disable_interrupts(wc); // In case hardware is still there
2010
free_irq(pdev->irq, wc); // release the interrupt resource
2013
zt_unregister(&wc->span);
2016
printk (KERN_ALERT "DS1x1F: resetting relay / falc / red led on\n");
2018
ctrl_write_reg(wc, CTRL_FRST | CTRL_LRED); // reset FALC, relay= off, Red LED = on
2020
if (wc->ioaddr != NULL) // unmap io space
2021
iounmap (wc->ioaddr);
2023
if (wc->cnaddr != NULL) // unmap control space
2024
iounmap (wc->cnaddr);
2026
release_mem_region(wc->iostart, wc->iolen); // release io memory region
2027
release_mem_region(wc->cnstart, wc->cnlen); // release control memory region
2031
printk (KERN_ALERT "DS1x1F: disable pci device\n");
2032
pci_disable_device (pdev);
2035
printk (KERN_ALERT "DS1x1F: WARNING Removal Failed !!!\n");
2040
static struct pci_device_id ds1_ids[] = { { PCI_DEVICE( 0x2321, 0x011f) }, { 0, }, };
2043
MODULE_DEVICE_TABLE(pci,ds1_ids);
2046
static struct pci_driver ds1_driver = {
2049
remove: __devexit_p(ds1_remove),
2056
static int __init ds1_init(void)
2059
res = zap_pci_module(&ds1_driver);
2068
static void __exit ds1_cleanup(void)
2070
pci_unregister_driver(&ds1_driver);
2075
module_param(alarmdebounce, int, 0600);
2076
module_param(loopback, int, 0600);
2077
module_param(cardmode, int, 0600);
2078
module_param(frames, int, 0600);
2079
module_param(debug, int, 0600);
2080
module_param(extclk, int, 0600);
2081
module_param(monitor, int, 0600);
2083
MODULE_DESCRIPTION("TC-DG ds1x1f Zaptel Driver");
2084
MODULE_AUTHOR("TCDG Corp. <tech@tc-dg.net");
2085
MODULE_LICENSE("GPL");
2087
module_init(ds1_init);
2088
module_exit(ds1_cleanup);
added
removed
kernel/ds1x1f.c
