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#define qoz_FIFO_SIZE 128
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#define qoz_DFIFO_SIZE4 2048
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#define qoz_DFIFO_SIZE8 1024
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typedef struct qoz_span {
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unsigned char bswapped;
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unsigned char layer1state;
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typedef struct qoz_regs {
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unsigned char fifo_en;
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unsigned char sctrl_e;
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unsigned char sctrl_r;
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unsigned char connect;
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unsigned char mst_mode;
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typedef struct qoz_card {
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unsigned char leds[8];
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unsigned char *pci_io;
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struct qoz_span st[qoz_SPANS];
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int st_sync[qoz_SPANS];
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unsigned int pcidevfn;
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struct pci_dev *pcidev;
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struct zt_span spans[qoz_SPANS];
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struct zt_chan chans[qoz_SPANS][3];
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unsigned char rxbuf[qoz_SPANS][2][ZT_CHUNKSIZE];
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unsigned char txbuf[qoz_SPANS][2][ZT_CHUNKSIZE];
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unsigned char drxbuf[qoz_SPANS][qoz_DFIFO_SIZE4];
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unsigned char dtxbuf[qoz_SPANS][qoz_DFIFO_SIZE4];
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unsigned char stports;
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struct qoz_card *next;
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struct qoz_card *prev;
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#define qoz_outb_io(a,b,c) \
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outw((b), ((a)->ioport+4)); \
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outb((c), ((a)->ioport));
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#define qoz_inb_io(a,b) ({ outw((b), (a)->ioport+4); inb((a)->ioport); })
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#define qoz_outw_io(a,b,c) \
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outw((b), ((a)->ioport+4)); \
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outw((c), ((a)->ioport));
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#define qoz_inw_io(a,b) ({ outw((b), (a)->ioport+4); inw((a)->ioport); })
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#define qoz_outdw_io(a,b,c) \
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outw((b), ((a)->ioport+4)); \
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outl((c), ((a)->ioport));
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#define qoz_indw_io(a,b) ({ outw((b), (a)->ioport+4); inl((a)->ioport); })
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#define qoz_outb(a,b,c) (writeb((c),(a)->pci_io+(b)))
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#define qoz_inb(a,b) (readb((a)->pci_io+(b)))
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#define qoz_outw(a,b,c) (writew((c),(a)->pci_io+(b)))
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#define qoz_inw(a,b) (readw((a)->pci_io+(b)))
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#define qoz_outdw(a,b,c) (writel((c),(a)->pci_io+(b)))
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#define qoz_indw(a,b) (readl((a)->pci_io+(b)))
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/* Write only registers */
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#define qoz_A_CH_MSK 0xF4
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#define qoz_A_CHANNEL 0xFC
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#define qoz_A_CON_HDLC 0xFA
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#define qoz_A_CONF 0xD1
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#define qoz_A_FIFO_SEQ 0xFD
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#define qoz_R_INC_RES_FIFO 0x0E
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#define qoz_A_IRQ_MSK 0xFF
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#define qoz_A_SL_CFG 0xD0
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#define qoz_A_ST_B1_TX 0x3C
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#define qoz_A_ST_B2_TX 0x3D
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#define qoz_A_ST_CLK_DLY 0x37
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#define qoz_A_ST_CTRL0 0x31
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#define qoz_A_ST_CTRL1 0x32
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#define qoz_A_ST_CTRL2 0x33
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#define qoz_A_ST_D_TX 0x3E
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#define qoz_A_ST_SQ_WR 0x34
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#define qoz_A_ST_WR_STA 0x30
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#define qoz_A_SUBCH_CFG 0xFB
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#define qoz_R_BERT_WD_MD 0x1B
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#define qoz_R_BRG_CTRL 0x45
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#define qoz_R_BRG_MD 0x47
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#define qoz_R_BRG_PCM_CFG 0x02
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#define qoz_R_BRG_TIM_SEL01 0x4C
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#define qoz_R_BRG_TIM_SEL23 0x4D
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#define qoz_R_BRG_TIM_SEL45 0x4E
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#define qoz_R_BRG_TIM_SEL67 0x4F
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#define qoz_R_BRG_TIM0 0x48
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#define qoz_R_BRG_TIM1 0x49
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#define qoz_R_BRG_TIM2 0x4A
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#define qoz_R_BRG_TIM3 0x4B
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#define qoz_R_CIRM 0x00
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#define qoz_R_CONF_EN 0x18
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#define qoz_R_CTRL 0x01
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#define qoz_R_DTMF0 0x1C
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#define qoz_R_DTMF1 0x1D
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#define qoz_R_FIFO_MD 0x0D
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#define qoz_R_FIFO 0x0F
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#define qoz_R_FIRST_FIFO 0x0B
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#define qoz_R_FSM_IDX 0x0F
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#define qoz_R_GPIO_EN0 0x42
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#define qoz_R_GPIO_EN1 0x43
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#define qoz_R_GPIO_OUT0 0x40
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#define qoz_R_GPIO_OUT1 0x41
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#define qoz_R_GPIO_SEL 0x44
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#define qoz_R_IRQ_CTRL 0x13
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#define qoz_R_IRQMSK_MISC 0x11
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#define qoz_R_PCM_MD0 0x14
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#define qoz_R_PCM_MD1 0x15
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#define qoz_R_PCM_MD2 0x15
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#define qoz_R_PWM_MD 0x46
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#define qoz_R_PWM0 0x38
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#define qoz_R_PWM1 0x39
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#define qoz_R_RAM_ADDR0 0x08
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#define qoz_R_RAM_ADDR1 0x09
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#define qoz_R_RAM_ADDR2 0x0A
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#define qoz_R_RAM_MISC 0x0C
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#define qoz_R_SCI_MSK 0x12
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#define qoz_R_SH0H 0x15
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#define qoz_R_SH0L 0x15
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#define qoz_R_SH1H 0x15
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#define qoz_R_SH1L 0x15
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#define qoz_R_SL_SEL0 0x15
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#define qoz_R_SL_SEL1 0x15
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#define qoz_R_SL_SEL2 0x15
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#define qoz_R_SL_SEL3 0x15
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#define qoz_R_SL_SEL4 0x15
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#define qoz_R_SL_SEL5 0x15
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#define qoz_R_SL_SEL6 0x15
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#define qoz_R_SL_SEL7 0x15
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#define qoz_R_SLOT 0x10
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#define qoz_R_ST_SEL 0x16
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#define qoz_R_ST_SYNC 0x17
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#define qoz_R_TI_WD 0x1A
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/* Read only registers */
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#define qoz_A_F1 0x0C
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#define qoz_A_F12 0x0C
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#define qoz_A_F2 0x0D
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#define qoz_A_ST_B1_RX 0x3C
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#define qoz_A_ST_B2_TX 0x3D
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#define qoz_A_ST_D_RX 0x3E
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#define qoz_A_ST_E_RX 0x3F
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#define qoz_A_ST_RD_STA 0x30
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#define qoz_A_ST_SQ_RD 0x34
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#define qoz_A_Z1 0x04
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#define qoz_A_Z12 0x04
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#define qoz_A_Z1H 0x05
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#define qoz_A_Z1L 0x04
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#define qoz_A_Z2 0x06
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#define qoz_A_Z2H 0x07
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#define qoz_A_Z2L 0x06
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#define qoz_R_BERT_ECH 0x1B
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#define qoz_R_BERT_ECL 0x1A
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#define qoz_R_BERT_STA 0x17
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#define qoz_R_CHIP_ID 0x16
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#define qoz_R_CHIP_RV 0x1F
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#define qoz_R_CONF_OFLOW 0x14
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#define qoz_R_F0_CNTH 0x19
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#define qoz_R_F0_CNTL 0x18
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#define qoz_R_GPI_IN0 0x44
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#define qoz_R_GPI_IN1 0x45
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#define qoz_R_GPI_IN2 0x46
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#define qoz_R_GPI_IN3 0x47
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#define qoz_R_GPIO_IN0 0x40
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#define qoz_R_GPIO_IN1 0x41
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#define qoz_R_INT_DATA 0x88
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#define qoz_R_IRQ_FIFO_BL0 0xC8
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#define qoz_R_IRQ_FIFO_BL1 0xC9
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#define qoz_R_IRQ_FIFO_BL2 0xCA
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#define qoz_R_IRQ_FIFO_BL3 0xCB
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#define qoz_R_IRQ_FIFO_BL4 0xCC
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#define qoz_R_IRQ_FIFO_BL5 0xCD
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#define qoz_R_IRQ_FIFO_BL6 0xCE
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#define qoz_R_IRQ_FIFO_BL7 0xCF
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#define qoz_R_IRQ_MISC 0x11
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#define qoz_R_IRQ_OVIEW 0x10
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#define qoz_R_RAM_USE 0x15
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#define qoz_R_SCI 0x12
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#define qoz_R_STATUS 0x1C
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/* Read/Write registers */
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#define qoz_A_FIFO_DATA0_NOINC 0x84
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#define qoz_A_FIFO_DATA0 0x80
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#define qoz_A_FIFO_DATA1_NOINC 0x84
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#define qoz_A_FIFO_DATA1 0x80
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#define qoz_A_FIFO_DATA2_NOINC 0x84
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#define qoz_A_FIFO_DATA2 0x80
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#define qoz_R_RAM_DATA 0xC0
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#define PCI_DEVICE_ID_CCD_M 0x16b8
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#define PCI_DEVICE_ID_CCD_M4 0x08b4
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#define CLKDEL_TE 0xe /* CLKDEL in TE mode */
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#define CLKDEL_NT 0xc /* CLKDEL in NT mode */
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#define HFC8S_CHIP_ID 0x80
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#define HFC4S_CHIP_ID 0xC0
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#define qoz_WD_P0 0x000000
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#define qoz_WD_P1 0x808080
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#define qoz_WD_P2 0x404040