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Viewing changes to src/VBox/VMM/HWACCMInternal.h

  • Committer: Bazaar Package Importer
  • Author(s): Felix Geyer
  • Date: 2009-12-18 16:44:29 UTC
  • mfrom: (0.3.3 upstream) (0.4.6 squeeze)
  • Revision ID: james.westby@ubuntu.com-20091218164429-jd34ccexpv5na11a
Tags: 3.1.2-dfsg-1ubuntu1
https://launchpad.net/bugs/498219
https://launchpad.net/bugs/288590
https://launchpad.net/bugs/474625
https://launchpad.net/bugs/495935
https://launchpad.net/bugs/473334
* Merge from Debian unstable (LP: #498219), remaining changes:
  - Disable update action
    - debian/patches/u01-disable-update-action.dpatch
  - VirtualBox should go in Accessories, not in System tools (LP: #288590)
    - debian/virtualbox-ose-qt.files/virtualbox-ose.desktop
  - Add Apport hook
    - debian/virtualbox-ose.files/source_virtualbox-ose.py
    - debian/virtualbox-ose.install
  - Add Launchpad integration
    - debian/control
    - debian/lpi-bug.xpm
    - debian/patches/u02-lp-integration.dpatch
* Fixes the following bugs:
  - Kernel module fails to build with Linux >= 2.6.32 (LP: #474625)
  - X.Org drivers need to be rebuilt against X-Server 1.7 (LP: #495935)
  - The *-source packages try to build the kernel modules even though the
    kernel headers aren't available (LP: #473334)
* Replace *-source packages with transitional packages for *-dkms.
* Adapt u01-disable-update-action.dpatch and u02-lp-integration.dpatch for
  new upstream version.

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Lines of Context:
src/VBox/VMM/HWACCMInternal.h
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} HWACCM_CPUINFO;
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typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
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/* VT-x capability qword. */
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typedef union
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{
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    struct
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    {
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        uint32_t        disallowed0;
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        uint32_t        allowed1;
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    } n;
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    uint64_t            u;
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} VMX_CAPABILITY;
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typedef enum
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{
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    HWACCMPENDINGIO_INVALID = 0,
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    /** Set when TPR patching is allowed. */
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    bool                        fTRPPatchingAllowed;
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    /** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
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     *  naturally. */
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    bool                        padding[1];
 
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    /** Set when we initialize VT-x or AMD-V once for all CPUs. */
 
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    bool                        fGlobalInit;
 
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    /** Set when TPR patching is active. */
 
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    bool                        fTPRPatchingActive;
 
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    bool                        u8Alignment[7];
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    /** And mask for copying register contents. */
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    uint64_t                    u64RegisterMask;
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        bool                        fEnabled;
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        /** Set if erratum 170 affects the AMD cpu. */
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        bool                        fAlwaysFlushTLB;
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        /** Set when TPR patching is active. */
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        bool                        fTPRPatchingActive;
 
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        bool                        u8Alignment;
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        /** R0 memory object for the IO bitmap (12kb). */
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        RTR0MEMOBJ                  pMemObjIOBitmap;
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        /** Virtual address of the IO bitmap. */
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        R0PTRTYPE(void *)           pIOBitmap;
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        /* HWCR msr (for diagnostics) */
 
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        uint64_t                    msrHWCR;
 
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        /** SVM revision. */
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        uint32_t                    u32Rev;
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        /** SVM feature bits from cpuid 0x8000000a */
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        uint32_t                    u32Features;
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        /**
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         * AVL tree with all patches (active or disabled) sorted by guest instruction address
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         */
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        AVLOU32TREE                 PatchTree;
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        uint32_t                    cPatches;
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        HWACCMTPRPATCH              aPatches[64];
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    } svm;
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    /**
 
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     * AVL tree with all patches (active or disabled) sorted by guest instruction address
 
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     */
 
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    AVLOU32TREE                     PatchTree;
 
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    uint32_t                        cPatches;
 
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    HWACCMTPRPATCH                  aPatches[64];
 
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    struct
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    {
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        uint32_t                    u32AMDFeatureECX;
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    /** HWACCMR0Init was run */
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    bool                    fHWACCMR0Init;
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    bool                    u8Alignment[7];
 
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    bool                    u8Alignment1[7];
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    STAMCOUNTER             StatTPRPatchSuccess;
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    STAMCOUNTER             StatTPRPatchFailure;
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    /** Set when we're using VT-x or AMD-V at that moment. */
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    bool                        fActive;
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    /** Set when the TLB has been checked until we return from the world switch. */
 
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    volatile uint8_t            fCheckedTLBFlush;
 
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    uint8_t                     bAlignment[3];
 
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    /** HWACCM_CHANGED_* flags. */
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    RTUINT                      fContextUseFlags;
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    /* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
 
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    /** Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
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    RTCPUID                     idLastCpu;
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    /* TLB flush count */
 
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    /** TLB flush count */
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    RTUINT                      cTLBFlushes;
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    /* Current ASID in use by the VM */
 
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    /** Current ASID in use by the VM */
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    RTUINT                      uCurrentASID;
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    /** World switch exit counter. */ 
 
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    volatile uint32_t           cWorldSwitchExit;
 
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    uint32_t                    u32Alignment;
 
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    struct
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    {
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        /** Physical address of the VM control structure (VMCS). */
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        /** Ring 0 handlers for VT-x. */
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        PFNHWACCMVMXSTARTVM         pfnStartVM;
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#if HC_ARCH_BITS == 32
 
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        uint32_t                    u32Alignment;
 
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#endif
 
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        /** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
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        uint64_t                    proc_ctls;
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#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
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    STAMPROFILEADV          StatWorldSwitch3264;
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#endif
 
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    STAMPROFILEADV          StatPoke;
 
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    STAMPROFILEADV          StatSpinPoke;
 
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    STAMPROFILEADV          StatSpinPokeFailed;
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    STAMCOUNTER             StatIntInject;
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    STAMCOUNTER             StatIntReinject;
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    STAMCOUNTER             StatPendingHostIrq;
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    STAMCOUNTER             StatFlushPage;
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    STAMCOUNTER             StatFlushPageManual;
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    STAMCOUNTER             StatFlushPhysPageManual;
 
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    STAMCOUNTER             StatFlushTLB;
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    STAMCOUNTER             StatFlushTLBManual;
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    STAMCOUNTER             StatFlushPageInvlpg;
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    STAMCOUNTER             StatFlushTLBWorldSwitch;