36
36
* 0xe000_0000 0xe000_ffff CCSR 1M
37
37
* 0xe200_0000 0xe27f_ffff PCI1 IO 8M
38
38
* 0xe280_0000 0xe2ff_ffff PCIe IO 8M
39
* 0xec00_0000 0xefff_ffff FLASH (2nd bank) 64M
39
40
* 0xf000_0000 0xf7ff_ffff SDRAM 128M
40
41
* 0xf8b0_0000 0xf80f_ffff EEPROM 1M
41
* 0xfb80_0000 0xff7f_ffff FLASH (2nd bank) 64M
42
42
* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
44
* If swapped CS0/CS6 via JP12+SW2.8:
45
* 0xef80_0000 0xefff_ffff FLASH (2nd bank) 8M
46
* 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M
45
49
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
46
50
* If flash is 8M at default position (last 8M), no LAW needed.
49
53
struct law_entry law_table[] = {
54
#ifdef CONFIG_SYS_ALT_BOOT
55
SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
57
SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
50
59
#ifndef CONFIG_SPD_EEPROM
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60
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
62
#ifdef CONFIG_SYS_LBC_SDRAM_BASE
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63
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
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64
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
66
/* LBC window - maps 128M 0xf8000000 -> 0xffffffff */
67
SET_LAW(CONFIG_SYS_EPLD_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
57
71
int num_law_entries = ARRAY_SIZE(law_table);