37
37
to reflect a different CCB:SYSCLK ratio]
39
39
The third option builds PCI support in, and leaves the clocking at the
40
default 66MHz. Options four and five are just repeats of option two
40
default 66MHz. Options four and five are just repeats of option two
41
41
and three, but with PCI-e support enabled as well.
43
43
PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx
44
is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with
44
is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with
45
45
a 33MHz PCI configuration is currently untested.)
48
48
Scanning PCI devices on bus 0
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BusDevFun VendorId DeviceId Device Class Sub-Class
49
BusDevFun VendorId DeviceId Device Class Sub-Class
50
50
_____________________________________________________________
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00.00.00 0x1057 0x0012 Processor 0x20
52
00.01.00 0x8086 0x1026 Network controller 0x00
51
00.00.00 0x1057 0x0012 Processor 0x20
52
00.01.00 0x8086 0x1026 Network controller 0x00
54
54
Scanning PCI devices on bus 1
55
BusDevFun VendorId DeviceId Device Class Sub-Class
55
BusDevFun VendorId DeviceId Device Class Sub-Class
56
56
_____________________________________________________________
57
01.00.00 0x1957 0x0012 Processor 0x20
57
01.00.00 0x1957 0x0012 Processor 0x20
59
59
Scanning PCI devices on bus 2
60
BusDevFun VendorId DeviceId Device Class Sub-Class
60
BusDevFun VendorId DeviceId Device Class Sub-Class
61
61
_____________________________________________________________
62
02.00.00 0x1148 0x9e00 Network controller 0x00
62
02.00.00 0x1148 0x9e00 Network controller 0x00
65
Memory Size and using SPD:
66
==========================
68
The default configuration uses hard coded memory configuration settings
69
for 256MB of DDR2 @400MHz. It does not by default use the DDR2 SPD
70
EEPROM data to read what memory is installed.
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There is a hardware errata, which causes the older local bus SDRAM
73
SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so
74
that the SPD data can not be read reliably. You can test if your
75
board has the errata fix by running "i2c probe". If you see 0x53
76
as a valid device, it has been fixed. If you only see 0x50, 0x51
77
then your board does not have the fix.
79
You can also visually inspect the board to see if this hardware
82
1) Remove R314 (RES-R0174-033, 1K, 0603). R314 is located on
83
the back of the PCB behind the DDR SDRAM SODIMM connector.
84
2) Solder RES-R0174-033 (1K, 0603) resistor from R314 pin 2 pad
85
to R313 pin 2. Pin 2 for each resistor is the end of the
86
resistor closest to the CPU.
88
Boards without the mod will have R314 and R313 in parallel, like "||".
89
After the mod, they will be touching and form an "L" shape.
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If you want to upgrade to larger RAM size, you can simply enable
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#define CONFIG_SPD_EEPROM
93
#define CONFIG_DDR_SPD
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in include/configs/sbc8548.h file. (The lines are already there
95
but listed as #undef).
97
If you did the i2c test, and your board does not have the errata
98
fix, then you will have to physically remove the LBC 128MB DIMM
99
from the board's socket to resolve the above i2c address overlap
100
issue and allow SPD autodetection of RAM to work.
66
103
Updating U-boot with U-boot:
67
104
============================
86
123
you to confirm the u-boot version that was downloaded, and then confirm
87
124
that it was copied to flash.
126
The above assumes that you are using the default board settings which
127
have u-boot in the 8MB flash, tied to /CS0.
129
If you are running the default 8MB /CS0 settings but want to store an
130
image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled,
131
(as a backup, etc) then the steps will become:
136
era eff00000 efffffff
137
cp.b 200000 eff00000 100000
141
Finally, if you are running the alternate 64MB /CS0 settings and want
142
to update the in-use u-boot image, then (again with CONFIG_SYS_ALT_BOOT
143
enabled) the steps will become:
148
era fff00000 ffffffff
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cp.b 200000 fff00000 100000
90
154
Hardware Reference:
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155
===================
93
157
The following contains some summary information on hardware settings
94
that are relevant to u-boot, based on the board manual. For the
158
that are relevant to u-boot, based on the board manual. For the
95
159
most up to date and complete details of the board, please request the
96
160
reference manual ERG-00327-001.pdf from www.windriver.com
124
191
onto /CS0 and the SODIMM flash on /CS6 (default). When JP12
125
192
is jumpered parallel to the LBC-SDRAM, then /CS0 is for the
126
193
SODIMM flash and /CS6 is for the boot flash. Note that in this
127
alternate setting, you also need to switch SW2.8 to ON. Currently
128
u-boot doesn't support booting off the SODIMM in this alternate
129
setting without manually altering BR0/OR0 and BR6/OR6 in the
130
board config file appropriately.
194
alternate setting, you also need to switch SW2.8 to ON.
195
See the setting CONFIG_SYS_ALT_BOOT if you want to use this setting
196
and boot u-boot from the 64MB SODIMM
187
253
0000_0000 0fff_ffff MCS0,1 64 DDR2 (256MB)
188
254
f000_0000 f7ff_ffff CS3,4 32 LB SDRAM (128MB)
189
255
f800_0000 f8b0_1fff CS5 - EPLD
190
fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB)
256
fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) [*]
191
257
ff80_0000 ffff_ffff CS0 8 Boot flash (8MB)
259
[*] fb80 represents the default programmed by WR JTAG register files,
260
but u-boot places the flash at either ec00 or fc00 based on JP12.
193
262
The EPLD on CS5 demuxes the following devices at the following offsets:
195
264
offset size width device
added
removed
doc/README.sbc8548
