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* Copyright Ericsson AB 2010. All Rights Reserved.
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* The contents of this file are subject to the Erlang Public License,
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* Version 1.1, (the "License"); you may not use this file except in
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* compliance with the License. You should have received a copy of the
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* Erlang Public License along with this software. If not, it can be
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* retrieved online at http://www.erlang.org/.
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* Software distributed under the License is distributed on an "AS IS"
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* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
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* the License for the specific language governing rights and limitations
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* Description: Native atomics ethread support using gcc's builtins
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* Author: Rickard Green
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#undef ETHR_INCLUDE_ATOMIC_IMPL__
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#if !defined(ETHR_GCC_ATOMIC32_H__) && defined(ETHR_ATOMIC_WANT_32BIT_IMPL__)
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#define ETHR_GCC_ATOMIC32_H__
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#define ETHR_INCLUDE_ATOMIC_IMPL__ 4
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#undef ETHR_ATOMIC_WANT_32BIT_IMPL__
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#elif !defined(ETHR_GCC_ATOMIC64_H__) && defined(ETHR_ATOMIC_WANT_64BIT_IMPL__)
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#define ETHR_GCC_ATOMIC64_H__
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#define ETHR_INCLUDE_ATOMIC_IMPL__ 8
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#undef ETHR_ATOMIC_WANT_64BIT_IMPL__
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#ifdef ETHR_INCLUDE_ATOMIC_IMPL__
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#ifndef ETHR_GCC_ATOMIC_COMMON__
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#define ETHR_GCC_ATOMIC_COMMON__
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#define ETHR_READ_AND_SET_WITHOUT_SYNC_OP__ 0
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#if defined(__i386__) || defined(__x86_64__) || defined(__sparc__) \
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|| defined(__powerpc__) || defined(__ppc__) || defined(__mips__)
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# undef ETHR_READ_AND_SET_WITHOUT_SYNC_OP__
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# define ETHR_READ_AND_SET_WITHOUT_SYNC_OP__ 1
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#if defined(__x86_64__) || (defined(__i386__) \
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&& !defined(ETHR_PRE_PENTIUM4_COMPAT))
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# define ETHR_READ_ACQB_AND_SET_RELB_COMPILER_BARRIER_ONLY__ 1
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# define ETHR_READ_ACQB_AND_SET_RELB_COMPILER_BARRIER_ONLY__ 0
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* According to the documentation this is what we want:
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* #define ETHR_MEMORY_BARRIER __sync_synchronize()
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* However, __sync_synchronize() is known to erroneously be
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* a noop on at least some platforms with some gcc versions.
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* This has suposedly been fixed in some gcc version, but we
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* don't know from which version. Therefore, we only use
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* it when it has been verified to work. Otherwise
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* we use a workaround.
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#if defined(__mips__) && (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 2))
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/* __sync_synchronize() has been verified to work here */
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#define ETHR_MEMORY_BARRIER __sync_synchronize()
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#define ETHR_READ_DEPEND_MEMORY_BARRIER __sync_synchronize()
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#elif defined(__x86_64__) || (defined(__i386__) \
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&& !defined(ETHR_PRE_PENTIUM4_COMPAT))
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/* Use fence instructions directly instead of workaround */
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#define ETHR_MEMORY_BARRIER __asm__ __volatile__("mfence" : : : "memory")
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#define ETHR_WRITE_MEMORY_BARRIER __asm__ __volatile__("sfence" : : : "memory")
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#define ETHR_READ_MEMORY_BARRIER __asm__ __volatile__("lfence" : : : "memory")
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#define ETHR_READ_DEPEND_MEMORY_BARRIER __asm__ __volatile__("" : : : "memory")
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#define ETHR_MEMORY_BARRIER \
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volatile ethr_sint32_t x___ = 0; \
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(void) __sync_val_compare_and_swap(&x___, (ethr_sint32_t) 0, (ethr_sint32_t) 1); \
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#define ETHR_READ_DEPEND_MEMORY_BARRIER ETHR_MEMORY_BARRIER
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#define ETHR_COMPILER_BARRIER __asm__ __volatile__("" : : : "memory")
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#endif /* ETHR_GCC_ATOMIC_COMMON__ */
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#if ETHR_INCLUDE_ATOMIC_IMPL__ == 4
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#define ETHR_HAVE_NATIVE_ATOMIC32 1
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#define ETHR_NATMC_FUNC__(X) ethr_native_atomic32_ ## X
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#define ETHR_ATMC_T__ ethr_native_atomic32_t
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#define ETHR_AINT_T__ ethr_sint32_t
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#elif ETHR_INCLUDE_ATOMIC_IMPL__ == 8
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#define ETHR_HAVE_NATIVE_ATOMIC64 1
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#define ETHR_NATMC_FUNC__(X) ethr_native_atomic64_ ## X
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#define ETHR_ATMC_T__ ethr_native_atomic64_t
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#define ETHR_AINT_T__ ethr_sint64_t
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#error "Unsupported integer size"
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volatile ETHR_AINT_T__ counter;
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#if defined(ETHR_TRY_INLINE_FUNCS) || defined(ETHR_ATOMIC_IMPL__)
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static ETHR_INLINE ETHR_AINT_T__ *
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ETHR_NATMC_FUNC__(addr)(ETHR_ATMC_T__ *var)
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return (ETHR_AINT_T__ *) &var->counter;
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static ETHR_INLINE void
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ETHR_NATMC_FUNC__(set)(ETHR_ATMC_T__ *var, ETHR_AINT_T__ value)
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#if ETHR_READ_AND_SET_WITHOUT_SYNC_OP__
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var->counter = value;
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* Unfortunately no __sync_store() or similar exist in the gcc atomic
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* op interface. We therefore have to simulate it this way...
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ETHR_AINT_T__ act = 0, exp;
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act = __sync_val_compare_and_swap(&var->counter, exp, value);
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} while (act != exp);
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static ETHR_INLINE void
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ETHR_NATMC_FUNC__(init)(ETHR_ATMC_T__ *var, ETHR_AINT_T__ value)
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ETHR_NATMC_FUNC__(set)(var, value);
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static ETHR_INLINE ETHR_AINT_T__
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ETHR_NATMC_FUNC__(read)(ETHR_ATMC_T__ *var)
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#if ETHR_READ_AND_SET_WITHOUT_SYNC_OP__
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* Unfortunately no __sync_fetch() or similar exist in the gcc atomic
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* op interface. We therefore have to simulate it this way...
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return __sync_add_and_fetch(&var->counter, (ETHR_AINT_T__) 0);
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static ETHR_INLINE void
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ETHR_NATMC_FUNC__(add)(ETHR_ATMC_T__ *var, ETHR_AINT_T__ incr)
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(void) __sync_add_and_fetch(&var->counter, incr);
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static ETHR_INLINE ETHR_AINT_T__
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ETHR_NATMC_FUNC__(add_return)(ETHR_ATMC_T__ *var, ETHR_AINT_T__ incr)
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return __sync_add_and_fetch(&var->counter, incr);
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static ETHR_INLINE void
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ETHR_NATMC_FUNC__(inc)(ETHR_ATMC_T__ *var)
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(void) __sync_add_and_fetch(&var->counter, (ETHR_AINT_T__) 1);
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static ETHR_INLINE void
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ETHR_NATMC_FUNC__(dec)(ETHR_ATMC_T__ *var)
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(void) __sync_sub_and_fetch(&var->counter, (ETHR_AINT_T__) 1);
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static ETHR_INLINE ETHR_AINT_T__
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ETHR_NATMC_FUNC__(inc_return)(ETHR_ATMC_T__ *var)
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return __sync_add_and_fetch(&var->counter, (ETHR_AINT_T__) 1);
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static ETHR_INLINE ETHR_AINT_T__
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ETHR_NATMC_FUNC__(dec_return)(ETHR_ATMC_T__ *var)
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return __sync_sub_and_fetch(&var->counter, (ETHR_AINT_T__) 1);
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static ETHR_INLINE ETHR_AINT_T__
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ETHR_NATMC_FUNC__(and_retold)(ETHR_ATMC_T__ *var, ETHR_AINT_T__ mask)
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return __sync_fetch_and_and(&var->counter, mask);
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static ETHR_INLINE ETHR_AINT_T__
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ETHR_NATMC_FUNC__(or_retold)(ETHR_ATMC_T__ *var, ETHR_AINT_T__ mask)
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return (ETHR_AINT_T__) __sync_fetch_and_or(&var->counter, mask);
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static ETHR_INLINE ETHR_AINT_T__
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ETHR_NATMC_FUNC__(cmpxchg)(ETHR_ATMC_T__ *var,
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return __sync_val_compare_and_swap(&var->counter, old, new);
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static ETHR_INLINE ETHR_AINT_T__
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ETHR_NATMC_FUNC__(xchg)(ETHR_ATMC_T__ *var, ETHR_AINT_T__ new)
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ETHR_AINT_T__ exp, act = 0;
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act = __sync_val_compare_and_swap(&var->counter, exp, new);
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} while (act != exp);
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* Atomic ops with at least specified barriers.
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static ETHR_INLINE ETHR_AINT_T__
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ETHR_NATMC_FUNC__(read_acqb)(ETHR_ATMC_T__ *var)
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#if ETHR_READ_ACQB_AND_SET_RELB_COMPILER_BARRIER_ONLY__
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ETHR_AINT_T__ val = var->counter;
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ETHR_COMPILER_BARRIER;
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return __sync_add_and_fetch(&var->counter, (ETHR_AINT_T__) 0);
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static ETHR_INLINE void
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ETHR_NATMC_FUNC__(set_relb)(ETHR_ATMC_T__ *var, ETHR_AINT_T__ i)
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#if ETHR_READ_ACQB_AND_SET_RELB_COMPILER_BARRIER_ONLY__
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ETHR_COMPILER_BARRIER;
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(void) ETHR_NATMC_FUNC__(xchg)(var, i);
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static ETHR_INLINE ETHR_AINT_T__
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ETHR_NATMC_FUNC__(inc_return_acqb)(ETHR_ATMC_T__ *var)
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return ETHR_NATMC_FUNC__(inc_return)(var);
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static ETHR_INLINE void
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ETHR_NATMC_FUNC__(dec_relb)(ETHR_ATMC_T__ *var)
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ETHR_NATMC_FUNC__(dec)(var);
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static ETHR_INLINE ETHR_AINT_T__
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ETHR_NATMC_FUNC__(dec_return_relb)(ETHR_ATMC_T__ *var)
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return ETHR_NATMC_FUNC__(dec_return)(var);
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static ETHR_INLINE ETHR_AINT_T__
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ETHR_NATMC_FUNC__(cmpxchg_acqb)(ETHR_ATMC_T__ *var,
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return ETHR_NATMC_FUNC__(cmpxchg)(var, new, old);
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static ETHR_INLINE ETHR_AINT_T__
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ETHR_NATMC_FUNC__(cmpxchg_relb)(ETHR_ATMC_T__ *var,
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return ETHR_NATMC_FUNC__(cmpxchg)(var, new, old);
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#undef ETHR_NATMC_FUNC__
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#undef ETHR_AINT_SUFFIX__