58
58
/// LegalizedNodes - The set of nodes which have already been legalized.
59
59
SmallPtrSet<SDNode *, 16> LegalizedNodes;
61
EVT getSetCCResultType(EVT VT) const {
62
return TLI.getSetCCResultType(*DAG.getContext(), VT);
61
65
// Libcall insertion helpers.
79
83
/// is necessary to spill the vector being inserted into to memory, perform
80
84
/// the insert there, and then read the result back.
81
85
SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
82
SDValue Idx, DebugLoc dl);
86
SDValue Idx, SDLoc dl);
83
87
SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
84
SDValue Idx, DebugLoc dl);
88
SDValue Idx, SDLoc dl);
86
90
/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
87
91
/// performs the same shuffe in terms of order or result bytes, but on a type
88
92
/// whose vector element type is narrower than the original shuffle type.
89
93
/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
90
SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
94
SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
91
95
SDValue N1, SDValue N2,
92
96
ArrayRef<int> Mask) const;
94
98
void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
97
101
SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
98
102
SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
99
unsigned NumOps, bool isSigned, DebugLoc dl);
103
unsigned NumOps, bool isSigned, SDLoc dl);
101
105
std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
102
106
SDNode *Node, bool isSigned);
113
117
void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
114
118
void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
116
SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
120
SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
117
121
SDValue ExpandBUILD_VECTOR(SDNode *Node);
118
122
SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
119
123
void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
120
124
SmallVectorImpl<SDValue> &Results);
121
125
SDValue ExpandFCOPYSIGN(SDNode *Node);
122
126
SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
124
128
SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
126
130
SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
129
SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
130
SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
133
SDValue ExpandBSWAP(SDValue Op, SDLoc dl);
134
SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl);
132
136
SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
133
137
SDValue ExpandInsertToVectorThroughStack(SDValue Op);
181
185
/// whose vector element type is narrower than the original shuffle type.
182
186
/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
184
SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
188
SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
185
189
SDValue N1, SDValue N2,
186
190
ArrayRef<int> Mask) const {
187
191
unsigned NumMaskElts = VT.getVectorNumElements();
248
252
SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
249
253
bool Extend = false;
250
DebugLoc dl = CFP->getDebugLoc();
252
256
// If a FP immediate is precise when represented as a float and if the
253
257
// target can do an extending load from float to double, we put it into
307
311
SDValue Val = ST->getValue();
308
312
EVT VT = Val.getValueType();
309
313
int Alignment = ST->getAlignment();
310
DebugLoc dl = ST->getDebugLoc();
311
315
if (ST->getMemoryVT().isFloatingPoint() ||
312
316
ST->getMemoryVT().isVector()) {
313
317
EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
428
432
SDValue Ptr = LD->getBasePtr();
429
433
EVT VT = LD->getValueType(0);
430
434
EVT LoadedVT = LD->getMemoryVT();
431
DebugLoc dl = LD->getDebugLoc();
432
436
if (VT.isFloatingPoint() || VT.isVector()) {
433
437
EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
434
438
if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
570
574
/// the insert there, and then read the result back.
571
575
SDValue SelectionDAGLegalize::
572
576
PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
574
578
SDValue Tmp1 = Vec;
575
579
SDValue Tmp2 = Val;
576
580
SDValue Tmp3 = Idx;
614
618
SDValue SelectionDAGLegalize::
615
ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
619
ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) {
616
620
if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
617
621
// SCALAR_TO_VECTOR requires that the type of the value being inserted
618
622
// match the element type of the vector being created, except for
651
655
unsigned Alignment = ST->getAlignment();
652
656
bool isVolatile = ST->isVolatile();
653
657
bool isNonTemporal = ST->isNonTemporal();
654
DebugLoc dl = ST->getDebugLoc();
655
659
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
656
660
if (CFP->getValueType(0) == MVT::f32 &&
657
661
TLI.isTypeLegal(MVT::i32)) {
699
703
StoreSDNode *ST = cast<StoreSDNode>(Node);
700
704
SDValue Chain = ST->getChain();
701
705
SDValue Ptr = ST->getBasePtr();
702
DebugLoc dl = Node->getDebugLoc();
704
708
unsigned Alignment = ST->getAlignment();
705
709
bool isVolatile = ST->isVolatile();
863
867
SDValue Chain = LD->getChain(); // The chain.
864
868
SDValue Ptr = LD->getBasePtr(); // The base pointer.
865
869
SDValue Value; // The value returned by the load op.
866
DebugLoc dl = Node->getDebugLoc();
868
872
ISD::LoadExtType ExtType = LD->getExtensionType();
869
873
if (ExtType == ISD::NON_EXTLOAD) {
1249
1253
if (Action == TargetLowering::Expand) {
1250
1254
// replace ISD::DEBUGTRAP with ISD::TRAP
1251
1255
SDValue NewVal;
1252
NewVal = DAG.getNode(ISD::TRAP, Node->getDebugLoc(), Node->getVTList(),
1256
NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1253
1257
Node->getOperand(0));
1254
1258
ReplaceNode(Node, NewVal.getNode());
1255
1259
LegalizeOp(NewVal.getNode());
1370
1374
SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1371
1375
SDValue Vec = Op.getOperand(0);
1372
1376
SDValue Idx = Op.getOperand(1);
1373
DebugLoc dl = Op.getDebugLoc();
1374
1378
// Store the value to a temporary stack slot, then LOAD the returned part.
1375
1379
SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1376
1380
SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1404
1408
SDValue Vec = Op.getOperand(0);
1405
1409
SDValue Part = Op.getOperand(1);
1406
1410
SDValue Idx = Op.getOperand(2);
1407
DebugLoc dl = Op.getDebugLoc();
1409
1413
// Store the value to a temporary stack slot, then LOAD the returned part.
1449
1453
// Create the stack frame object.
1450
1454
EVT VT = Node->getValueType(0);
1451
1455
EVT EltVT = VT.getVectorElementType();
1452
DebugLoc dl = Node->getDebugLoc();
1453
1457
SDValue FIPtr = DAG.CreateStackTemporary(VT);
1454
1458
int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1455
1459
MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1544
1548
// Now get the sign bit proper, by seeing whether the value is negative.
1545
SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1549
SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()),
1546
1550
SignBit, DAG.getConstant(0, SignBit.getValueType()),
1548
1552
// Get the absolute value of the result.
1559
1563
unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1560
1564
assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1561
1565
" not tell us which reg is the stack pointer!");
1562
DebugLoc dl = Node->getDebugLoc();
1563
1567
EVT VT = Node->getValueType(0);
1564
1568
SDValue Tmp1 = SDValue(Node, 0);
1565
1569
SDValue Tmp2 = SDValue(Node, 1);
1594
1598
void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1595
1599
SDValue &LHS, SDValue &RHS,
1598
1602
MVT OpVT = LHS.getSimpleValueType();
1599
1603
ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1600
1604
switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1727
1731
SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1728
DebugLoc dl = Node->getDebugLoc();
1729
1733
// Create a vector sized/aligned stack slot, store the value to element #0,
1730
1734
// then load the whole vector back out.
1731
1735
SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1749
1753
SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1750
1754
unsigned NumElems = Node->getNumOperands();
1751
1755
SDValue Value1, Value2;
1752
DebugLoc dl = Node->getDebugLoc();
1753
1757
EVT VT = Node->getValueType(0);
1754
1758
EVT OpVT = Node->getOperand(0).getValueType();
1755
1759
EVT EltVT = VT.getVectorElementType();
1881
1885
CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1882
1886
0, TLI.getLibcallCallingConv(LC), isTailCall,
1883
1887
/*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1884
Callee, Args, DAG, Node->getDebugLoc());
1888
Callee, Args, DAG, SDLoc(Node));
1885
1889
std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1896
1900
/// and returning a result of type RetVT.
1897
1901
SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
1898
1902
const SDValue *Ops, unsigned NumOps,
1899
bool isSigned, DebugLoc dl) {
1903
bool isSigned, SDLoc dl) {
1900
1904
TargetLowering::ArgListTy Args;
1901
1905
Args.reserve(NumOps);
1950
1954
CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1951
1955
0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
1952
1956
/*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1953
Callee, Args, DAG, Node->getDebugLoc());
1957
Callee, Args, DAG, SDLoc(Node));
1954
1958
std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1956
1960
return CallInfo;
2082
2086
SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2083
2087
TLI.getPointerTy());
2085
DebugLoc dl = Node->getDebugLoc();
2086
2090
TargetLowering::
2087
2091
CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2088
2092
0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2196
2200
SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2197
2201
TLI.getPointerTy());
2199
DebugLoc dl = Node->getDebugLoc();
2200
2204
TargetLowering::
2201
2205
CallLoweringInfo CLI(InChain, Type::getVoidTy(*DAG.getContext()),
2202
2206
false, false, false, false,
2327
2331
// select. We happen to get lucky and machinesink does the right
2328
2332
// thing most of the time. This would be a good candidate for a
2329
2333
//pseudo-op, or, even better, for whole-function isel.
2330
SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2334
SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2331
2335
Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2332
2336
return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast);
2340
2344
DAG.getConstant(UINT64_C(0x800), MVT::i64));
2341
2345
SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2342
2346
DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2343
SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2347
SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2344
2348
And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2345
2349
SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2346
SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2350
SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2347
2351
Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2349
2353
SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2366
2370
SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2368
SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2372
SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2369
2373
Op0, DAG.getConstant(0, Op0.getValueType()),
2371
2375
SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2495
2499
/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2497
SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2501
SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
2498
2502
EVT VT = Op.getValueType();
2499
2503
EVT SHVT = TLI.getShiftAmountTy(VT);
2500
2504
SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2723
2727
void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2724
2728
SmallVector<SDValue, 8> Results;
2725
DebugLoc dl = Node->getDebugLoc();
2726
2730
SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2727
2731
switch (Node->getOpcode()) {
2728
2732
case ISD::CTPOP:
2759
2763
Results.push_back(DAG.getConstant(0, MVT::i32));
2760
2764
Results.push_back(Node->getOperand(0));
2762
case ISD::ATOMIC_FENCE:
2763
case ISD::MEMBARRIER: {
2766
case ISD::ATOMIC_FENCE: {
2764
2767
// If the target didn't lower this, lower it to '__sync_synchronize()' call
2765
2768
// FIXME: handle "fence singlethread" more efficiently.
2766
2769
TargetLowering::ArgListTy Args;
2914
2917
APInt x = APInt::getSignBit(NVT.getSizeInBits());
2915
2918
(void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2916
2919
Tmp1 = DAG.getConstantFP(apf, VT);
2917
Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2920
Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
2918
2921
Node->getOperand(0),
2919
2922
Tmp1, ISD::SETLT);
2920
2923
True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3132
3135
EVT VT = Node->getValueType(0);
3133
3136
Tmp1 = Node->getOperand(0);
3134
3137
Tmp2 = DAG.getConstantFP(0.0, VT);
3135
Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3138
Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()),
3136
3139
Tmp1, Tmp2, ISD::SETUGT);
3137
3140
Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3138
3141
Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
3529
3532
Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3530
3533
TLI.getShiftAmountTy(BottomHalf.getValueType()));
3531
3534
Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3532
TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3535
TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3535
TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3538
TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3536
3539
DAG.getConstant(0, VT), ISD::SETNE);
3538
3541
Results.push_back(BottomHalf);
3655
3658
Tmp4 = Node->getOperand(3); // False
3656
3659
SDValue CC = Node->getOperand(4);
3658
LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
3661
LegalizeSetCCCondCode(getSetCCResultType(Tmp1.getValueType()),
3659
3662
Tmp1, Tmp2, CC, dl);
3661
3664
assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
3672
3675
Tmp3 = Node->getOperand(3); // RHS
3673
3676
Tmp4 = Node->getOperand(1); // CC
3675
LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
3678
LegalizeSetCCCondCode(getSetCCResultType(Tmp2.getValueType()),
3676
3679
Tmp2, Tmp3, Tmp4, dl);
3678
3681
assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
3739
3742
OVT = Node->getOperand(0).getSimpleValueType();
3741
3744
MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3742
DebugLoc dl = Node->getDebugLoc();
3743
3746
SDValue Tmp1, Tmp2, Tmp3;
3744
3747
switch (Node->getOpcode()) {
3745
3748
case ISD::CTTZ:
3754
3757
Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3755
3758
if (Node->getOpcode() == ISD::CTTZ) {
3756
3759
// FIXME: This should set a bit in the zero extended value instead.
3757
Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
3760
Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
3758
3761
Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3760
3763
Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,