1270
1270
<< "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC)\n"
1271
1271
<< " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
1272
1272
<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
1274
1276
<< " InitMCRegisterInfo(" << TargetName << "RegDesc, "
1275
1277
<< Regs.size()+1 << ", RA, PC,\n " << TargetName
1276
1278
<< "MCRegisterClasses, " << RegisterClasses.size() << ",\n"