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; Test 32-bit floating-point comparison.
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Check comparison with registers.
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define i64 @f1(i64 %a, i64 %b, float %f1, float %f2) {
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%cond = fcmp oeq float %f1, %f2
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%res = select i1 %cond, i64 %a, i64 %b
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; Check the low end of the CEB range.
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define i64 @f2(i64 %a, i64 %b, float %f1, float *%ptr) {
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; CHECK: ceb %f0, 0(%r4)
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%f2 = load float *%ptr
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%cond = fcmp oeq float %f1, %f2
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%res = select i1 %cond, i64 %a, i64 %b
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; Check the high end of the aligned CEB range.
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define i64 @f3(i64 %a, i64 %b, float %f1, float *%base) {
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; CHECK: ceb %f0, 4092(%r4)
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%ptr = getelementptr float *%base, i64 1023
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%f2 = load float *%ptr
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%cond = fcmp oeq float %f1, %f2
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%res = select i1 %cond, i64 %a, i64 %b
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f4(i64 %a, i64 %b, float %f1, float *%base) {
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; CHECK: aghi %r4, 4096
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; CHECK: ceb %f0, 0(%r4)
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%ptr = getelementptr float *%base, i64 1024
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%f2 = load float *%ptr
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%cond = fcmp oeq float %f1, %f2
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%res = select i1 %cond, i64 %a, i64 %b
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; Check negative displacements, which also need separate address logic.
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define i64 @f5(i64 %a, i64 %b, float %f1, float *%base) {
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; CHECK: ceb %f0, 0(%r4)
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%ptr = getelementptr float *%base, i64 -1
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%f2 = load float *%ptr
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%cond = fcmp oeq float %f1, %f2
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%res = select i1 %cond, i64 %a, i64 %b
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; Check that CEB allows indices.
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define i64 @f6(i64 %a, i64 %b, float %f1, float *%base, i64 %index) {
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; CHECK: sllg %r1, %r5, 2
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; CHECK: ceb %f0, 400(%r1,%r4)
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%ptr1 = getelementptr float *%base, i64 %index
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%ptr2 = getelementptr float *%ptr1, i64 100
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%f2 = load float *%ptr2
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%cond = fcmp oeq float %f1, %f2
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%res = select i1 %cond, i64 %a, i64 %b