128
133
case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
129
134
case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
130
135
case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
131
case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true, DAG);
136
case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
132
138
case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
133
139
case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
314
320
return SDValue();
323
static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
325
const MipsSubtarget *Subtarget) {
326
// See if this is a vector splat immediate node.
327
APInt SplatValue, SplatUndef;
328
unsigned SplatBitSize;
330
unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
331
BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
334
!BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
335
EltSize, !Subtarget->isLittle()) ||
336
(SplatBitSize != EltSize) ||
337
(SplatValue.getZExtValue() >= EltSize))
340
return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
341
DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
344
static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
345
TargetLowering::DAGCombinerInfo &DCI,
346
const MipsSubtarget *Subtarget) {
347
EVT Ty = N->getValueType(0);
349
if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
352
return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
355
static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
356
TargetLowering::DAGCombinerInfo &DCI,
357
const MipsSubtarget *Subtarget) {
358
EVT Ty = N->getValueType(0);
360
if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
363
return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
367
static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
368
TargetLowering::DAGCombinerInfo &DCI,
369
const MipsSubtarget *Subtarget) {
370
EVT Ty = N->getValueType(0);
372
if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
375
return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
378
static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
379
bool IsV216 = (Ty == MVT::v2i16);
383
case ISD::SETNE: return true;
387
case ISD::SETGE: return IsV216;
391
case ISD::SETUGE: return !IsV216;
392
default: return false;
396
static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
397
EVT Ty = N->getValueType(0);
399
if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
402
if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
405
return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
406
N->getOperand(1), N->getOperand(2));
409
static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
410
EVT Ty = N->getValueType(0);
412
if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
415
SDValue SetCC = N->getOperand(0);
417
if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
420
return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
421
SetCC.getOperand(0), SetCC.getOperand(1), N->getOperand(1),
422
N->getOperand(2), SetCC.getOperand(2));
318
426
MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
319
427
SelectionDAG &DAG = DCI.DAG;
321
430
switch (N->getOpcode()) {
323
432
return performADDECombine(N, DAG, DCI, Subtarget);
325
434
return performSUBECombine(N, DAG, DCI, Subtarget);
327
return MipsTargetLowering::PerformDAGCombine(N, DCI);
436
return performSHLCombine(N, DAG, DCI, Subtarget);
438
return performSRACombine(N, DAG, DCI, Subtarget);
440
return performSRLCombine(N, DAG, DCI, Subtarget);
442
return performVSELECTCombine(N, DAG);
444
Val = performSETCCCombine(N, DAG);
452
return MipsTargetLowering::PerformDAGCombine(N, DCI);
331
455
MachineBasicBlock *