30
30
SDTCisVT<2, i32>]>;
31
31
def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
32
32
SDTCisSameAs<1, 2>]>;
33
def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>;
33
34
def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
35
36
SDTCisSameAs<1, 2>]>;
42
43
def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
43
44
def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
44
45
[SDNPHasChain, SDNPOptInGlue]>;
46
def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>;
45
47
def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
46
48
def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
47
49
SDT_MipsExtractElementF64>;
154
156
InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
155
157
[(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI> {
156
158
let DecoderMethod = "DecodeFMem";
159
162
class SW_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
161
164
InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
162
165
[(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI> {
163
166
let DecoderMethod = "DecodeFMem";
166
170
class MADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
253
257
let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
254
def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 17>;
255
def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 21>;
256
def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
257
def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
258
def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64, FGR64, IIFcvt>, ABSS_FM<0x21, 21>;
258
def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 17>;
259
def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 21>;
260
def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
261
def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
262
def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64, FGR64, IIFcvt>, ABSS_FM<0x21, 21>;
265
let isPseudo = 1, isCodeGenOnly = 1 in {
266
def PseudoCVT_S_W : ABSS_FT<"", FGR32, CPURegs, IIFcvt>;
267
def PseudoCVT_D32_W : ABSS_FT<"", AFGR64, CPURegs, IIFcvt>;
268
def PseudoCVT_S_L : ABSS_FT<"", FGR64, CPU64Regs, IIFcvt>;
269
def PseudoCVT_D64_W : ABSS_FT<"", FGR64, CPURegs, IIFcvt>;
270
def PseudoCVT_D64_L : ABSS_FT<"", FGR64, CPU64Regs, IIFcvt>;
261
273
let Predicates = [NoNaNsFPMath, HasStdEnc] in {
316
328
let Predicates = [NotN64, NotMips64, HasStdEnc] in {
317
def LDC1 : LW_FT<"ldc1", AFGR64, IILoad, mem, load>, LW_FM<0x35>;
318
def SDC1 : SW_FT<"sdc1", AFGR64, IIStore, mem, store>, LW_FM<0x3d>;
329
let isPseudo = 1, isCodeGenOnly = 1 in {
330
def PseudoLDC1 : LW_FT<"", AFGR64, IILoad, mem, load>;
331
def PseudoSDC1 : SW_FT<"", AFGR64, IIStore, mem, store>;
333
def LDC1 : LW_FT<"ldc1", AFGR64, IILoad, mem>, LW_FM<0x35>;
334
def SDC1 : SW_FT<"sdc1", AFGR64, IIStore, mem>, LW_FM<0x3d>;
321
337
// Indexed loads and stores.
470
486
def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
471
487
def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
473
def : MipsPat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
474
def : MipsPat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>;
489
def : MipsPat<(f32 (sint_to_fp CPURegs:$src)), (PseudoCVT_S_W CPURegs:$src)>;
490
def : MipsPat<(MipsTruncIntFP FGR32:$src), (TRUNC_W_S FGR32:$src)>;
476
492
let Predicates = [NotFP64bit, HasStdEnc] in {
477
493
def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
478
(CVT_D32_W (MTC1 CPURegs:$src))>;
479
def : MipsPat<(i32 (fp_to_sint AFGR64:$src)),
480
(MFC1 (TRUNC_W_D32 AFGR64:$src))>;
494
(PseudoCVT_D32_W CPURegs:$src)>;
495
def : MipsPat<(MipsTruncIntFP AFGR64:$src), (TRUNC_W_D32 AFGR64:$src)>;
481
496
def : MipsPat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>;
482
497
def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>;
487
502
def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
489
504
def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
490
(CVT_D64_W (MTC1 CPURegs:$src))>;
505
(PseudoCVT_D64_W CPURegs:$src)>;
491
506
def : MipsPat<(f32 (sint_to_fp CPU64Regs:$src)),
492
(CVT_S_L (DMTC1 CPU64Regs:$src))>;
507
(EXTRACT_SUBREG (PseudoCVT_S_L CPU64Regs:$src), sub_32)>;
493
508
def : MipsPat<(f64 (sint_to_fp CPU64Regs:$src)),
494
(CVT_D64_L (DMTC1 CPU64Regs:$src))>;
509
(PseudoCVT_D64_L CPU64Regs:$src)>;
496
def : MipsPat<(i32 (fp_to_sint FGR64:$src)),
497
(MFC1 (TRUNC_W_D64 FGR64:$src))>;
498
def : MipsPat<(i64 (fp_to_sint FGR32:$src)), (DMFC1 (TRUNC_L_S FGR32:$src))>;
499
def : MipsPat<(i64 (fp_to_sint FGR64:$src)),
500
(DMFC1 (TRUNC_L_D64 FGR64:$src))>;
511
def : MipsPat<(MipsTruncIntFP FGR64:$src), (TRUNC_W_D64 FGR64:$src)>;
512
def : MipsPat<(MipsTruncIntFP FGR32:$src), (TRUNC_L_S FGR32:$src)>;
513
def : MipsPat<(MipsTruncIntFP FGR64:$src), (TRUNC_L_D64 FGR64:$src)>;
502
515
def : MipsPat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>;
503
516
def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>;
525
538
let Predicates = [NotN64, NotMips64, HasStdEnc] in {
526
def : LoadRegImmPat<LDC1, f64, load>;
527
def : StoreRegImmPat<SDC1, f64>;
539
def : LoadRegImmPat<PseudoLDC1, f64, load>;
540
def : StoreRegImmPat<PseudoSDC1, f64>;