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/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#include "ctrlEnv/mvCtrlEnvSpec.h"
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#include "mvSysDdrConfig.h"
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#include "mvDramIfConfig.h"
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#include "mvDramIfRegs.h"
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#include "../mvDramIf.h"
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#warning "Fix this include...."
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#include "pmu/mvPmuRegs.h"
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#include <asm/setup.h>
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#if defined (CONFIG_PM) && defined (CONFIG_ARCH_DOVE)
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/* DDR speed to mask map table */
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MV_U32 ddr_freq_mask[][2] = {{100, MV_DDR_100},
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#define MV_DRAM_FREQ_MASK_CNT (sizeof(ddr_freq_mask)/sizeof(ddr_freq_mask[0]))
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/* Mandatory address decoding configurations */
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MV_DDR_MC_PARAMS dove_windows[]={{0xD0800010, 0xF1800000}, /* Set DDR register space */
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{0xD00D025C, 0x000F1890}, /* Set NB register space */
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{0xD0020080, 0xF1000000}, /* Set SB register space */
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#define MV_DRAM_ADDR_DEC_CNT (sizeof(dove_windows)/sizeof(dove_windows[0]))
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/* Mandatory DDR reconfig configurations */
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MV_DDR_MC_PARAMS ddr_reconfig[]={{0x00120, 0x03000100}, /* Load Mode Register */
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{0x00120, 0x03000200}, /* load Extended Mode Register */
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#define MV_DRAM_RECONFIG_CNT (sizeof(ddr_reconfig)/sizeof(ddr_reconfig[0]))
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extern MV_DRAM_INIT mv_dram_init_info;
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extern u32 mv_dram_init_valid;
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/*******************************************************************************
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* mvDramIfParamCountGet - Get the number of Addr/Value configuration needed
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* Get the number of Addr/Value configuration needed to init the DDR
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* Number of Address Value couples
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*******************************************************************************/
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MV_U32 mvDramIfParamCountGet(MV_VOID)
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if (!mv_dram_init_valid)
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mvOsPrintf("Warning: DRAM Initialization Parameters Not Found (Check Tags)!");
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/* scan all available frequencies and decide MAX parameters count */
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for (hdr = 0; hdr < MV_DRAM_HEADERS_CNT; hdr++) {
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if (mv_dram_init_info.dram_init_ctrl[hdr].freq_mask != 0) {
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if (mv_dram_init_info.dram_init_ctrl[hdr].size > cnt) {
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cnt = mv_dram_init_info.dram_init_ctrl[hdr].size;
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/* Add the FIXED count used for address decoding or reconfig; the bigger */
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if (MV_DRAM_ADDR_DEC_CNT > MV_DRAM_RECONFIG_CNT)
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cnt += MV_DRAM_ADDR_DEC_CNT;
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cnt += MV_DRAM_RECONFIG_CNT;
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/* Add 1 entry for the DLL reset clearing in DDR reconfig */
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/*******************************************************************************
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* mvDramIfParamFill - Fill in the Address/Value couples
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* This function fills in the addr/val couples needed to init the DDR
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* controller based on the requesed frequency
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* ddrFreq - Target frequency
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* params - pointer to the first addr/value element.
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* paramcnt - Number of paramters filled in the addr/value array.
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*******************************************************************************/
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MV_STATUS mvDramIfParamFill(MV_U32 ddrFreq, MV_DDR_MC_PARAMS * params, MV_U32 * paramcnt)
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MV_U32 reg_index, i, mask;
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/* Check that the Uboot passed valid parameters in the TAG */
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if (!mv_dram_init_valid) {
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mvOsPrintf("Warning: DRAM Initialization Parameters Not Found (Check Tags)!");
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/* Lookup the appropriate frequency mask */
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for (i=0; i<MV_DRAM_FREQ_MASK_CNT; i++) {
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if (ddr_freq_mask[i][0] == ddrFreq) {
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mask = ddr_freq_mask[i][1];
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/* Verify that the mask was found in the lookup table */
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if (i == MV_DRAM_FREQ_MASK_CNT) {
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/* Lookup the configurations entry in the table */
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for (i=0; i<MV_DRAM_HEADERS_CNT; i++) {
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if (mv_dram_init_info.dram_init_ctrl[i].freq_mask & mask) {
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reg_index = mv_dram_init_info.dram_init_ctrl[i].start_index;
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*paramcnt = mv_dram_init_info.dram_init_ctrl[i].size;
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/* Check if frequency is not available OR zero configurations */
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if ((i == MV_DRAM_HEADERS_CNT) || (*paramcnt == 0))
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/* First copy the address decoding PREFIX */
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for (i=0; i<MV_DRAM_ADDR_DEC_CNT; i++) {
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params->addr = dove_windows[i].addr;
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params->val = dove_windows[i].val;
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/* Copy the parameters in 32bit access */
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for (i=0; i<*paramcnt; i++) {
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params->addr = mv_dram_init_info.reg_init[reg_index].reg_addr;
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params->val = mv_dram_init_info.reg_init[reg_index].reg_value;
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/* Add the count of the Address decoding registers */
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*paramcnt += MV_DRAM_ADDR_DEC_CNT;
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/*******************************************************************************
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* mvDramReconfigParamFill - Fill in the Address/Value couples
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* This function fills in the addr/val couples needed to init the DDR
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* controller based on the requesed frequency
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* ddrFreq - Target frequency
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* cpuFreq - cpu frequency to calculate Timing against
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* params - pointer to the first addr/value element.
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* paramcnt - Number of paramters filled in the addr/value array.
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*******************************************************************************/
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MV_STATUS mvDramReconfigParamFill(MV_U32 ddrFreq, MV_U32 cpuFreq, MV_DDR_MC_PARAMS * params, MV_U32 * paramcnt)
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MV_U32 reg_index, i, mask;
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/* Check that the Uboot passed valid parameters in the TAG */
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if (!mv_dram_init_valid) {
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mvOsPrintf("Warning: DRAM Initialization Parameters Not Found (Check Tags)!");
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/* Lookup the appropriate frequency mask */
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for (i=0; i<MV_DRAM_FREQ_MASK_CNT; i++) {
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if (ddr_freq_mask[i][0] == ddrFreq) {
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mask = ddr_freq_mask[i][1];
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/* Verify that the mask was found in the lookup table */
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if (i == MV_DRAM_FREQ_MASK_CNT) {
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/* Lookup the configurations entry in the table */
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for (i=0; i<MV_DRAM_HEADERS_CNT; i++) {
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if (mv_dram_init_info.dram_init_ctrl[i].freq_mask & mask) {
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reg_index = mv_dram_init_info.dram_init_ctrl[i].start_index;
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*paramcnt = mv_dram_init_info.dram_init_ctrl[i].size;
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/* Check if frequency is not available OR zero configurations */
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if ((i == MV_DRAM_HEADERS_CNT) || (*paramcnt == 0))
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/* Drop the last line with the DDR init trigger - replaced with LMR and LEMR */
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/* Firt copy the parameters in 32bit access */
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for (i=0; i<*paramcnt; i++) {
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params->addr = (mv_dram_init_info.reg_init[reg_index].reg_addr & 0xFFFFF); /* offset only */
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params->val = mv_dram_init_info.reg_init[reg_index].reg_value;
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if (params->addr == 0x80)
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dll_rst = params->val;
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params->val |= 0x40; /* Add DLL reset */
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/* Finally add the DRAM reinit couples */
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for (i=0; i<MV_DRAM_RECONFIG_CNT; i++) {
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params->addr = ddr_reconfig[i].addr;
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params->val = ddr_reconfig[i].val;
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/* Add the DLL reset deasser */
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params->val = dll_rst;
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/* Add the count of LMR and LEMR registers count + DLL reset clearing */
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*paramcnt += (MV_DRAM_RECONFIG_CNT + 1);
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/*******************************************************************************
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* mvDramInitPollAmvFill - Fill in the Address/Value couples
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* This function fills in the addr/val couples needed to init the DDR
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* controller based on the requesed frequency
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* amv - address/mask/value for the DDR init done register.
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* amv->addr: Physical adddress of the init done register
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* amv->mask: Bit mask to poll for init done
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* amv->val: Value expected after the mask.
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*******************************************************************************/
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MV_STATUS mvDramInitPollAmvFill(MV_DDR_INIT_POLL_AMV * amv)
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amv->addr = (DOVE_SB_REGS_PHYS_BASE|SDRAM_STATUS_REG)/*mvOsIoVirtToPhy(NULL, (void*)(INTER_REGS_BASE|SDRAM_STATUS_REG))*/;
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amv->mask = SDRAM_STATUS_INIT_DONE_MASK;
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amv->val = SDRAM_STATUS_INIT_DONE;
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#endif /* #if defined (CONFIG_PM) && defined (CONFIG_ARCH_DOVE) */