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  • Committer: Bazaar Package Importer
  • Author(s): Stefan Bader
  • Date: 2010-03-10 22:24:12 UTC
  • mto: (15.1.2 karmic-security)
  • mto: This revision was merged to the branch mainline in revision 18.
  • Revision ID: james.westby@ubuntu.com-20100310222412-k86m3r53jw0je7x1
Tags: upstream-2.6.31
Import upstream version 2.6.31

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drivers/mtd/nand/dove_nand_hal.c
1
 
/*
2
 
 * drivers/mtd/nand/pxa3xx_nand.c
3
 
 *
4
 
 * Copyright c 2005 Intel Corporation
5
 
 * Copyright c 2006 Marvell International Ltd.
6
 
 *
7
 
 * This program is free software; you can redistribute it and/or modify
8
 
 * it under the terms of the GNU General Public License version 2 as
9
 
 * published by the Free Software Foundation.
10
 
 */
11
 
 
12
 
#include <linux/module.h>
13
 
#include <linux/interrupt.h>
14
 
#include <linux/platform_device.h>
15
 
#include <linux/dma-mapping.h>
16
 
#include <linux/delay.h>
17
 
#include <linux/clk.h>
18
 
#include <linux/mtd/mtd.h>
19
 
#include <linux/mtd/nand.h>
20
 
#include <linux/mtd/partitions.h>
21
 
#include <linux/io.h>
22
 
#include <linux/irq.h>
23
 
#include <asm/dma.h>
24
 
 
25
 
#include <mach/dove_nand.h>
26
 
#include <asm/hardware/pxa-dma.h>
27
 
 
28
 
#include "mvCommon.h"
29
 
#include "mvOs.h"
30
 
#include "pdma/mvPdma.h"
31
 
#include "pdma/mvPdmaRegs.h"
32
 
#include "nfc/mvNfc.h"
33
 
#include "nfc/mvNfcRegs.h"
34
 
 
35
 
#define NFC_DPRINT(x) /*printk x*/
36
 
 
37
 
#define CHIP_DELAY_TIMEOUT      (20 * HZ/10)
38
 
 
39
 
#define NFC_SR_MASK             (0xfff)
40
 
#define NFC_SR_BBD_MASK         (NFC_SR_CS0_BBD_MASK | NFC_SR_CS1_BBD_MASK)
41
 
 
42
 
/* error code and state */
43
 
enum {
44
 
        ERR_NONE        = 0,
45
 
        ERR_DMABUSERR   = -1,
46
 
        ERR_SENDCMD     = -2,
47
 
        ERR_DBERR       = -3,
48
 
        ERR_BBERR       = -4,
49
 
};
50
 
 
51
 
enum {
52
 
        STATE_READY     = 0,
53
 
        STATE_CMD_HANDLE,
54
 
        STATE_DMA_READING,
55
 
        STATE_DMA_WRITING,
56
 
        STATE_DMA_DONE,
57
 
        STATE_PIO_READING,
58
 
        STATE_PIO_WRITING,
59
 
};
60
 
 
61
 
struct pxa3xx_nand_flash {
62
 
        uint32_t page_per_block;/* Pages per block (PG_PER_BLK) */
63
 
        uint32_t page_size;     /* Page size in bytes (PAGE_SZ) */
64
 
        uint32_t flash_width;   /* Width of Flash memory (DWIDTH_M) */
65
 
        size_t   read_id_bytes;
66
 
        uint32_t num_devs;
67
 
};
68
 
 
69
 
struct pxa3xx_nand_info {
70
 
        struct nand_chip        nand_chip;
71
 
 
72
 
        struct platform_device   *pdev;
73
 
        struct pxa3xx_nand_flash flash_info;
74
 
 
75
 
        struct clk              *clk;
76
 
        void __iomem            *mmio_base;
77
 
        unsigned int            mmio_phys_base;
78
 
 
79
 
        unsigned int            buf_start;
80
 
        unsigned int            buf_count;
81
 
 
82
 
        unsigned char           *data_buff;
83
 
        dma_addr_t              data_buff_phys;
84
 
        size_t                  data_buff_size;
85
 
 
86
 
        /* saved column/page_addr during CMD_SEQIN */
87
 
        int                     seqin_column;
88
 
        int                     seqin_page_addr;
89
 
 
90
 
        /* relate to the command */
91
 
        unsigned int            state;
92
 
 
93
 
        int                     use_ecc;        /* use HW ECC ? */
94
 
        int                     use_dma;        /* use DMA ? */
95
 
        int                     use_bch;        /* use BCH if use_ecc == 1 */
96
 
 
97
 
        size_t                  data_size;      /* data size in FIFO */
98
 
        size_t                  read_size;
99
 
        int                     retcode;
100
 
        struct completion       cmd_complete;
101
 
 
102
 
        int                     chained_cmd;
103
 
        uint32_t                column;
104
 
        uint32_t                page_addr;
105
 
        MV_NFC_CMD_TYPE         cmd;
106
 
        MV_NFC_CTRL             nfcCtrl;
107
 
 
108
 
        /* RW buffer chunks config */
109
 
        MV_U32                  sgBuffAddr[MV_NFC_RW_MAX_BUFF_NUM];
110
 
        MV_U32                  sgBuffSize[MV_NFC_RW_MAX_BUFF_NUM];
111
 
        MV_U32                  sgNumBuffs;
112
 
 
113
 
        /* suspend / resume data */
114
 
        MV_U32                  nfcUnitData[128];
115
 
        MV_U32                  nfcDataLen;
116
 
        MV_U32                  pdmaUnitData[128];
117
 
        MV_U32                  pdmaDataLen;
118
 
 
119
 
 
120
 
};
121
 
 
122
 
static int use_dma = 0;
123
 
module_param(use_dma, bool, 0444);
124
 
MODULE_PARM_DESC(use_dma, "enable DMA for data transfering to/from NAND HW");
125
 
static int use_ecc = 0;
126
 
module_param(use_ecc, bool, 0444);
127
 
MODULE_PARM_DESC(use_ecc, "enable ECC calculation/checking for data transfering to/from NAND HW");
128
 
static int use_bch = 0;
129
 
module_param(use_bch, bool, 0444);
130
 
MODULE_PARM_DESC(use_bch, "enable 16bit BCH ECC calculation if ECC operations are enabled");
131
 
 
132
 
static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
133
 
                        int column, int page_addr)
134
 
{
135
 
        MV_U32 size;
136
 
 
137
 
        if (mvNfcFlashPageSizeGet(&info->nfcCtrl, &size, &info->data_size) 
138
 
            != MV_OK)
139
 
                return -EINVAL;
140
 
 
141
 
        return 0;
142
 
}
143
 
 
144
 
static int handle_data_pio(struct pxa3xx_nand_info *info)
145
 
{
146
 
        int ret, timeout = CHIP_DELAY_TIMEOUT;
147
 
        NFC_DPRINT((KERN_INFO "handle_data_pio() - state = %d.\n",info->state));
148
 
        switch (info->state) {
149
 
        case STATE_PIO_WRITING:
150
 
                mvNfcReadWrite(&info->nfcCtrl, info->cmd, (MV_U32*)info->data_buff, info->data_buff_phys);
151
 
                mvNfcIntrEnable(&info->nfcCtrl,  MV_NFC_STATUS_BBD | MV_NFC_STATUS_CMDD, MV_TRUE);
152
 
 
153
 
                ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
154
 
                if (!ret) {
155
 
                        printk(KERN_ERR "program command time out\n");
156
 
                        return -1;
157
 
                }
158
 
                break;
159
 
        case STATE_PIO_READING:
160
 
                NFC_DPRINT((KERN_INFO "handle_data_pio() - data_size = %d.\n",info->data_size));
161
 
                mvNfcReadWrite(&info->nfcCtrl, info->cmd, (MV_U32*)info->data_buff, info->data_buff_phys);
162
 
                break;
163
 
        default:
164
 
                printk(KERN_ERR "%s: invalid state %d\n", __func__,
165
 
                                info->state);
166
 
                return -EINVAL;
167
 
        }
168
 
 
169
 
        info->state = STATE_READY;
170
 
        return 0;
171
 
}
172
 
 
173
 
static void pxa3xx_nand_data_dma_irq(int irq, void *data)
174
 
{
175
 
        struct pxa3xx_nand_info *info = data;
176
 
        uint32_t dcsr, intr;
177
 
        int channel = info->nfcCtrl.dataChanHndl.chanNumber;
178
 
 
179
 
        intr = MV_REG_READ(PDMA_INTR_CAUSE_REG);
180
 
        dcsr = MV_REG_READ(PDMA_CTRL_STATUS_REG(channel));
181
 
        MV_REG_WRITE(PDMA_CTRL_STATUS_REG(channel), dcsr);
182
 
 
183
 
        NFC_DPRINT((KERN_INFO "pxa3xx_nand_data_dma_irq(0x%x, 0x%x) - 1.\n", dcsr, intr));
184
 
 
185
 
        if(info->chained_cmd) {
186
 
                if (dcsr & DCSR_BUSERRINTR) {
187
 
                        info->retcode = ERR_DMABUSERR;
188
 
                        complete(&info->cmd_complete);
189
 
                }
190
 
                if ((info->state == STATE_DMA_READING) && (dcsr & DCSR_ENDINTR)) {
191
 
                        info->state = STATE_READY;
192
 
                        complete(&info->cmd_complete);
193
 
                }
194
 
                return;
195
 
        }
196
 
 
197
 
        if (dcsr & DCSR_BUSERRINTR) {
198
 
                info->retcode = ERR_DMABUSERR;
199
 
                complete(&info->cmd_complete);
200
 
        }
201
 
 
202
 
        if (info->state == STATE_DMA_WRITING) {
203
 
                info->state = STATE_DMA_DONE;
204
 
                mvNfcIntrEnable(&info->nfcCtrl,  MV_NFC_STATUS_BBD | MV_NFC_STATUS_RDY , MV_TRUE);
205
 
        } else {
206
 
                info->state = STATE_READY;
207
 
                complete(&info->cmd_complete);
208
 
        }
209
 
 
210
 
        return;
211
 
}
212
 
 
213
 
static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
214
 
{
215
 
        struct pxa3xx_nand_info *info = devid;
216
 
        unsigned int status;
217
 
 
218
 
        status = MV_REG_READ(NFC_STATUS_REG);
219
 
 
220
 
        NFC_DPRINT((KERN_INFO "pxa3xx_nand_irq(0x%x) - 1.\n", status));
221
 
 
222
 
        if(!info->chained_cmd) {
223
 
                if (status & (NFC_SR_RDDREQ_MASK | NFC_SR_UNCERR_MASK)) {
224
 
                        if (status & NFC_SR_UNCERR_MASK)
225
 
                                info->retcode = ERR_DBERR;
226
 
                        mvNfcIntrEnable(&info->nfcCtrl, NFC_SR_RDDREQ_MASK | NFC_SR_UNCERR_MASK, MV_FALSE);
227
 
                        if (info->use_dma) {
228
 
                                info->state = STATE_DMA_READING;
229
 
                                mvNfcReadWrite(&info->nfcCtrl, info->cmd, (MV_U32*)info->data_buff, info->data_buff_phys);
230
 
                        } else {
231
 
                                info->state = STATE_PIO_READING;
232
 
                                complete(&info->cmd_complete);
233
 
                        }
234
 
                } else if (status & NFC_SR_WRDREQ_MASK) {
235
 
                        mvNfcIntrEnable(&info->nfcCtrl, NFC_SR_WRDREQ_MASK, MV_FALSE);
236
 
                        if (info->use_dma) {
237
 
                                info->state = STATE_DMA_WRITING;
238
 
                                NFC_DPRINT((KERN_INFO "Calling mvNfcReadWrite().\n"));
239
 
                                if (mvNfcReadWrite(&info->nfcCtrl, info->cmd,
240
 
                                                   (MV_U32 *)info->data_buff,
241
 
                                                   info->data_buff_phys) 
242
 
                                    != MV_OK)
243
 
                                        printk(KERN_ERR "mvNfcReadWrite() failed.\n");
244
 
                        } else {
245
 
                                info->state = STATE_PIO_WRITING;
246
 
                                complete(&info->cmd_complete);
247
 
                        }
248
 
                } else if (status & (NFC_SR_BBD_MASK | MV_NFC_CS0_CMD_DONE_INT |
249
 
                                     NFC_SR_RDY0_MASK | MV_NFC_CS1_CMD_DONE_INT |
250
 
                                     NFC_SR_RDY1_MASK)) {
251
 
                        if (status & NFC_SR_BBD_MASK)
252
 
                                info->retcode = ERR_BBERR;
253
 
                        mvNfcIntrEnable(&info->nfcCtrl,  MV_NFC_STATUS_BBD |
254
 
                                        MV_NFC_STATUS_CMDD | MV_NFC_STATUS_RDY,
255
 
                                        MV_FALSE);
256
 
                        info->state = STATE_READY;
257
 
                        complete(&info->cmd_complete);
258
 
                }
259
 
        } else if (status & (NFC_SR_BBD_MASK | NFC_SR_RDY0_MASK |
260
 
                                NFC_SR_RDY1_MASK | NFC_SR_UNCERR_MASK)) {
261
 
                if (status & (NFC_SR_BBD_MASK | NFC_SR_UNCERR_MASK))
262
 
                        info->retcode = ERR_DBERR;
263
 
                mvNfcIntrEnable(&info->nfcCtrl, MV_NFC_STATUS_BBD |
264
 
                                MV_NFC_STATUS_RDY | MV_NFC_STATUS_CMDD,
265
 
                                MV_FALSE);
266
 
                if ((info->state != STATE_DMA_READING) ||
267
 
                    (info->retcode == ERR_DBERR)) {
268
 
                        info->state = STATE_READY;
269
 
                        complete(&info->cmd_complete);
270
 
                }
271
 
        }
272
 
        MV_REG_WRITE(NFC_STATUS_REG, status);
273
 
        return IRQ_HANDLED;
274
 
}
275
 
 
276
 
static void pxa3xx_nand_set_rw_chunks(struct pxa3xx_nand_info *info)
277
 
{
278
 
        uint32_t idx, i;
279
 
        uint32_t spare_size, single_trans;
280
 
        uint32_t oob_size;
281
 
 
282
 
        if ((info->nfcCtrl.ifMode != MV_NFC_IF_2X8) &&
283
 
            (info->flash_info.page_size <= 2048)) {
284
 
                /* Non-Ganged mode */
285
 
                info->sgNumBuffs = 1;
286
 
                return;
287
 
        }
288
 
 
289
 
        /*
290
 
        ** Ganged mode,
291
 
        ** need to split the MTD read / write buffer into several buffers
292
 
        ** according to what the HW expects.
293
 
        ** e.g. MTD sees
294
 
        ** ---------------------------
295
 
        ** | Data (4K) | Spare | ECC |
296
 
        ** ---------------------------
297
 
        ** While HW see
298
 
        ** -----------------------------------------------------
299
 
        ** | Data (2K) | Spare | ECC | Data (2K) | Spare | ECC |
300
 
        ** -----------------------------------------------------
301
 
        **
302
 
        ** In BCH mode, we read only the spare area.
303
 
        */
304
 
        if (info->flash_info.page_size == 1024) {       /* 2 x 512 */
305
 
                spare_size = 16;
306
 
                single_trans = 512;
307
 
                oob_size = 32;
308
 
        } else if (info->flash_info.page_size == 4096) {/* 2 x 2048 */
309
 
                spare_size = 32;
310
 
                single_trans = 2048;
311
 
                oob_size = 64;
312
 
        } else if (info->flash_info.page_size == 8192) {/* 2 x 4096 */
313
 
                spare_size = 32;
314
 
                single_trans = 2048;
315
 
                oob_size = 64;
316
 
        } else
317
 
                return;
318
 
 
319
 
        idx = 0;
320
 
        for (i = 0; i < (info->flash_info.page_size / single_trans); i++) {
321
 
                info->sgBuffAddr[2 * i] = info->data_buff_phys +
322
 
                        (single_trans * i);
323
 
                info->sgBuffSize[2 * i] = single_trans;
324
 
                info->sgBuffAddr[2 * i + 1] = info->data_buff_phys +
325
 
                        info->flash_info.page_size + (oob_size * i);
326
 
                info->sgBuffSize[2 * i + 1] = spare_size;
327
 
                idx += 2;
328
 
        }
329
 
        info->sgNumBuffs = idx;
330
 
 
331
 
        return;
332
 
}
333
 
 
334
 
static int pxa3xx_nand_do_cmd_multiple(struct pxa3xx_nand_info *info, uint32_t event)
335
 
{
336
 
        uint32_t ndcr;
337
 
        int ret, timeout = CHIP_DELAY_TIMEOUT;
338
 
        MV_STATUS status;
339
 
        MV_U32  numCmds = 1;
340
 
        MV_U32  i, singleBuffSize;
341
 
        MV_NFC_MULTI_CMD descInfo[6], *currDesc;
342
 
 
343
 
        /* Clear all status bits. */
344
 
        MV_REG_WRITE(NFC_STATUS_REG, NFC_SR_MASK);
345
 
 
346
 
        mvNfcIntrEnable(&info->nfcCtrl, event, MV_TRUE);
347
 
 
348
 
        NFC_DPRINT((KERN_INFO "About to issue multi command %d (cs %d) - 0x%x.\n",
349
 
                                info->cmd,info->nfcCtrl.currCs, MV_REG_READ(NFC_CONTROL_REG)));
350
 
        if(info->cmd == MV_NFC_CMD_READ_MONOLITHIC)
351
 
                info->state = STATE_DMA_READING;
352
 
        else
353
 
                info->state = STATE_CMD_HANDLE;
354
 
        info->chained_cmd = 1;
355
 
 
356
 
        currDesc = descInfo;
357
 
        if(info->cmd == MV_NFC_CMD_READ_MONOLITHIC) {
358
 
                mvNfcTransferDataLength(&info->nfcCtrl, info->cmd, &singleBuffSize);
359
 
                numCmds = info->data_size / singleBuffSize;
360
 
 
361
 
                currDesc->cmd = MV_NFC_CMD_READ_MONOLITHIC;
362
 
                currDesc->pageAddr = info->page_addr;
363
 
                currDesc->pageCount = 1;
364
 
                currDesc->virtAddr = (MV_U32*)info->data_buff;
365
 
                currDesc->physAddr = info->data_buff_phys;
366
 
                currDesc->numSgBuffs = ((info->sgNumBuffs == 1) ? 1 : 2);
367
 
                if(currDesc->numSgBuffs > 1) {
368
 
                        memcpy(currDesc->sgBuffAddr, info->sgBuffAddr, sizeof(MV_U32) * 2);
369
 
                        memcpy(currDesc->sgBuffSize, info->sgBuffSize, sizeof(MV_U32) * 2);
370
 
                }
371
 
                currDesc++;
372
 
 
373
 
                for(i = 1; i < numCmds; i++) {
374
 
                        if(i == (numCmds - 1))          /* Last desc  */
375
 
                                currDesc->cmd = MV_NFC_CMD_READ_LAST_NAKED;
376
 
                        else                            /* all other  */
377
 
                                currDesc->cmd = MV_NFC_CMD_READ_NAKED;
378
 
 
379
 
                        currDesc->pageAddr = info->page_addr;
380
 
                        currDesc->pageCount = 1;
381
 
                        currDesc->virtAddr = (MV_U32 *)(info->data_buff +
382
 
                                        (i * singleBuffSize));
383
 
                        currDesc->physAddr = info->data_buff_phys +
384
 
                                (i * singleBuffSize);
385
 
                        currDesc->numSgBuffs =
386
 
                                ((info->sgNumBuffs == 1) ? 1 : 2);
387
 
                        if(currDesc->numSgBuffs > 1) {
388
 
                                memcpy(currDesc->sgBuffAddr, info->sgBuffAddr +
389
 
                                                i*2, sizeof(MV_U32) * 2);
390
 
                                memcpy(currDesc->sgBuffSize, info->sgBuffSize +
391
 
                                                i*2, sizeof(MV_U32) * 2);
392
 
                        }
393
 
                        currDesc++;
394
 
                }
395
 
        } else if(info->cmd == MV_NFC_CMD_WRITE_MONOLITHIC) {
396
 
                mvNfcTransferDataLength(&info->nfcCtrl, info->cmd, &singleBuffSize);
397
 
                numCmds = info->data_size / singleBuffSize;
398
 
                /* Add 2 commands for Write dispatch start / end */
399
 
                numCmds += 2;
400
 
 
401
 
                currDesc->cmd = MV_NFC_CMD_WRITE_DISPATCH_START;
402
 
                currDesc->pageAddr = info->page_addr;
403
 
                currDesc->pageCount = 1;
404
 
                currDesc->numSgBuffs = 1;
405
 
                currDesc++;
406
 
 
407
 
                for(i = 0; i < (numCmds - 2); i++) {
408
 
                        currDesc->cmd = MV_NFC_CMD_WRITE_NAKED;
409
 
                        currDesc->pageAddr = info->page_addr;
410
 
                        currDesc->pageCount = 1;
411
 
                        currDesc->virtAddr = (MV_U32 *)(info->data_buff +
412
 
                                        (i * singleBuffSize));
413
 
                        currDesc->physAddr = info->data_buff_phys +
414
 
                                (i * singleBuffSize);
415
 
                        currDesc->numSgBuffs = ((info->sgNumBuffs == 1) ? 1 : 2);
416
 
                        if(currDesc->numSgBuffs > 1) {
417
 
                                memcpy(currDesc->sgBuffAddr,
418
 
                                                info->sgBuffAddr + (i * 2),
419
 
                                                sizeof(MV_U32) * 2);
420
 
                                memcpy(currDesc->sgBuffSize,
421
 
                                                info->sgBuffSize + (i * 2),
422
 
                                                sizeof(MV_U32) * 2);
423
 
                        }
424
 
                        currDesc++;
425
 
                }
426
 
                currDesc->cmd = MV_NFC_CMD_WRITE_DISPATCH_END;
427
 
                currDesc->pageAddr = info->page_addr;
428
 
                currDesc->pageCount = 1;
429
 
                currDesc->numSgBuffs = 1;
430
 
        } else {
431
 
                descInfo[0].cmd = info->cmd;
432
 
                descInfo[0].pageAddr = info->page_addr;
433
 
                descInfo[0].pageCount = 1;
434
 
                descInfo[0].virtAddr = (MV_U32*)info->data_buff;
435
 
                descInfo[0].physAddr = info->data_buff_phys;
436
 
                descInfo[0].numSgBuffs = 1;
437
 
        }
438
 
 
439
 
        status = mvNfcCommandMultiple(&info->nfcCtrl,descInfo, numCmds);
440
 
        if(status != MV_OK) {
441
 
                printk(KERN_ERR "mvNfcCommandMultiple() failed for command %d (%d).\n",info->cmd, status);
442
 
                goto fail;
443
 
        }
444
 
        NFC_DPRINT((KERN_INFO "After issue command %d - 0x%x.\n", info->cmd, MV_REG_READ(NFC_STATUS_REG)));
445
 
 
446
 
        ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
447
 
        if (!ret) {
448
 
                printk(KERN_ERR "command %d execution timed out (0x%x) - cs %d.\n",info->cmd, MV_REG_READ(NFC_STATUS_REG),
449
 
                                info->nfcCtrl.currCs);
450
 
                info->retcode = ERR_SENDCMD;
451
 
                goto fail_stop;
452
 
        }
453
 
 
454
 
        if (info->use_dma == 0 && info->data_size > 0)
455
 
                if (handle_data_pio(info))
456
 
                        goto fail_stop;
457
 
 
458
 
        mvNfcIntrEnable(&info->nfcCtrl, event | MV_NFC_STATUS_CMDD, MV_FALSE);
459
 
 
460
 
        while (MV_PDMA_CHANNEL_STOPPED !=
461
 
                        mvPdmaChannelStateGet(&info->nfcCtrl.dataChanHndl)) {
462
 
                if (info->retcode == ERR_NONE)
463
 
                        BUG();
464
 
 
465
 
        }
466
 
 
467
 
        return 0;
468
 
 
469
 
fail_stop:
470
 
        ndcr = MV_REG_READ(NFC_CONTROL_REG);
471
 
        MV_REG_WRITE(NFC_CONTROL_REG, ndcr & ~NFC_CTRL_ND_RUN_MASK);
472
 
        udelay(10);
473
 
fail:
474
 
        return -ETIMEDOUT;
475
 
}
476
 
 
477
 
static int pxa3xx_nand_do_cmd(struct pxa3xx_nand_info *info, uint32_t event)
478
 
{
479
 
        uint32_t ndcr;
480
 
        int ret, timeout = CHIP_DELAY_TIMEOUT;
481
 
        MV_STATUS status;
482
 
 
483
 
        /* Clear all status bits. */
484
 
        MV_REG_WRITE(NFC_STATUS_REG, NFC_SR_MASK);
485
 
        mvNfcIntrEnable(&info->nfcCtrl, NFC_SR_WRCMDREQ_MASK, MV_FALSE);
486
 
        mvNfcIntrEnable(&info->nfcCtrl, event, MV_TRUE);
487
 
 
488
 
        NFC_DPRINT((KERN_INFO "About to issue command %d (cs %d) - 0x%x.\n",
489
 
                                info->cmd,info->nfcCtrl.currCs, MV_REG_READ(NFC_CONTROL_REG)));
490
 
        info->state = STATE_CMD_HANDLE;
491
 
 
492
 
        status = mvNfcCommandIssue(&info->nfcCtrl,info->cmd,
493
 
                                   info->page_addr,info->column);
494
 
        if(status != MV_OK) {
495
 
                printk(KERN_ERR "mvNfcCommandIssue() failed for command %d (%d).\n",info->cmd, status);
496
 
                goto fail;
497
 
        }
498
 
        NFC_DPRINT((KERN_INFO "After issue command %d - 0x%x.\n", info->cmd, MV_REG_READ(NFC_STATUS_REG)));
499
 
 
500
 
        ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
501
 
        if (!ret) {
502
 
                printk(KERN_ERR "command %d execution timed out (0x%x).\n",info->cmd, MV_REG_READ(NFC_STATUS_REG));
503
 
                info->retcode = ERR_SENDCMD;
504
 
                goto fail_stop;
505
 
        }
506
 
 
507
 
        if(info->state != STATE_READY)
508
 
                printk(KERN_INFO "%s - %d - Bad state.\n", __FUNCTION__, __LINE__);
509
 
        if (info->use_dma == 0 && info->data_size > 0)
510
 
                if (handle_data_pio(info))
511
 
                        goto fail_stop;
512
 
 
513
 
        mvNfcIntrEnable(&info->nfcCtrl, event | MV_NFC_STATUS_CMDD, MV_FALSE);
514
 
 
515
 
        if(MV_PDMA_CHANNEL_STOPPED != mvPdmaChannelStateGet(&info->nfcCtrl.dataChanHndl))
516
 
                BUG();
517
 
 
518
 
        return 0;
519
 
 
520
 
fail_stop:
521
 
        ndcr = MV_REG_READ(NFC_CONTROL_REG);
522
 
        MV_REG_WRITE(NFC_CONTROL_REG, ndcr & ~NFC_CTRL_ND_RUN_MASK);
523
 
        udelay(10);
524
 
fail:
525
 
        return -ETIMEDOUT;
526
 
}
527
 
 
528
 
static int pxa3xx_nand_dev_ready(struct mtd_info *mtd)
529
 
{
530
 
        return (MV_REG_READ(NFC_STATUS_REG) & (NFC_SR_RDY0_MASK | NFC_SR_RDY1_MASK)) ? 1 : 0;
531
 
}
532
 
 
533
 
static inline int is_buf_blank(uint8_t *buf, size_t len)
534
 
{
535
 
        for (; len > 0; len--)
536
 
                if (*buf++ != 0xff)
537
 
                        return 0;
538
 
        return 1;
539
 
}
540
 
 
541
 
static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
542
 
                                int column, int page_addr)
543
 
{
544
 
        struct pxa3xx_nand_info *info = mtd->priv;
545
 
        struct pxa3xx_nand_flash *flash_info = &info->flash_info;
546
 
        int ret;
547
 
 
548
 
        info->use_dma = (use_dma) ? 1 : 0;
549
 
        info->use_bch = (use_bch) ? 1 : 0;
550
 
        info->use_ecc = 0;
551
 
        info->data_size = 0;
552
 
        info->state = STATE_READY;
553
 
        info->chained_cmd = 0;
554
 
        info->retcode = ERR_NONE;
555
 
        init_completion(&info->cmd_complete);
556
 
 
557
 
        switch (command) {
558
 
        case NAND_CMD_READOOB:
559
 
                info->buf_count = mtd->writesize + mtd->oobsize;
560
 
                info->buf_start = mtd->writesize + column;
561
 
                info->cmd = MV_NFC_CMD_READ_MONOLITHIC;
562
 
                info->column = column;
563
 
                info->page_addr = page_addr;
564
 
                if (prepare_read_prog_cmd(info, column, page_addr))
565
 
                        break;
566
 
                pxa3xx_nand_do_cmd_multiple(info,
567
 
                                MV_NFC_STATUS_RDY | NFC_SR_UNCERR_MASK);
568
 
                /*pxa3xx_nand_do_cmd(info,
569
 
                                NFC_SR_RDDREQ_MASK | NFC_SR_UNCERR_MASK);*/
570
 
                /* We only are OOB, so if the data has error, does not matter */
571
 
                if (info->retcode == ERR_DBERR)
572
 
                        info->retcode = ERR_NONE;
573
 
                break;
574
 
 
575
 
        case NAND_CMD_READ0:
576
 
                info->use_ecc = 1;
577
 
                info->buf_start = column;
578
 
                info->buf_count = mtd->writesize + mtd->oobsize;
579
 
                memset(info->data_buff, 0xff, info->buf_count);
580
 
                info->cmd = MV_NFC_CMD_READ_MONOLITHIC;
581
 
                info->column = column;
582
 
                info->page_addr = page_addr;
583
 
                if (prepare_read_prog_cmd(info, column, page_addr))
584
 
                        break;
585
 
                pxa3xx_nand_do_cmd_multiple(info,
586
 
                                MV_NFC_STATUS_RDY | NFC_SR_UNCERR_MASK);
587
 
                /*pxa3xx_nand_do_cmd(info,
588
 
                                NFC_SR_RDDREQ_MASK | NFC_SR_UNCERR_MASK);*/
589
 
                if (info->retcode == ERR_DBERR) {
590
 
                        /* for blank page (all 0xff), HW will calculate its ECC as
591
 
                         * 0, which is different from the ECC information within
592
 
                         * OOB, ignore such double bit errors
593
 
                         */
594
 
                        if (is_buf_blank(info->data_buff, mtd->writesize))
595
 
                                info->retcode = ERR_NONE;
596
 
                        else
597
 
                                printk(KERN_INFO "%s: retCode == ERR_DBERR\n", __FUNCTION__);
598
 
                }
599
 
                break;
600
 
        case NAND_CMD_SEQIN:
601
 
                info->buf_start = column;
602
 
                info->buf_count = mtd->writesize + mtd->oobsize;
603
 
                memset(info->data_buff + mtd->writesize, 0xff, mtd->oobsize);
604
 
 
605
 
                /* save column/page_addr for next CMD_PAGEPROG */
606
 
                info->seqin_column = column;
607
 
                info->seqin_page_addr = page_addr;
608
 
                break;
609
 
        case NAND_CMD_PAGEPROG:
610
 
                info->use_ecc = (info->seqin_column >= mtd->writesize) ? 0 : 1;
611
 
                info->column = info->seqin_column;
612
 
                info->page_addr = info->seqin_page_addr;
613
 
                info->cmd = MV_NFC_CMD_WRITE_MONOLITHIC;
614
 
                if (prepare_read_prog_cmd(info,
615
 
                                info->seqin_column, info->seqin_page_addr)) {
616
 
                        printk(KERN_ERR "prepare_read_prog_cmd() failed.\n");
617
 
                        break;
618
 
                }
619
 
                pxa3xx_nand_do_cmd_multiple(info, MV_NFC_STATUS_RDY);
620
 
                /*pxa3xx_nand_do_cmd(info, NFC_SR_WRDREQ_MASK);*/
621
 
                break;
622
 
        case NAND_CMD_ERASE1:
623
 
                info->column = 0;
624
 
                info->page_addr = page_addr;
625
 
                info->cmd = MV_NFC_CMD_ERASE;
626
 
 
627
 
                pxa3xx_nand_do_cmd_multiple(info, MV_NFC_STATUS_BBD | MV_NFC_STATUS_RDY);
628
 
                /*pxa3xx_nand_do_cmd(info, MV_NFC_STATUS_BBD | MV_NFC_STATUS_RDY);*/
629
 
                break;
630
 
        case NAND_CMD_ERASE2:
631
 
                break;
632
 
        case NAND_CMD_READID:
633
 
        case NAND_CMD_STATUS:
634
 
                info->buf_start = 0;
635
 
                info->buf_count = (command == NAND_CMD_READID) ?
636
 
                                flash_info->read_id_bytes : 1;
637
 
                info->data_size = 8;
638
 
                info->column = 0;
639
 
                info->page_addr = 0;
640
 
                info->cmd = (command == NAND_CMD_READID) ?
641
 
                        MV_NFC_CMD_READ_ID : MV_NFC_CMD_READ_STATUS;
642
 
                pxa3xx_nand_do_cmd(info,NFC_SR_RDDREQ_MASK);
643
 
                break;
644
 
        case NAND_CMD_RESET:
645
 
                info->column = 0;
646
 
                info->page_addr = 0;
647
 
                info->cmd = MV_NFC_CMD_RESET;
648
 
                ret = pxa3xx_nand_do_cmd_multiple(info, MV_NFC_STATUS_CMDD);
649
 
                /*ret = pxa3xx_nand_do_cmd(info, MV_NFC_STATUS_CMDD);*/
650
 
                if (ret == 0) {
651
 
                        int timeout = 2;
652
 
                        uint32_t ndcr;
653
 
 
654
 
                        while (timeout--) {
655
 
                                if (MV_REG_READ(NFC_STATUS_REG) & (NFC_SR_RDY0_MASK | NFC_SR_RDY1_MASK))
656
 
                                        break;
657
 
                                msleep(10);
658
 
                        }
659
 
 
660
 
                        ndcr = MV_REG_READ(NFC_CONTROL_REG);
661
 
                        MV_REG_WRITE(NFC_CONTROL_REG, ndcr & ~NFC_CTRL_ND_RUN_MASK);
662
 
                }
663
 
                break;
664
 
        default:
665
 
                printk(KERN_ERR "non-supported command.\n");
666
 
                break;
667
 
        }
668
 
 
669
 
        if (info->retcode == ERR_DBERR) {
670
 
                printk(KERN_ERR "double bit error @ page %08x\n", page_addr);
671
 
                info->retcode = ERR_NONE;
672
 
        }
673
 
}
674
 
 
675
 
static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
676
 
{
677
 
        struct pxa3xx_nand_info *info = mtd->priv;
678
 
        char retval = 0xFF;
679
 
 
680
 
        if (info->buf_start < info->buf_count)
681
 
                /* Has just send a new command? */
682
 
                retval = info->data_buff[info->buf_start++];
683
 
        return retval;
684
 
}
685
 
 
686
 
static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
687
 
{
688
 
        struct pxa3xx_nand_info *info = mtd->priv;
689
 
        u16 retval = 0xFFFF;
690
 
 
691
 
        if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
692
 
                retval = *((u16 *)(info->data_buff+info->buf_start));
693
 
                info->buf_start += 2;
694
 
        }
695
 
        else
696
 
                printk(KERN_ERR "\n%s: returning 0xFFFF (%d, %d).\n",__FUNCTION__, info->buf_start,info->buf_count);
697
 
 
698
 
        return retval;
699
 
}
700
 
 
701
 
static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
702
 
{
703
 
        struct pxa3xx_nand_info *info = mtd->priv;
704
 
        int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
705
 
 
706
 
        memcpy(buf, info->data_buff + info->buf_start, real_len);
707
 
        info->buf_start += real_len;
708
 
}
709
 
 
710
 
static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
711
 
                const uint8_t *buf, int len)
712
 
{
713
 
        struct pxa3xx_nand_info *info = mtd->priv;
714
 
        int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
715
 
 
716
 
        memcpy(info->data_buff + info->buf_start, buf, real_len);
717
 
        info->buf_start += real_len;
718
 
}
719
 
 
720
 
static int pxa3xx_nand_verify_buf(struct mtd_info *mtd,
721
 
                const uint8_t *buf, int len)
722
 
{
723
 
        return 0;
724
 
}
725
 
 
726
 
static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
727
 
{
728
 
        struct pxa3xx_nand_info *info = mtd->priv;
729
 
        mvNfcSelectChip(&info->nfcCtrl, MV_NFC_CS_0 + chip);
730
 
        return;
731
 
}
732
 
 
733
 
static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
734
 
{
735
 
        struct pxa3xx_nand_info *info = mtd->priv;
736
 
 
737
 
        /* pxa3xx_nand_send_command has waited for command complete */
738
 
        if (this->state == FL_WRITING || this->state == FL_ERASING) {
739
 
                if (info->retcode == ERR_NONE)
740
 
                        return 0;
741
 
                else {
742
 
                        /*
743
 
                         * any error make it return 0x01 which will tell
744
 
                         * the caller the erase and write fail
745
 
                         */
746
 
                        return 0x01;
747
 
                }
748
 
        }
749
 
 
750
 
        return 0;
751
 
}
752
 
 
753
 
static void pxa3xx_nand_ecc_hwctl(struct mtd_info *mtd, int mode)
754
 
{
755
 
        return;
756
 
}
757
 
 
758
 
static int pxa3xx_nand_ecc_calculate(struct mtd_info *mtd,
759
 
                const uint8_t *dat, uint8_t *ecc_code)
760
 
{
761
 
        return 0;
762
 
}
763
 
 
764
 
static int pxa3xx_nand_ecc_correct(struct mtd_info *mtd,
765
 
                uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc)
766
 
{
767
 
        struct pxa3xx_nand_info *info = mtd->priv;
768
 
        /*
769
 
         * Any error include ERR_SEND_CMD, ERR_DBERR, ERR_BUSERR, we
770
 
         * consider it as a ecc error which will tell the caller the
771
 
         * read fail We have distinguish all the errors, but the
772
 
         * nand_read_ecc only check this function return value
773
 
         */
774
 
        if (info->retcode != ERR_NONE)
775
 
                return -1;
776
 
 
777
 
        return 0;
778
 
}
779
 
 
780
 
static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info)
781
 
{
782
 
        struct platform_device *pdev = info->pdev;
783
 
        struct dove_nand_platform_data *pdata = pdev->dev.platform_data;
784
 
        struct pxa3xx_nand_flash *f = &info->flash_info;
785
 
 
786
 
        mvNfcFlashPageSizeGet(&info->nfcCtrl, &f->page_size, NULL);
787
 
        if (f->page_size != 8192 && f->page_size != 4096 &&
788
 
            f->page_size != 2048 && f->page_size != 512)
789
 
                return -EINVAL;
790
 
 
791
 
        f->flash_width = pdata->nfc_width;
792
 
        if (f->flash_width != 16 && f->flash_width != 8)
793
 
                return -EINVAL;
794
 
 
795
 
        /* calculate flash information */
796
 
        f->read_id_bytes = (f->page_size >= 2048) ? 4 : 2;
797
 
        f->num_devs = pdata->num_devs;
798
 
 
799
 
        return 0;
800
 
}
801
 
 
802
 
/* the maximum possible buffer size for large page with OOB data
803
 
 * is: 4096 + 128 = 4224 bytes, allocate a page here for both the
804
 
 * data buffer and the DMA descriptor
805
 
 * Multiply by 2 for Ganged mode.
806
 
 */
807
 
#define MAX_BUFF_SIZE   (PAGE_SIZE << 2)
808
 
 
809
 
static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
810
 
{
811
 
        struct platform_device *pdev = info->pdev;
812
 
        int ret;
813
 
 
814
 
        if (use_dma == 0) {
815
 
                info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
816
 
                if (info->data_buff == NULL)
817
 
                        return -ENOMEM;
818
 
                return 0;
819
 
        }
820
 
 
821
 
        info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
822
 
                                &info->data_buff_phys, GFP_KERNEL);
823
 
        if (info->data_buff == NULL) {
824
 
                dev_err(&pdev->dev, "failed to allocate dma buffer\n");
825
 
                return -ENOMEM;
826
 
        }
827
 
        memset(info->data_buff, 0xff, MAX_BUFF_SIZE);
828
 
 
829
 
        ret = pxa_request_dma_intr ("nand-data", info->nfcCtrl.dataChanHndl.chanNumber,
830
 
                        pxa3xx_nand_data_dma_irq, info);
831
 
        if (ret < 0) {
832
 
                dev_err(&pdev->dev, "failed to request PDMA IRQ\n");
833
 
                return -ENOMEM;
834
 
        }
835
 
        return 0;
836
 
}
837
 
 
838
 
static struct nand_ecclayout hw_smallpage_ecclayout = {
839
 
        .eccbytes = 6,
840
 
        .eccpos = {8, 9, 10, 11, 12, 13 },
841
 
        .oobfree = { {2, 6} }
842
 
};
843
 
 
844
 
static struct nand_ecclayout hw_largepage_ecclayout = {
845
 
        .eccbytes = 24,
846
 
        .eccpos = {
847
 
                40, 41, 42, 43, 44, 45, 46, 47,
848
 
                48, 49, 50, 51, 52, 53, 54, 55,
849
 
                56, 57, 58, 59, 60, 61, 62, 63},
850
 
        .oobfree = { {2, 38} }
851
 
};
852
 
 
853
 
static struct nand_ecclayout hw_largepage_bch_ecclayout = {
854
 
        .eccbytes = 32,
855
 
        .eccpos = {
856
 
                32, 33, 34, 35, 36, 37, 38, 39,
857
 
                40, 41, 42, 43, 44, 45, 46, 47,
858
 
                48, 49, 50, 51, 52, 53, 54, 55,
859
 
                56, 57, 58, 59, 60, 61, 62, 63},
860
 
        .oobfree = { {2, 30} }
861
 
};
862
 
 
863
 
static struct nand_ecclayout hw_ganged_largepage_bch_ecclayout = {
864
 
        .eccbytes = 64,
865
 
        .eccpos = {
866
 
                32,  33,  34,  35,  36,  37,  38,  39,
867
 
                40,  41,  42,  43,  44,  45,  46,  47,
868
 
                48,  49,  50,  51,  52,  53,  54,  55,
869
 
                56,  57,  58,  59,  60,  61,  62,  63,
870
 
                96,  97,  98,  99,  100, 101, 102, 103,
871
 
                104, 105, 106, 107, 108, 109, 110, 111,
872
 
                112, 113, 114, 115, 116, 117, 118, 119,
873
 
                120, 121, 122, 123, 124, 125, 126, 127},
874
 
        /* Bootrom looks in bytes 0 & 5 for bad blocks */
875
 
        .oobfree = { {1, 4}, {6, 26}, { 64, 32} }
876
 
};
877
 
 
878
 
static struct nand_ecclayout hw_ganged_largepage_8k_bch_ecclayout = {
879
 
        .eccbytes = 128,
880
 
        .eccpos = {
881
 
                32,  33,  34,  35,  36,  37,  38,  39,
882
 
                40,  41,  42,  43,  44,  45,  46,  47,
883
 
                48,  49,  50,  51,  52,  53,  54,  55,
884
 
                56,  57,  58,  59,  60,  61,  62,  63,
885
 
 
886
 
                96,  97,  98,  99,  100, 101, 102, 103,
887
 
                104, 105, 106, 107, 108, 109, 110, 111,
888
 
                112, 113, 114, 115, 116, 117, 118, 119,
889
 
                120, 121, 122, 123, 124, 125, 126, 127,
890
 
 
891
 
                160, 161, 162, 163, 164, 165, 166, 167,
892
 
                168, 169, 170, 171, 172, 173, 174, 175,
893
 
                176, 177, 178, 179, 180, 181, 182, 183,
894
 
                184, 185, 186, 187, 188, 189, 190, 191,
895
 
 
896
 
                224, 225, 226, 227, 228, 229, 230, 231,
897
 
                232, 233, 234, 235, 236, 237, 238, 239,
898
 
                240, 241, 242, 243, 244, 245, 246, 247,
899
 
                248, 249, 250, 251, 252, 253, 254, 255},
900
 
 
901
 
        /* Bootrom looks in bytes 0 & 5 for bad blocks */
902
 
        .oobfree = { {1, 4}, {6, 26}, { 64, 32}, {128, 32}, {192, 32} }
903
 
};
904
 
 
905
 
static uint8_t mv_bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };
906
 
static uint8_t mv_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' };
907
 
 
908
 
static struct nand_bbt_descr mvbbt_main_descr = {
909
 
        .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
910
 
                | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
911
 
        .offs = 8,
912
 
        .len = 6,
913
 
        .veroffs = 14,
914
 
        .maxblocks = 8,         /* Last 8 blocks in each chip */
915
 
        .pattern = mv_bbt_pattern
916
 
};
917
 
 
918
 
static struct nand_bbt_descr mvbbt_mirror_descr = {
919
 
        .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
920
 
                | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
921
 
        .offs = 8,
922
 
        .len = 6,
923
 
        .veroffs = 14,
924
 
        .maxblocks = 8,         /* Last 8 blocks in each chip */
925
 
        .pattern = mv_mirror_pattern
926
 
};
927
 
 
928
 
static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
929
 
                                 struct pxa3xx_nand_info *info)
930
 
{
931
 
        struct pxa3xx_nand_flash *f = &info->flash_info;
932
 
        struct nand_chip *this = &info->nand_chip;
933
 
        struct dove_nand_platform_data *pdata = info->pdev->dev.platform_data;
934
 
 
935
 
        this->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16: 0;
936
 
 
937
 
        this->num_devs = pdata->num_devs;
938
 
        this->options |= NAND_USE_FLASH_BBT;
939
 
 
940
 
        this->waitfunc          = pxa3xx_nand_waitfunc;
941
 
        this->select_chip       = pxa3xx_nand_select_chip;
942
 
        this->dev_ready         = pxa3xx_nand_dev_ready;
943
 
        this->cmdfunc           = pxa3xx_nand_cmdfunc;
944
 
        this->read_word         = pxa3xx_nand_read_word;
945
 
        this->read_byte         = pxa3xx_nand_read_byte;
946
 
        this->read_buf          = pxa3xx_nand_read_buf;
947
 
        this->write_buf         = pxa3xx_nand_write_buf;
948
 
        this->verify_buf        = pxa3xx_nand_verify_buf;
949
 
 
950
 
        this->ecc.mode          = NAND_ECC_HW;
951
 
        this->ecc.hwctl         = pxa3xx_nand_ecc_hwctl;
952
 
        this->ecc.calculate     = pxa3xx_nand_ecc_calculate;
953
 
        this->ecc.correct       = pxa3xx_nand_ecc_correct;
954
 
        this->ecc.size          = f->page_size;
955
 
 
956
 
        if (f->page_size >= 2048) {
957
 
                if (info->nfcCtrl.ifMode != MV_NFC_IF_2X8) {
958
 
                        if (f->page_size < 4096) {
959
 
                                if (info->use_bch)
960
 
                                        this->ecc.layout =
961
 
                                                &hw_largepage_bch_ecclayout;
962
 
                                else
963
 
                                        this->ecc.layout =
964
 
                                                &hw_largepage_ecclayout;
965
 
                        } else
966
 
                                this->ecc.layout =
967
 
                                        &hw_ganged_largepage_bch_ecclayout;
968
 
                } else {
969
 
                        if (f->page_size <= 4096)
970
 
                                this->ecc.layout =
971
 
                                        &hw_ganged_largepage_bch_ecclayout;
972
 
                        else
973
 
                                this->ecc.layout =
974
 
                                        &hw_ganged_largepage_8k_bch_ecclayout;
975
 
                }
976
 
        } else
977
 
                this->ecc.layout = &hw_smallpage_ecclayout;
978
 
 
979
 
        this->bbt_td = &mvbbt_main_descr;
980
 
        this->bbt_md = &mvbbt_mirror_descr;
981
 
 
982
 
        this->chip_delay = 25;
983
 
}
984
 
 
985
 
static int pxa3xx_nand_probe(struct platform_device *pdev)
986
 
{
987
 
        struct dove_nand_platform_data *pdata;
988
 
        struct pxa3xx_nand_info *info;
989
 
        struct nand_chip *this;
990
 
        struct mtd_info *mtd;
991
 
        struct resource *r;
992
 
        int ret = 0, irq;
993
 
        char * stat[2] = {"Disabled", "Enabled"};
994
 
        MV_NFC_INFO nfcInfo;
995
 
 
996
 
        pdata = pdev->dev.platform_data;
997
 
 
998
 
        if (!pdata) {
999
 
                dev_err(&pdev->dev, "no platform data defined\n");
1000
 
                return -ENODEV;
1001
 
        }
1002
 
 
1003
 
        /* Set global parameters based on platform data */
1004
 
        if (pdata->use_dma) use_dma = 1;
1005
 
        if (pdata->use_ecc) use_ecc = 1;
1006
 
        if (pdata->use_bch) use_bch = 1;
1007
 
 
1008
 
        dev_info(&pdev->dev, "Initialize HAL based NFC in %dbit mode with "
1009
 
                        "DMA %s, ECC %s, BCH %s\n",
1010
 
                        pdata->nfc_width, stat[use_dma], stat[use_ecc],
1011
 
                        stat[use_bch]);
1012
 
 
1013
 
        mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct pxa3xx_nand_info),
1014
 
                        GFP_KERNEL);
1015
 
        if (!mtd) {
1016
 
                dev_err(&pdev->dev, "failed to allocate memory\n");
1017
 
                return -ENOMEM;
1018
 
        }
1019
 
 
1020
 
        info = (struct pxa3xx_nand_info *)(&mtd[1]);
1021
 
        info->pdev = pdev;
1022
 
 
1023
 
        this = &info->nand_chip;
1024
 
        mtd->priv = info;
1025
 
        mtd->owner = THIS_MODULE;
1026
 
 
1027
 
        info->clk = clk_get_sys("dove-nand", NULL);
1028
 
        if (IS_ERR(info->clk)) {
1029
 
                dev_err(&pdev->dev, "failed to get nand clock\n");
1030
 
                ret = PTR_ERR(info->clk);
1031
 
                goto fail_free_mtd;
1032
 
        }
1033
 
        clk_enable(info->clk);
1034
 
 
1035
 
        irq = platform_get_irq(pdev, 0);
1036
 
        if (irq < 0) {
1037
 
                dev_err(&pdev->dev, "no IRQ resource defined\n");
1038
 
                ret = -ENXIO;
1039
 
                goto fail_put_clk;
1040
 
        }
1041
 
 
1042
 
        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1043
 
        if (r == NULL) {
1044
 
                dev_err(&pdev->dev, "no IO memory resource defined\n");
1045
 
                ret = -ENODEV;
1046
 
                goto fail_put_clk;
1047
 
        }
1048
 
 
1049
 
        r = devm_request_mem_region(&pdev->dev, r->start, r->end - r->start + 1,
1050
 
                                    pdev->name);
1051
 
        if (r == NULL) {
1052
 
                dev_err(&pdev->dev, "failed to request memory resource\n");
1053
 
                ret = -EBUSY;
1054
 
                goto fail_put_clk;
1055
 
        }
1056
 
 
1057
 
        info->mmio_base = devm_ioremap(&pdev->dev, r->start,
1058
 
                                       r->end - r->start + 1);
1059
 
        if (info->mmio_base == NULL) {
1060
 
                dev_err(&pdev->dev, "ioremap() failed\n");
1061
 
                ret = -ENODEV;
1062
 
                goto fail_put_clk;
1063
 
        }
1064
 
 
1065
 
        info->mmio_phys_base = r->start;
1066
 
 
1067
 
#if 0
1068
 
        if (mvPdmaHalInit(MV_PDMA_MAX_CHANNELS_NUM) != MV_OK) {
1069
 
                dev_err(&pdev->dev, "mvPdmaHalInit() failed.\n");
1070
 
                goto fail_put_clk;
1071
 
        }
1072
 
#endif
1073
 
        /* Initialize NFC HAL */
1074
 
        nfcInfo.ioMode = (use_dma ? MV_NFC_PDMA_ACCESS : MV_NFC_PIO_ACCESS);
1075
 
        if(use_ecc) {
1076
 
                if(use_bch)
1077
 
                        nfcInfo.eccMode = MV_NFC_ECC_BCH;
1078
 
                else
1079
 
                        nfcInfo.eccMode = MV_NFC_ECC_HAMMING;
1080
 
        } else
1081
 
                nfcInfo.eccMode = MV_NFC_ECC_DISABLE;
1082
 
 
1083
 
        if(pdata->num_devs == 1)
1084
 
                nfcInfo.ifMode = ((pdata->nfc_width == 8) ? MV_NFC_IF_1X8 : MV_NFC_IF_1X16);
1085
 
        else
1086
 
                nfcInfo.ifMode = MV_NFC_IF_2X8;
1087
 
        nfcInfo.autoStatusRead = MV_FALSE;
1088
 
        nfcInfo.tclk = pdata->tclk;
1089
 
        nfcInfo.readyBypass = MV_FALSE;
1090
 
        nfcInfo.osHandle = NULL;
1091
 
        nfcInfo.regsPhysAddr = DOVE_SB_REGS_PHYS_BASE;
1092
 
        nfcInfo.dataPdmaIntMask = MV_PDMA_END_OF_RX_INTR_EN | MV_PDMA_END_INTR_EN;
1093
 
        nfcInfo.cmdPdmaIntMask = 0x0;
1094
 
        if (mvNfcInit(&nfcInfo, &info->nfcCtrl) != MV_OK) {
1095
 
                dev_err(&pdev->dev, "mvNfcInit() failed.\n");
1096
 
                goto fail_put_clk;
1097
 
        }
1098
 
 
1099
 
        mvNfcSelectChip(&info->nfcCtrl, MV_NFC_CS_0);
1100
 
        mvNfcIntrEnable(&info->nfcCtrl,  0xFFF, MV_FALSE);
1101
 
        mvNfcSelectChip(&info->nfcCtrl, MV_NFC_CS_1);
1102
 
        mvNfcIntrEnable(&info->nfcCtrl,  0xFFF, MV_FALSE);
1103
 
        mvNfcSelectChip(&info->nfcCtrl, MV_NFC_CS_NONE);
1104
 
 
1105
 
        ret = pxa3xx_nand_init_buff(info);
1106
 
        if (ret)
1107
 
                goto fail_put_clk;
1108
 
 
1109
 
        /* Clear all old events on the status register */
1110
 
        MV_REG_WRITE(NFC_STATUS_REG, MV_REG_READ(NFC_STATUS_REG));
1111
 
        ret = request_irq(IRQ_NAND, pxa3xx_nand_irq, IRQF_DISABLED,
1112
 
                                pdev->name, info);
1113
 
        if (ret < 0) {
1114
 
                dev_err(&pdev->dev, "failed to request IRQ\n");
1115
 
                goto fail_free_buf;
1116
 
        }
1117
 
 
1118
 
        ret = pxa3xx_nand_detect_flash(info);
1119
 
        if (ret) {
1120
 
                dev_err(&pdev->dev, "failed to detect flash\n");
1121
 
                ret = -ENODEV;
1122
 
                goto fail_free_irq;
1123
 
        }
1124
 
 
1125
 
        pxa3xx_nand_set_rw_chunks(info);
1126
 
 
1127
 
        pxa3xx_nand_init_mtd(mtd, info);
1128
 
 
1129
 
        platform_set_drvdata(pdev, mtd);
1130
 
 
1131
 
        if (nand_scan(mtd, pdata->num_cs)) {
1132
 
                dev_err(&pdev->dev, "failed to scan nand\n");
1133
 
                ret = -ENXIO;
1134
 
                goto fail_free_irq;
1135
 
        }
1136
 
 
1137
 
        return add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts);
1138
 
 
1139
 
fail_free_irq:
1140
 
        free_irq(IRQ_NAND, info);
1141
 
fail_free_buf:
1142
 
        if (use_dma) {
1143
 
                dma_free_coherent(&pdev->dev, info->data_buff_size,
1144
 
                        info->data_buff, info->data_buff_phys);
1145
 
        } else
1146
 
                kfree(info->data_buff);
1147
 
fail_put_clk:
1148
 
        clk_disable(info->clk);
1149
 
        clk_put(info->clk);
1150
 
fail_free_mtd:
1151
 
        kfree(mtd);
1152
 
        return ret;
1153
 
}
1154
 
 
1155
 
static int pxa3xx_nand_remove(struct platform_device *pdev)
1156
 
{
1157
 
        struct mtd_info *mtd = platform_get_drvdata(pdev);
1158
 
        struct pxa3xx_nand_info *info = mtd->priv;
1159
 
 
1160
 
        platform_set_drvdata(pdev, NULL);
1161
 
 
1162
 
        del_mtd_device(mtd);
1163
 
        del_mtd_partitions(mtd);
1164
 
        free_irq(IRQ_NAND, info);
1165
 
        if (use_dma) {
1166
 
                dma_free_writecombine(&pdev->dev, info->data_buff_size,
1167
 
                                info->data_buff, info->data_buff_phys);
1168
 
        } else
1169
 
                kfree(info->data_buff);
1170
 
 
1171
 
        clk_disable(info->clk);
1172
 
        clk_put(info->clk);
1173
 
        kfree(mtd);
1174
 
        return 0;
1175
 
}
1176
 
 
1177
 
#ifdef CONFIG_PM
1178
 
static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1179
 
{
1180
 
        struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
1181
 
        struct pxa3xx_nand_info *info = mtd->priv;
1182
 
 
1183
 
        if (info->state != STATE_READY) {
1184
 
                dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1185
 
                return -EAGAIN;
1186
 
        }
1187
 
 
1188
 
        /* Store PDMA registers.        */
1189
 
        info->pdmaDataLen = 128;
1190
 
        mvPdmaUnitStateStore(info->pdmaUnitData, &info->pdmaDataLen);
1191
 
 
1192
 
        /* Store NFC registers. */
1193
 
        info->nfcDataLen = 128;
1194
 
        mvNfcUnitStateStore(info->nfcUnitData, &info->nfcDataLen);
1195
 
 
1196
 
        clk_disable(info->clk);
1197
 
        return 0;
1198
 
}
1199
 
 
1200
 
static int pxa3xx_nand_resume(struct platform_device *pdev)
1201
 
{
1202
 
        struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
1203
 
        struct pxa3xx_nand_info *info = mtd->priv;
1204
 
        MV_U32  i;
1205
 
 
1206
 
        clk_enable(info->clk);
1207
 
 
1208
 
        /* restore PDMA registers */
1209
 
        for(i = 0; i < info->pdmaDataLen; i+=2)
1210
 
                MV_REG_WRITE(info->pdmaUnitData[i], info->pdmaUnitData[i+1]);
1211
 
 
1212
 
        /* Clear all NAND interrupts */
1213
 
        MV_REG_WRITE(NFC_STATUS_REG, MV_REG_READ(NFC_STATUS_REG));
1214
 
 
1215
 
        /* restore NAND registers */
1216
 
        for(i = 0; i < info->nfcDataLen; i+=2)
1217
 
                MV_REG_WRITE(info->nfcUnitData[i], info->nfcUnitData[i+1]);
1218
 
 
1219
 
        return 0;
1220
 
}
1221
 
#else
1222
 
#define pxa3xx_nand_suspend     NULL
1223
 
#define pxa3xx_nand_resume      NULL
1224
 
#endif
1225
 
 
1226
 
static struct platform_driver pxa3xx_nand_driver = {
1227
 
        .driver = {
1228
 
                .name   = "dove-nand-hal",
1229
 
                .owner  = THIS_MODULE,
1230
 
        },
1231
 
        .probe          = pxa3xx_nand_probe,
1232
 
        .remove         = pxa3xx_nand_remove,
1233
 
        .suspend        = pxa3xx_nand_suspend,
1234
 
        .resume         = pxa3xx_nand_resume,
1235
 
};
1236
 
 
1237
 
static int __init pxa3xx_nand_init(void)
1238
 
{
1239
 
        return platform_driver_register(&pxa3xx_nand_driver);
1240
 
}
1241
 
module_init(pxa3xx_nand_init);
1242
 
 
1243
 
static void __exit pxa3xx_nand_exit(void)
1244
 
{
1245
 
        platform_driver_unregister(&pxa3xx_nand_driver);
1246
 
}
1247
 
module_exit(pxa3xx_nand_exit);
1248
 
 
1249
 
MODULE_LICENSE("GPL");
1250
 
MODULE_DESCRIPTION("Dove NAND controller driver");