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Copyright 1999, 2000, 2001 Free Software Foundation, Inc.
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This file is part of the GNU MP Library.
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The GNU MP Library is free software; you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as published by
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the Free Software Foundation; either version 2.1 of the License, or (at your
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option) any later version.
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The GNU MP Library is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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License for more details.
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You should have received a copy of the GNU Lesser General Public License
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along with the GNU MP Library; see the file COPYING.LIB. If not, write to
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the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
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PPC630 (aka Power3) pipeline information:
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Decoding is 4-way and issue is 8-way with some out-of-order capability.
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Branches are handled separately, and are not part of the 4-way issue limit.
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FXU1 - integer unit 1, handles any simple integer instruction
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FXU2 - integer unit 2, handles any simple integer instruction
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FXU3 - integer unit 3, handles integer multiply and divide
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FPU1 - floating-point unit 1
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FPU2 - floating-point unit 2
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Memory: Any two memory operations can issue, but memory subsystem
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can sustain just one store per cycle. No need for data
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prefetch; the hardware has very sophisticated prefetch logic.
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Simple integer: 2 operations (such as add, rl*)
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Integer multiply: 1 operation every 9th cycle worst case; exact timing depends
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on 2nd operand most significant bit position (10 bits per
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cycle). Multiply unit is not pipelined, only one multiply
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operation in progress is allowed.
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Floating-point: Any plain 2 arithmetic instructions (such as fmul, fadd, fmadd)
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Floating-point divide:
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Floating-point square root:
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Best possible times for the main loops:
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shift: 1.5 cycles limited by integer unit contention.
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With 63 special loops, one for each shift count, we could
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reduce the needed integer instructions to 2, which would
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reduce the best possible time to 1 cycle.
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add/sub: 1.5 cycles, limited by ld/st unit contention.
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mul: 18 cycles (average) unless floating-point operations are used,
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but that would only help for multiplies of perhaps 10 and more
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addmul/submul:Same situation as for mul.
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*mul_1: Handling one limb using mulld/mulhdu and two limbs using
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floating-point operations should give a performance of about 20 cycles
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for 3 limbs, or 7 cycles/limb.
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We should probably split the single-limb operand in 32-bit chunks, and
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the multi-limb operand in 16-bit chunks, allowing us to accumulate
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fctidz,stfd,ld,fctidz,stfd,ld
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fctidz,stfd,ld,fctidz,stfd,ld
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srd,sld,add,adde,add,adde