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//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This file contains the declaration of the MachineInstr class, which is the
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// basic representation for all target dependent machine instructions used by
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEINSTR_H
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#define LLVM_CODEGEN_MACHINEINSTR_H
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Target/TargetOpcodes.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/ilist.h"
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#include "llvm/ADT/ilist_node.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/DenseMapInfo.h"
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#include "llvm/Support/DebugLoc.h"
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template <typename T> class SmallVectorImpl;
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class TargetInstrInfo;
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class TargetRegisterClass;
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class TargetRegisterInfo;
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class MachineFunction;
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class MachineMemOperand;
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//===----------------------------------------------------------------------===//
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/// MachineInstr - Representation of each machine instruction.
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class MachineInstr : public ilist_node<MachineInstr> {
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typedef MachineMemOperand **mmo_iterator;
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/// Flags to specify different kinds of comments to output in
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/// assembly code. These flags carry semantic information not
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/// otherwise easily derivable from the IR text.
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FrameSetup = 1 << 0, // Instruction is used as a part of
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// function frame setup code.
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InsideBundle = 1 << 1 // Instruction is inside a bundle (not
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// the first MI in a bundle)
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const MCInstrDesc *MCID; // Instruction descriptor.
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uint8_t Flags; // Various bits of additional
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// information about machine
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uint8_t AsmPrinterFlags; // Various bits of information used by
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// the AsmPrinter to emit helpful
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// comments. This is *not* semantic
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// information. Do not use this for
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// anything other than to convey comment
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// information to AsmPrinter.
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uint16_t NumMemRefs; // information on memory references
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std::vector<MachineOperand> Operands; // the operands
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MachineBasicBlock *Parent; // Pointer to the owning basic block.
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DebugLoc debugLoc; // Source line information.
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MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
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void operator=(const MachineInstr&); // DO NOT IMPLEMENT
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// Intrusive list support
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friend struct ilist_traits<MachineInstr>;
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friend struct ilist_traits<MachineBasicBlock>;
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void setParent(MachineBasicBlock *P) { Parent = P; }
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/// MachineInstr ctor - This constructor creates a copy of the given
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/// MachineInstr in the given MachineFunction.
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MachineInstr(MachineFunction &, const MachineInstr &);
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/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
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/// MCID NULL and no operands.
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// The next two constructors have DebugLoc and non-DebugLoc versions;
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// over time, the non-DebugLoc versions should be phased out and eventually
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/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
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/// implicit operands. It reserves space for the number of operands specified
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/// by the MCInstrDesc. The version with a DebugLoc should be preferred.
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explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false);
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/// MachineInstr ctor - Work exactly the same as the ctor above, except that
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/// the MachineInstr is created and added to the end of the specified basic
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/// block. The version with a DebugLoc should be preferred.
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MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID);
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/// MachineInstr ctor - This constructor create a MachineInstr and add the
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/// implicit operands. It reserves space for number of operands specified by
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/// MCInstrDesc. An explicit DebugLoc is supplied.
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explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl,
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/// MachineInstr ctor - Work exactly the same as the ctor above, except that
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/// the MachineInstr is created and added to the end of the specified basic
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MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
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const MCInstrDesc &MCID);
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// MachineInstrs are pool-allocated and owned by MachineFunction.
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friend class MachineFunction;
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const MachineBasicBlock* getParent() const { return Parent; }
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MachineBasicBlock* getParent() { return Parent; }
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/// getAsmPrinterFlags - Return the asm printer flags bitvector.
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uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
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/// clearAsmPrinterFlags - clear the AsmPrinter bitvector
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void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
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/// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
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bool getAsmPrinterFlag(CommentFlag Flag) const {
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return AsmPrinterFlags & Flag;
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/// setAsmPrinterFlag - Set a flag for the AsmPrinter.
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void setAsmPrinterFlag(CommentFlag Flag) {
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AsmPrinterFlags |= (uint8_t)Flag;
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/// clearAsmPrinterFlag - clear specific AsmPrinter flags
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void clearAsmPrinterFlag(CommentFlag Flag) {
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AsmPrinterFlags &= ~Flag;
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/// getFlags - Return the MI flags bitvector.
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uint8_t getFlags() const {
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/// getFlag - Return whether an MI flag is set.
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bool getFlag(MIFlag Flag) const {
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/// setFlag - Set a MI flag.
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void setFlag(MIFlag Flag) {
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Flags |= (uint8_t)Flag;
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void setFlags(unsigned flags) {
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/// clearFlag - Clear a MI flag.
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void clearFlag(MIFlag Flag) {
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Flags &= ~((uint8_t)Flag);
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/// isInsideBundle - Return true if MI is in a bundle (but not the first MI
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/// A bundle looks like this before it's finalized:
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/// In this case, the first MI starts a bundle but is not inside a bundle, the
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/// next 2 MIs are considered "inside" the bundle.
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/// After a bundle is finalized, it looks like this:
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/// The first instruction has the special opcode "BUNDLE". It's not "inside"
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/// a bundle, but the next three MIs are.
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bool isInsideBundle() const {
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return getFlag(InsideBundle);
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/// setIsInsideBundle - Set InsideBundle bit.
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void setIsInsideBundle(bool Val = true) {
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setFlag(InsideBundle);
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clearFlag(InsideBundle);
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/// isBundled - Return true if this instruction part of a bundle. This is true
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/// if either itself or its following instruction is marked "InsideBundle".
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bool isBundled() const;
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/// getDebugLoc - Returns the debug location id of this MachineInstr.
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DebugLoc getDebugLoc() const { return debugLoc; }
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/// emitError - Emit an error referring to the source location of this
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/// instruction. This should only be used for inline assembly that is somehow
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/// impossible to compile. Other errors should have been handled much
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/// If this method returns, the caller should try to recover from the error.
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void emitError(StringRef Msg) const;
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/// getDesc - Returns the target instruction descriptor of this
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const MCInstrDesc &getDesc() const { return *MCID; }
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/// getOpcode - Returns the opcode of this MachineInstr.
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int getOpcode() const { return MCID->Opcode; }
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/// Access to explicit operands of the instruction.
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unsigned getNumOperands() const { return (unsigned)Operands.size(); }
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const MachineOperand& getOperand(unsigned i) const {
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assert(i < getNumOperands() && "getOperand() out of range!");
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MachineOperand& getOperand(unsigned i) {
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assert(i < getNumOperands() && "getOperand() out of range!");
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/// getNumExplicitOperands - Returns the number of non-implicit operands.
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unsigned getNumExplicitOperands() const;
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/// iterator/begin/end - Iterate over all operands of a machine instruction.
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typedef std::vector<MachineOperand>::iterator mop_iterator;
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typedef std::vector<MachineOperand>::const_iterator const_mop_iterator;
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mop_iterator operands_begin() { return Operands.begin(); }
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mop_iterator operands_end() { return Operands.end(); }
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const_mop_iterator operands_begin() const { return Operands.begin(); }
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const_mop_iterator operands_end() const { return Operands.end(); }
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/// Access to memory operands of the instruction
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mmo_iterator memoperands_begin() const { return MemRefs; }
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mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
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bool memoperands_empty() const { return NumMemRefs == 0; }
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/// hasOneMemOperand - Return true if this instruction has exactly one
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/// MachineMemOperand.
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bool hasOneMemOperand() const {
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return NumMemRefs == 1;
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/// API for querying MachineInstr properties. They are the same as MCInstrDesc
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/// queries but they are bundle aware.
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IgnoreBundle, // Ignore bundles
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AnyInBundle, // Return true if any instruction in bundle has property
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AllInBundle // Return true if all instructions in bundle have property
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/// hasProperty - Return true if the instruction (or in the case of a bundle,
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/// the instructions inside the bundle) has the specified property.
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/// The first argument is the property being queried.
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/// The second argument indicates whether the query should look inside
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/// instruction bundles.
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bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
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// Inline the fast path.
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if (Type == IgnoreBundle || !isBundle())
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return getDesc().getFlags() & (1 << MCFlag);
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// If we have a bundle, take the slow path.
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return hasPropertyInBundle(1 << MCFlag, Type);
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/// isVariadic - Return true if this instruction can have a variable number of
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/// operands. In this case, the variable operands will be after the normal
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/// operands but before the implicit definitions and uses (if any are
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bool isVariadic(QueryType Type = IgnoreBundle) const {
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return hasProperty(MCID::Variadic, Type);
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/// hasOptionalDef - Set if this instruction has an optional definition, e.g.
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/// ARM instructions which can set condition code if 's' bit is set.
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bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
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return hasProperty(MCID::HasOptionalDef, Type);
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/// isPseudo - Return true if this is a pseudo instruction that doesn't
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/// correspond to a real machine instruction.
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bool isPseudo(QueryType Type = IgnoreBundle) const {
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return hasProperty(MCID::Pseudo, Type);
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bool isReturn(QueryType Type = AnyInBundle) const {
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return hasProperty(MCID::Return, Type);
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bool isCall(QueryType Type = AnyInBundle) const {
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return hasProperty(MCID::Call, Type);
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/// isBarrier - Returns true if the specified instruction stops control flow
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/// from executing the instruction immediately following it. Examples include
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/// unconditional branches and return instructions.
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bool isBarrier(QueryType Type = AnyInBundle) const {
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return hasProperty(MCID::Barrier, Type);
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/// isTerminator - Returns true if this instruction part of the terminator for
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/// a basic block. Typically this is things like return and branch
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/// Various passes use this to insert code into the bottom of a basic block,
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/// but before control flow occurs.
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bool isTerminator(QueryType Type = AnyInBundle) const {
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return hasProperty(MCID::Terminator, Type);
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/// isBranch - Returns true if this is a conditional, unconditional, or
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/// indirect branch. Predicates below can be used to discriminate between
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/// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
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/// get more information.
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bool isBranch(QueryType Type = AnyInBundle) const {
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return hasProperty(MCID::Branch, Type);
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/// isIndirectBranch - Return true if this is an indirect branch, such as a
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/// branch through a register.
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bool isIndirectBranch(QueryType Type = AnyInBundle) const {
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return hasProperty(MCID::IndirectBranch, Type);
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/// isConditionalBranch - Return true if this is a branch which may fall
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/// through to the next instruction or may transfer control flow to some other
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/// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
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/// information about this branch.
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bool isConditionalBranch(QueryType Type = AnyInBundle) const {
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return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
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/// isUnconditionalBranch - Return true if this is a branch which always
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/// transfers control flow to some other block. The
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/// TargetInstrInfo::AnalyzeBranch method can be used to get more information
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/// about this branch.
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bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
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return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
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// isPredicable - Return true if this instruction has a predicate operand that
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// controls execution. It may be set to 'always', or may be set to other
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/// values. There are various methods in TargetInstrInfo that can be used to
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/// control and modify the predicate in this instruction.
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bool isPredicable(QueryType Type = AllInBundle) const {
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// If it's a bundle than all bundled instructions must be predicable for this
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return hasProperty(MCID::Predicable, Type);
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/// isCompare - Return true if this instruction is a comparison.
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bool isCompare(QueryType Type = IgnoreBundle) const {
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return hasProperty(MCID::Compare, Type);
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/// isMoveImmediate - Return true if this instruction is a move immediate
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/// (including conditional moves) instruction.
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bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
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return hasProperty(MCID::MoveImm, Type);
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/// isBitcast - Return true if this instruction is a bitcast instruction.
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bool isBitcast(QueryType Type = IgnoreBundle) const {
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return hasProperty(MCID::Bitcast, Type);
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/// isNotDuplicable - Return true if this instruction cannot be safely
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/// duplicated. For example, if the instruction has a unique labels attached
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/// to it, duplicating it would cause multiple definition errors.
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bool isNotDuplicable(QueryType Type = AnyInBundle) const {
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return hasProperty(MCID::NotDuplicable, Type);
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/// hasDelaySlot - Returns true if the specified instruction has a delay slot
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/// which must be filled by the code generator.
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bool hasDelaySlot(QueryType Type = AnyInBundle) const {
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return hasProperty(MCID::DelaySlot, Type);
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/// canFoldAsLoad - Return true for instructions that can be folded as
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/// memory operands in other instructions. The most common use for this
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/// is instructions that are simple loads from memory that don't modify
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/// the loaded value in any way, but it can also be used for instructions
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/// that can be expressed as constant-pool loads, such as V_SETALLONES
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/// on x86, to allow them to be folded when it is beneficial.
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/// This should only be set on instructions that return a value in their
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/// only virtual register definition.
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bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
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return hasProperty(MCID::FoldableAsLoad, Type);
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//===--------------------------------------------------------------------===//
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// Side Effect Analysis
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//===--------------------------------------------------------------------===//
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/// mayLoad - Return true if this instruction could possibly read memory.
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/// Instructions with this flag set are not necessarily simple load
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/// instructions, they may load a value and modify it, for example.
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bool mayLoad(QueryType Type = AnyInBundle) const {
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return hasProperty(MCID::MayLoad, Type);
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/// mayStore - Return true if this instruction could possibly modify memory.
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/// Instructions with this flag set are not necessarily simple store
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/// instructions, they may store a modified value based on their operands, or
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/// may not actually modify anything, for example.
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bool mayStore(QueryType Type = AnyInBundle) const {
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return hasProperty(MCID::MayStore, Type);
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//===--------------------------------------------------------------------===//
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// Flags that indicate whether an instruction can be modified by a method.
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//===--------------------------------------------------------------------===//
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/// isCommutable - Return true if this may be a 2- or 3-address
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/// instruction (of the form "X = op Y, Z, ..."), which produces the same
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/// result if Y and Z are exchanged. If this flag is set, then the
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/// TargetInstrInfo::commuteInstruction method may be used to hack on the
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/// Note that this flag may be set on instructions that are only commutable
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/// sometimes. In these cases, the call to commuteInstruction will fail.
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/// Also note that some instructions require non-trivial modification to
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bool isCommutable(QueryType Type = IgnoreBundle) const {
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return hasProperty(MCID::Commutable, Type);
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/// isConvertibleTo3Addr - Return true if this is a 2-address instruction
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/// which can be changed into a 3-address instruction if needed. Doing this
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/// transformation can be profitable in the register allocator, because it
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/// means that the instruction can use a 2-address form if possible, but
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/// degrade into a less efficient form if the source and dest register cannot
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/// be assigned to the same register. For example, this allows the x86
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/// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
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/// is the same speed as the shift but has bigger code size.
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/// If this returns true, then the target must implement the
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/// TargetInstrInfo::convertToThreeAddress method for this instruction, which
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/// is allowed to fail if the transformation isn't valid for this specific
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/// instruction (e.g. shl reg, 4 on x86).
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bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
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return hasProperty(MCID::ConvertibleTo3Addr, Type);
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/// usesCustomInsertionHook - Return true if this instruction requires
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/// custom insertion support when the DAG scheduler is inserting it into a
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/// machine basic block. If this is true for the instruction, it basically
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/// means that it is a pseudo instruction used at SelectionDAG time that is
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/// expanded out into magic code by the target when MachineInstrs are formed.
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/// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
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/// is used to insert this into the MachineBasicBlock.
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bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
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return hasProperty(MCID::UsesCustomInserter, Type);
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/// hasPostISelHook - Return true if this instruction requires *adjustment*
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/// after instruction selection by calling a target hook. For example, this
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/// can be used to fill in ARM 's' optional operand depending on whether
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/// the conditional flag register is used.
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bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
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return hasProperty(MCID::HasPostISelHook, Type);
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/// isRematerializable - Returns true if this instruction is a candidate for
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/// remat. This flag is deprecated, please don't use it anymore. If this
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/// flag is set, the isReallyTriviallyReMaterializable() method is called to
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/// verify the instruction is really rematable.
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bool isRematerializable(QueryType Type = AllInBundle) const {
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// It's only possible to re-mat a bundle if all bundled instructions are
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// re-materializable.
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return hasProperty(MCID::Rematerializable, Type);
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/// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
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/// less) than a move instruction. This is useful during certain types of
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/// optimizations (e.g., remat during two-address conversion or machine licm)
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/// where we would like to remat or hoist the instruction, but not if it costs
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/// more than moving the instruction into the appropriate register. Note, we
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/// are not marking copies from and to the same register class with this flag.
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bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
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// Only returns true for a bundle if all bundled instructions are cheap.
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// FIXME: This probably requires a target hook.
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return hasProperty(MCID::CheapAsAMove, Type);
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/// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
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/// have special register allocation requirements that are not captured by the
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/// operand register classes. e.g. ARM::STRD's two source registers must be an
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/// even / odd pair, ARM::STM registers have to be in ascending order.
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/// Post-register allocation passes should not attempt to change allocations
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/// for sources of instructions with this flag.
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bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
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return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
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/// hasExtraDefRegAllocReq - Returns true if this instruction def operands
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/// have special register allocation requirements that are not captured by the
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/// operand register classes. e.g. ARM::LDRD's two def registers must be an
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/// even / odd pair, ARM::LDM registers have to be in ascending order.
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/// Post-register allocation passes should not attempt to change allocations
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/// for definitions of instructions with this flag.
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bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
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return hasProperty(MCID::ExtraDefRegAllocReq, Type);
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CheckDefs, // Check all operands for equality
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CheckKillDead, // Check all operands including kill / dead markers
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IgnoreDefs, // Ignore all definitions
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IgnoreVRegDefs // Ignore virtual register definitions
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/// isIdenticalTo - Return true if this instruction is identical to (same
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/// opcode and same operands as) the specified instruction.
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bool isIdenticalTo(const MachineInstr *Other,
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MICheckType Check = CheckDefs) const;
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/// removeFromParent - This method unlinks 'this' from the containing basic
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/// block, and returns it, but does not delete it.
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MachineInstr *removeFromParent();
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/// eraseFromParent - This method unlinks 'this' from the containing basic
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/// block and deletes it.
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void eraseFromParent();
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/// isLabel - Returns true if the MachineInstr represents a label.
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bool isLabel() const {
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return getOpcode() == TargetOpcode::PROLOG_LABEL ||
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getOpcode() == TargetOpcode::EH_LABEL ||
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getOpcode() == TargetOpcode::GC_LABEL;
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bool isPrologLabel() const {
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return getOpcode() == TargetOpcode::PROLOG_LABEL;
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bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
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bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
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bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
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bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
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bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
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bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
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bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
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bool isStackAligningInlineAsm() const;
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bool isInsertSubreg() const {
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return getOpcode() == TargetOpcode::INSERT_SUBREG;
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bool isSubregToReg() const {
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return getOpcode() == TargetOpcode::SUBREG_TO_REG;
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bool isRegSequence() const {
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return getOpcode() == TargetOpcode::REG_SEQUENCE;
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bool isBundle() const {
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return getOpcode() == TargetOpcode::BUNDLE;
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bool isCopy() const {
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return getOpcode() == TargetOpcode::COPY;
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bool isFullCopy() const {
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return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
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/// isCopyLike - Return true if the instruction behaves like a copy.
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/// This does not include native copy instructions.
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bool isCopyLike() const {
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return isCopy() || isSubregToReg();
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/// isIdentityCopy - Return true is the instruction is an identity copy.
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bool isIdentityCopy() const {
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return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
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getOperand(0).getSubReg() == getOperand(1).getSubReg();
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/// getBundleSize - Return the number of instructions inside the MI bundle.
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unsigned getBundleSize() const;
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/// readsRegister - Return true if the MachineInstr reads the specified
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/// register. If TargetRegisterInfo is passed, then it also checks if there
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/// is a read of a super-register.
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/// This does not count partial redefines of virtual registers as reads:
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bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
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return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
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/// readsVirtualRegister - Return true if the MachineInstr reads the specified
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/// virtual register. Take into account that a partial define is a
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/// read-modify-write operation.
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bool readsVirtualRegister(unsigned Reg) const {
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return readsWritesVirtualRegister(Reg).first;
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/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
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/// indicating if this instruction reads or writes Reg. This also considers
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/// If Ops is not null, all operand indices for Reg are added.
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std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
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SmallVectorImpl<unsigned> *Ops = 0) const;
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/// killsRegister - Return true if the MachineInstr kills the specified
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/// register. If TargetRegisterInfo is passed, then it also checks if there is
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/// a kill of a super-register.
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bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
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return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
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/// definesRegister - Return true if the MachineInstr fully defines the
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/// specified register. If TargetRegisterInfo is passed, then it also checks
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/// if there is a def of a super-register.
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/// NOTE: It's ignoring subreg indices on virtual registers.
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bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
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return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
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/// modifiesRegister - Return true if the MachineInstr modifies (fully define
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/// or partially define) the specified register.
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/// NOTE: It's ignoring subreg indices on virtual registers.
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bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
683
return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
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/// registerDefIsDead - Returns true if the register is dead in this machine
687
/// instruction. If TargetRegisterInfo is passed, then it also checks
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/// if there is a dead def of a super-register.
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bool registerDefIsDead(unsigned Reg,
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const TargetRegisterInfo *TRI = NULL) const {
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return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
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/// findRegisterUseOperandIdx() - Returns the operand index that is a use of
695
/// the specific register or -1 if it is not found. It further tightens
696
/// the search criteria to a use that kills the register if isKill is true.
697
int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
698
const TargetRegisterInfo *TRI = NULL) const;
700
/// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
701
/// a pointer to the MachineOperand rather than an index.
702
MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
703
const TargetRegisterInfo *TRI = NULL) {
704
int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
705
return (Idx == -1) ? NULL : &getOperand(Idx);
708
/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
709
/// the specified register or -1 if it is not found. If isDead is true, defs
710
/// that are not dead are skipped. If Overlap is true, then it also looks for
711
/// defs that merely overlap the specified register. If TargetRegisterInfo is
712
/// non-null, then it also checks if there is a def of a super-register.
713
/// This may also return a register mask operand when Overlap is true.
714
int findRegisterDefOperandIdx(unsigned Reg,
715
bool isDead = false, bool Overlap = false,
716
const TargetRegisterInfo *TRI = NULL) const;
718
/// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
719
/// a pointer to the MachineOperand rather than an index.
720
MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
721
const TargetRegisterInfo *TRI = NULL) {
722
int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
723
return (Idx == -1) ? NULL : &getOperand(Idx);
726
/// findFirstPredOperandIdx() - Find the index of the first operand in the
727
/// operand list that is used to represent the predicate. It returns -1 if
729
int findFirstPredOperandIdx() const;
731
/// findInlineAsmFlagIdx() - Find the index of the flag word operand that
732
/// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
733
/// getOperand(OpIdx) does not belong to an inline asm operand group.
735
/// If GroupNo is not NULL, it will receive the number of the operand group
736
/// containing OpIdx.
738
/// The flag operand is an immediate that can be decoded with methods like
739
/// InlineAsm::hasRegClassConstraint().
741
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = 0) const;
743
/// getRegClassConstraint - Compute the static register class constraint for
744
/// operand OpIdx. For normal instructions, this is derived from the
745
/// MCInstrDesc. For inline assembly it is derived from the flag words.
747
/// Returns NULL if the static register classs constraint cannot be
750
const TargetRegisterClass*
751
getRegClassConstraint(unsigned OpIdx,
752
const TargetInstrInfo *TII,
753
const TargetRegisterInfo *TRI) const;
755
/// isRegTiedToUseOperand - Given the index of a register def operand,
756
/// check if the register def is tied to a source operand, due to either
757
/// two-address elimination or inline assembly constraints. Returns the
758
/// first tied use operand index by reference if UseOpIdx is not null.
759
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;
761
/// isRegTiedToDefOperand - Return true if the use operand of the specified
762
/// index is tied to an def operand. It also returns the def operand index by
763
/// reference if DefOpIdx is not null.
764
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;
766
/// clearKillInfo - Clears kill flags on all operands.
768
void clearKillInfo();
770
/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
772
void copyKillDeadInfo(const MachineInstr *MI);
774
/// copyPredicates - Copies predicate operand(s) from MI.
775
void copyPredicates(const MachineInstr *MI);
777
/// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
778
/// properly composing subreg indices where necessary.
779
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
780
const TargetRegisterInfo &RegInfo);
782
/// addRegisterKilled - We have determined MI kills a register. Look for the
783
/// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
784
/// add a implicit operand if it's not found. Returns true if the operand
785
/// exists / is added.
786
bool addRegisterKilled(unsigned IncomingReg,
787
const TargetRegisterInfo *RegInfo,
788
bool AddIfNotFound = false);
790
/// clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo is
791
/// provided, this includes super-register kills.
792
void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
794
/// addRegisterDead - We have determined MI defined a register without a use.
795
/// Look for the operand that defines it and mark it as IsDead. If
796
/// AddIfNotFound is true, add a implicit operand if it's not found. Returns
797
/// true if the operand exists / is added.
798
bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
799
bool AddIfNotFound = false);
801
/// addRegisterDefined - We have determined MI defines a register. Make sure
802
/// there is an operand defining Reg.
803
void addRegisterDefined(unsigned IncomingReg,
804
const TargetRegisterInfo *RegInfo = 0);
806
/// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
807
/// dead except those in the UsedRegs list.
809
/// On instructions with register mask operands, also add implicit-def
810
/// operands for all registers in UsedRegs.
811
void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
812
const TargetRegisterInfo &TRI);
814
/// isSafeToMove - Return true if it is safe to move this instruction. If
815
/// SawStore is set to true, it means that there is a store (or call) between
816
/// the instruction's location and its intended destination.
817
bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
818
bool &SawStore) const;
820
/// isSafeToReMat - Return true if it's safe to rematerialize the specified
821
/// instruction which defined the specified register instead of copying it.
822
bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
823
unsigned DstReg) const;
825
/// hasVolatileMemoryRef - Return true if this instruction may have a
826
/// volatile memory reference, or if the information describing the
827
/// memory reference is not available. Return false if it is known to
828
/// have no volatile memory references.
829
bool hasVolatileMemoryRef() const;
831
/// isInvariantLoad - Return true if this instruction is loading from a
832
/// location whose value is invariant across the function. For example,
833
/// loading a value from the constant pool or from the argument area of
834
/// a function if it does not change. This should only return true of *all*
835
/// loads the instruction does are invariant (if it does multiple loads).
836
bool isInvariantLoad(AliasAnalysis *AA) const;
838
/// isConstantValuePHI - If the specified instruction is a PHI that always
839
/// merges together the same virtual register, return the register, otherwise
841
unsigned isConstantValuePHI() const;
843
/// hasUnmodeledSideEffects - Return true if this instruction has side
844
/// effects that are not modeled by mayLoad / mayStore, etc.
845
/// For all instructions, the property is encoded in MCInstrDesc::Flags
846
/// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
847
/// INLINEASM instruction, in which case the side effect property is encoded
848
/// in one of its operands (see InlineAsm::Extra_HasSideEffect).
850
bool hasUnmodeledSideEffects() const;
852
/// allDefsAreDead - Return true if all the defs of this instruction are dead.
854
bool allDefsAreDead() const;
856
/// copyImplicitOps - Copy implicit register operands from specified
857
/// instruction to this instruction.
858
void copyImplicitOps(const MachineInstr *MI);
863
void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
866
//===--------------------------------------------------------------------===//
867
// Accessors used to build up machine instructions.
869
/// addOperand - Add the specified operand to the instruction. If it is an
870
/// implicit operand, it is added to the end of the operand list. If it is
871
/// an explicit operand it is added at the end of the explicit operand list
872
/// (before the first implicit operand).
873
void addOperand(const MachineOperand &Op);
875
/// setDesc - Replace the instruction descriptor (thus opcode) of
876
/// the current instruction with a new one.
878
void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
880
/// setDebugLoc - Replace current source information with new such.
881
/// Avoid using this, the constructor argument is preferable.
883
void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
885
/// RemoveOperand - Erase an operand from an instruction, leaving it with one
886
/// fewer operand than it started with.
888
void RemoveOperand(unsigned i);
890
/// addMemOperand - Add a MachineMemOperand to the machine instruction.
891
/// This function should be used only occasionally. The setMemRefs function
892
/// is the primary method for setting up a MachineInstr's MemRefs list.
893
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
895
/// setMemRefs - Assign this MachineInstr's memory reference descriptor
896
/// list. This does not transfer ownership.
897
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
898
MemRefs = NewMemRefs;
899
NumMemRefs = NewMemRefsEnd - NewMemRefs;
903
/// getRegInfo - If this instruction is embedded into a MachineFunction,
904
/// return the MachineRegisterInfo object for the current function, otherwise
906
MachineRegisterInfo *getRegInfo();
908
/// addImplicitDefUseOperands - Add all implicit def and use operands to
909
/// this instruction.
910
void addImplicitDefUseOperands();
912
/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
913
/// this instruction from their respective use lists. This requires that the
914
/// operands already be on their use lists.
915
void RemoveRegOperandsFromUseLists();
917
/// AddRegOperandsToUseLists - Add all of the register operands in
918
/// this instruction from their respective use lists. This requires that the
919
/// operands not be on their use lists yet.
920
void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
922
/// hasPropertyInBundle - Slow path for hasProperty when we're dealing with a
924
bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
927
/// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
928
/// MachineInstr* by *value* of the instruction rather than by pointer value.
929
/// The hashing and equality testing functions ignore definitions so this is
930
/// useful for CSE, etc.
931
struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
932
static inline MachineInstr *getEmptyKey() {
936
static inline MachineInstr *getTombstoneKey() {
937
return reinterpret_cast<MachineInstr*>(-1);
940
static unsigned getHashValue(const MachineInstr* const &MI);
942
static bool isEqual(const MachineInstr* const &LHS,
943
const MachineInstr* const &RHS) {
944
if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
945
LHS == getEmptyKey() || LHS == getTombstoneKey())
947
return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
951
//===----------------------------------------------------------------------===//
954
inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
959
} // End llvm namespace
added
removed
include/llvm/CodeGen/MachineInstr.h
