1
//===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===//
3
// The LLVM Compiler Infrastructure
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
8
//===----------------------------------------------------------------------===//
10
// This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
11
// instructions after register allocation.
13
//===----------------------------------------------------------------------===//
15
#define DEBUG_TYPE "postrapseudos"
16
#include "llvm/CodeGen/Passes.h"
17
#include "llvm/Function.h"
18
#include "llvm/CodeGen/MachineFunctionPass.h"
19
#include "llvm/CodeGen/MachineInstr.h"
20
#include "llvm/CodeGen/MachineInstrBuilder.h"
21
#include "llvm/CodeGen/MachineRegisterInfo.h"
22
#include "llvm/Target/TargetRegisterInfo.h"
23
#include "llvm/Target/TargetInstrInfo.h"
24
#include "llvm/Target/TargetMachine.h"
25
#include "llvm/Support/Debug.h"
26
#include "llvm/Support/raw_ostream.h"
30
struct ExpandPostRA : public MachineFunctionPass {
32
const TargetRegisterInfo *TRI;
33
const TargetInstrInfo *TII;
36
static char ID; // Pass identification, replacement for typeid
37
ExpandPostRA() : MachineFunctionPass(ID) {}
39
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
41
AU.addPreservedID(MachineLoopInfoID);
42
AU.addPreservedID(MachineDominatorsID);
43
MachineFunctionPass::getAnalysisUsage(AU);
46
/// runOnMachineFunction - pass entry point
47
bool runOnMachineFunction(MachineFunction&);
50
bool LowerSubregToReg(MachineInstr *MI);
51
bool LowerCopy(MachineInstr *MI);
53
void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
54
const TargetRegisterInfo *TRI);
55
void TransferImplicitDefs(MachineInstr *MI);
57
} // end anonymous namespace
59
char ExpandPostRA::ID = 0;
60
char &llvm::ExpandPostRAPseudosID = ExpandPostRA::ID;
62
INITIALIZE_PASS(ExpandPostRA, "postrapseudos",
63
"Post-RA pseudo instruction expansion pass", false, false)
65
/// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
66
/// and the lowered replacement instructions immediately precede it.
67
/// Mark the replacement instructions with the dead flag.
69
ExpandPostRA::TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
70
const TargetRegisterInfo *TRI) {
71
for (MachineBasicBlock::iterator MII =
72
prior(MachineBasicBlock::iterator(MI)); ; --MII) {
73
if (MII->addRegisterDead(DstReg, TRI))
75
assert(MII != MI->getParent()->begin() &&
76
"copyPhysReg output doesn't reference destination register!");
80
/// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered
81
/// replacement instructions immediately precede it. Copy any implicit-def
82
/// operands from MI to the replacement instruction.
84
ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) {
85
MachineBasicBlock::iterator CopyMI = MI;
88
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
89
MachineOperand &MO = MI->getOperand(i);
90
if (!MO.isReg() || !MO.isImplicit() || MO.isUse())
92
CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true));
96
bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
97
MachineBasicBlock *MBB = MI->getParent();
98
assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
99
MI->getOperand(1).isImm() &&
100
(MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
101
MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
103
unsigned DstReg = MI->getOperand(0).getReg();
104
unsigned InsReg = MI->getOperand(2).getReg();
105
assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
106
unsigned SubIdx = MI->getOperand(3).getImm();
108
assert(SubIdx != 0 && "Invalid index for insert_subreg");
109
unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
111
assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
112
"Insert destination must be in a physical register");
113
assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
114
"Inserted value must be in a physical register");
116
DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
118
if (DstSubReg == InsReg) {
119
// No need to insert an identify copy instruction.
120
// Watch out for case like this:
121
// %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3
122
// We must leave %RAX live.
123
if (DstReg != InsReg) {
124
MI->setDesc(TII->get(TargetOpcode::KILL));
125
MI->RemoveOperand(3); // SubIdx
126
MI->RemoveOperand(1); // Imm
127
DEBUG(dbgs() << "subreg: replace by: " << *MI);
130
DEBUG(dbgs() << "subreg: eliminated!");
132
TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
133
MI->getOperand(2).isKill());
134
// Transfer the kill/dead flags, if needed.
135
if (MI->getOperand(0).isDead())
136
TransferDeadFlag(MI, DstSubReg, TRI);
138
MachineBasicBlock::iterator dMI = MI;
139
dbgs() << "subreg: " << *(--dMI);
143
DEBUG(dbgs() << '\n');
148
bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
149
MachineOperand &DstMO = MI->getOperand(0);
150
MachineOperand &SrcMO = MI->getOperand(1);
152
if (SrcMO.getReg() == DstMO.getReg()) {
153
DEBUG(dbgs() << "identity copy: " << *MI);
154
// No need to insert an identity copy instruction, but replace with a KILL
155
// if liveness is changed.
156
if (DstMO.isDead() || SrcMO.isUndef() || MI->getNumOperands() > 2) {
157
// We must make sure the super-register gets killed. Replace the
158
// instruction with KILL.
159
MI->setDesc(TII->get(TargetOpcode::KILL));
160
DEBUG(dbgs() << "replaced by: " << *MI);
163
// Vanilla identity copy.
164
MI->eraseFromParent();
168
DEBUG(dbgs() << "real copy: " << *MI);
169
TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
170
DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
173
TransferDeadFlag(MI, DstMO.getReg(), TRI);
174
if (MI->getNumOperands() > 2)
175
TransferImplicitDefs(MI);
177
MachineBasicBlock::iterator dMI = MI;
178
dbgs() << "replaced by: " << *(--dMI);
180
MI->eraseFromParent();
184
/// runOnMachineFunction - Reduce subregister inserts and extracts to register
187
bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) {
188
DEBUG(dbgs() << "Machine Function\n"
189
<< "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
190
<< "********** Function: "
191
<< MF.getFunction()->getName() << '\n');
192
TRI = MF.getTarget().getRegisterInfo();
193
TII = MF.getTarget().getInstrInfo();
195
bool MadeChange = false;
197
for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
198
mbbi != mbbe; ++mbbi) {
199
for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
201
MachineInstr *MI = mi;
202
// Advance iterator here because MI may be erased.
205
// Only expand pseudos.
209
// Give targets a chance to expand even standard pseudos.
210
if (TII->expandPostRAPseudo(MI)) {
215
// Expand standard pseudos.
216
switch (MI->getOpcode()) {
217
case TargetOpcode::SUBREG_TO_REG:
218
MadeChange |= LowerSubregToReg(MI);
220
case TargetOpcode::COPY:
221
MadeChange |= LowerCopy(MI);
223
case TargetOpcode::DBG_VALUE:
225
case TargetOpcode::INSERT_SUBREG:
226
case TargetOpcode::EXTRACT_SUBREG:
227
llvm_unreachable("Sub-register pseudos should have been eliminated.");