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//===- RegisterCoalescer.cpp - Generic Register Coalescing Interface -------==//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This file implements the generic RegisterCoalescer interface which
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// is used as the common interface used by all clients and
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// implementations of register coalescing.
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "RegisterCoalescer.h"
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#include "LiveDebugVariables.h"
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#include "RegisterClassInfo.h"
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#include "VirtRegMap.h"
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#include "llvm/Pass.h"
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#include "llvm/Value.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/OwningPtr.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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STATISTIC(numJoins , "Number of interval joins performed");
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STATISTIC(numCrossRCs , "Number of cross class joins performed");
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STATISTIC(numCommutes , "Number of instruction commuting performed");
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STATISTIC(numExtends , "Number of copies extended");
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STATISTIC(NumReMats , "Number of instructions re-materialized");
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STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
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STATISTIC(numAborts , "Number of times interval joining aborted");
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STATISTIC(NumInflated , "Number of register classes inflated");
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EnableJoining("join-liveintervals",
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cl::desc("Coalesce copies (default=true)"),
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DisableCrossClassJoin("disable-cross-class-join",
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cl::desc("Avoid coalescing cross register class copies"),
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cl::init(false), cl::Hidden);
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EnablePhysicalJoin("join-physregs",
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cl::desc("Join physical register copies"),
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cl::init(false), cl::Hidden);
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VerifyCoalescing("verify-coalescing",
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cl::desc("Verify machine instrs before and after register coalescing"),
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class RegisterCoalescer : public MachineFunctionPass {
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MachineRegisterInfo* MRI;
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const TargetMachine* TM;
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const TargetRegisterInfo* TRI;
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const TargetInstrInfo* TII;
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LiveDebugVariables *LDV;
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const MachineLoopInfo* Loops;
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RegisterClassInfo RegClassInfo;
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/// JoinedCopies - Keep track of copies eliminated due to coalescing.
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SmallPtrSet<MachineInstr*, 32> JoinedCopies;
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/// ReMatCopies - Keep track of copies eliminated due to remat.
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SmallPtrSet<MachineInstr*, 32> ReMatCopies;
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/// ReMatDefs - Keep track of definition instructions which have
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SmallPtrSet<MachineInstr*, 8> ReMatDefs;
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/// joinIntervals - join compatible live intervals
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void joinIntervals();
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/// CopyCoalesceInMBB - Coalesce copies in the specified MBB, putting
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/// copies that cannot yet be coalesced into the "TryAgain" list.
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void CopyCoalesceInMBB(MachineBasicBlock *MBB,
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std::vector<MachineInstr*> &TryAgain);
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/// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
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/// which are the src/dst of the copy instruction CopyMI. This returns
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/// true if the copy was successfully coalesced away. If it is not
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/// currently possible to coalesce this interval, but it may be possible if
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/// other things get coalesced, then it returns true by reference in
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bool JoinCopy(MachineInstr *TheCopy, bool &Again);
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/// JoinIntervals - Attempt to join these two intervals. On failure, this
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/// returns false. The output "SrcInt" will not have been modified, so we
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/// can use this information below to update aliases.
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bool JoinIntervals(CoalescerPair &CP);
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/// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
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/// the source value number is defined by a copy from the destination reg
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/// see if we can merge these two destination reg valno# into a single
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/// value number, eliminating a copy.
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bool AdjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
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/// HasOtherReachingDefs - Return true if there are definitions of IntB
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/// other than BValNo val# that can reach uses of AValno val# of IntA.
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bool HasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
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VNInfo *AValNo, VNInfo *BValNo);
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/// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy.
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/// If the source value number is defined by a commutable instruction and
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/// its other operand is coalesced to the copy dest register, see if we
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/// can transform the copy into a noop by commuting the definition.
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bool RemoveCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI);
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/// ReMaterializeTrivialDef - If the source of a copy is defined by a
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/// trivial computation, replace the copy by rematerialize the definition.
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/// If PreserveSrcInt is true, make sure SrcInt is valid after the call.
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bool ReMaterializeTrivialDef(LiveInterval &SrcInt, bool PreserveSrcInt,
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unsigned DstReg, MachineInstr *CopyMI);
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/// shouldJoinPhys - Return true if a physreg copy should be joined.
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bool shouldJoinPhys(CoalescerPair &CP);
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/// isWinToJoinCrossClass - Return true if it's profitable to coalesce
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/// two virtual registers from different register classes.
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bool isWinToJoinCrossClass(unsigned SrcReg,
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const TargetRegisterClass *SrcRC,
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const TargetRegisterClass *DstRC,
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const TargetRegisterClass *NewRC);
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/// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
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/// update the subregister number if it is not zero. If DstReg is a
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/// physical register and the existing subregister number of the def / use
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/// being updated is not zero, make sure to set it to the correct physical
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void UpdateRegDefsUses(const CoalescerPair &CP);
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/// RemoveDeadDef - If a def of a live interval is now determined dead,
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/// remove the val# it defines. If the live interval becomes empty, remove
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bool RemoveDeadDef(LiveInterval &li, MachineInstr *DefMI);
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/// markAsJoined - Remember that CopyMI has already been joined.
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void markAsJoined(MachineInstr *CopyMI);
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/// eliminateUndefCopy - Handle copies of undef values.
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bool eliminateUndefCopy(MachineInstr *CopyMI, const CoalescerPair &CP);
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static char ID; // Class identification, replacement for typeinfo
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RegisterCoalescer() : MachineFunctionPass(ID) {
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initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual void releaseMemory();
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/// runOnMachineFunction - pass entry point
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virtual bool runOnMachineFunction(MachineFunction&);
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/// print - Implement the dump method.
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virtual void print(raw_ostream &O, const Module* = 0) const;
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} /// end anonymous namespace
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char &llvm::RegisterCoalescerID = RegisterCoalescer::ID;
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INITIALIZE_PASS_BEGIN(RegisterCoalescer, "simple-register-coalescing",
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"Simple Register Coalescing", false, false)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
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INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
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INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
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INITIALIZE_PASS_END(RegisterCoalescer, "simple-register-coalescing",
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"Simple Register Coalescing", false, false)
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char RegisterCoalescer::ID = 0;
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static unsigned compose(const TargetRegisterInfo &tri, unsigned a, unsigned b) {
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return tri.composeSubRegIndices(a, b);
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static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI,
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unsigned &Src, unsigned &Dst,
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unsigned &SrcSub, unsigned &DstSub) {
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Dst = MI->getOperand(0).getReg();
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DstSub = MI->getOperand(0).getSubReg();
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Src = MI->getOperand(1).getReg();
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SrcSub = MI->getOperand(1).getSubReg();
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} else if (MI->isSubregToReg()) {
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Dst = MI->getOperand(0).getReg();
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DstSub = compose(tri, MI->getOperand(0).getSubReg(),
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MI->getOperand(3).getImm());
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Src = MI->getOperand(2).getReg();
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SrcSub = MI->getOperand(2).getSubReg();
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bool CoalescerPair::setRegisters(const MachineInstr *MI) {
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SrcReg = DstReg = SubIdx = 0;
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Flipped = CrossClass = false;
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unsigned Src, Dst, SrcSub, DstSub;
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if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
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Partial = SrcSub || DstSub;
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// If one register is a physreg, it must be Dst.
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if (TargetRegisterInfo::isPhysicalRegister(Src)) {
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if (TargetRegisterInfo::isPhysicalRegister(Dst))
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std::swap(SrcSub, DstSub);
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const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
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if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
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// Eliminate DstSub on a physreg.
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Dst = TRI.getSubReg(Dst, DstSub);
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if (!Dst) return false;
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// Eliminate SrcSub by picking a corresponding Dst superregister.
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Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
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if (!Dst) return false;
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} else if (!MRI.getRegClass(Src)->contains(Dst)) {
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// Both registers are virtual.
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// Both registers have subreg indices.
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if (SrcSub && DstSub) {
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// For now we only handle the case of identical indices in commensurate
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// registers: Dreg:ssub_1 + Dreg:ssub_1 -> Dreg
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// FIXME: Handle Qreg:ssub_3 + Dreg:ssub_1 as QReg:dsub_1 + Dreg.
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if (SrcSub != DstSub)
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const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
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const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
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if (!TRI.getCommonSubClass(DstRC, SrcRC))
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// There can be no SrcSub.
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assert(!Flipped && "Unexpected flip");
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// Find the new register class.
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const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
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const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
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NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
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NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
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CrossClass = NewRC != DstRC || NewRC != SrcRC;
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// Check our invariants
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assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual");
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assert(!(TargetRegisterInfo::isPhysicalRegister(Dst) && DstSub) &&
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"Cannot have a physical SubIdx");
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bool CoalescerPair::flip() {
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if (SubIdx || TargetRegisterInfo::isPhysicalRegister(DstReg))
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std::swap(SrcReg, DstReg);
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bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
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unsigned Src, Dst, SrcSub, DstSub;
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if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
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// Find the virtual register that is SrcReg.
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std::swap(SrcSub, DstSub);
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} else if (Src != SrcReg) {
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// Now check that Dst matches DstReg.
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if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
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if (!TargetRegisterInfo::isPhysicalRegister(Dst))
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assert(!SubIdx && "Inconsistent CoalescerPair state.");
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// DstSub could be set for a physreg from INSERT_SUBREG.
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Dst = TRI.getSubReg(Dst, DstSub);
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return DstReg == Dst;
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// This is a partial register copy. Check that the parts match.
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return TRI.getSubReg(DstReg, SrcSub) == Dst;
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// DstReg is virtual.
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// Registers match, do the subregisters line up?
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return compose(TRI, SubIdx, SrcSub) == DstSub;
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void RegisterCoalescer::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<AliasAnalysis>();
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AU.addRequired<LiveIntervals>();
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AU.addPreserved<LiveIntervals>();
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AU.addRequired<LiveDebugVariables>();
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AU.addPreserved<LiveDebugVariables>();
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AU.addPreserved<SlotIndexes>();
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineLoopInfo>();
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AU.addPreservedID(MachineDominatorsID);
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MachineFunctionPass::getAnalysisUsage(AU);
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void RegisterCoalescer::markAsJoined(MachineInstr *CopyMI) {
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/// Joined copies are not deleted immediately, but kept in JoinedCopies.
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JoinedCopies.insert(CopyMI);
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/// Mark all register operands of CopyMI as <undef> so they won't affect dead
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/// code elimination.
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for (MachineInstr::mop_iterator I = CopyMI->operands_begin(),
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E = CopyMI->operands_end(); I != E; ++I)
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/// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
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/// being the source and IntB being the dest, thus this defines a value number
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/// in IntB. If the source value number (in IntA) is defined by a copy from B,
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/// see if we can merge these two pieces of B into a single value number,
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/// eliminating a copy. For example:
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/// B1 = A3 <- this copy
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/// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
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/// value number to be replaced with B0 (which simplifies the B liveinterval).
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/// This returns true if an interval was modified.
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bool RegisterCoalescer::AdjustCopiesBackFrom(const CoalescerPair &CP,
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MachineInstr *CopyMI) {
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// Bail if there is no dst interval - can happen when merging physical subreg
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if (!LIS->hasInterval(CP.getDstReg()))
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LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
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LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
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SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
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// BValNo is a value number in B that is defined by a copy from A. 'B3' in
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// the example above.
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LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
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if (BLR == IntB.end()) return false;
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VNInfo *BValNo = BLR->valno;
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// Get the location that B is defined at. Two options: either this value has
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// an unknown definition point or it is defined at CopyIdx. If unknown, we
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if (BValNo->def != CopyIdx) return false;
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// AValNo is the value number in A that defines the copy, A3 in the example.
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SlotIndex CopyUseIdx = CopyIdx.getRegSlot(true);
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LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
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// The live range might not exist after fun with physreg coalescing.
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if (ALR == IntA.end()) return false;
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VNInfo *AValNo = ALR->valno;
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// If AValNo is defined as a copy from IntB, we can potentially process this.
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// Get the instruction that defines this value number.
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MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def);
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if (!CP.isCoalescable(ACopyMI))
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// Get the LiveRange in IntB that this value number starts with.
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LiveInterval::iterator ValLR =
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IntB.FindLiveRangeContaining(AValNo->def.getPrevSlot());
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if (ValLR == IntB.end())
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// Make sure that the end of the live range is inside the same block as
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MachineInstr *ValLREndInst =
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LIS->getInstructionFromIndex(ValLR->end.getPrevSlot());
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if (!ValLREndInst || ValLREndInst->getParent() != CopyMI->getParent())
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// Okay, we now know that ValLR ends in the same block that the CopyMI
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// live-range starts. If there are no intervening live ranges between them in
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// IntB, we can merge them.
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if (ValLR+1 != BLR) return false;
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// If a live interval is a physical register, conservatively check if any
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// of its aliases is overlapping the live interval of the virtual register.
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// If so, do not coalesce.
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if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
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for (const uint16_t *AS = TRI->getAliasSet(IntB.reg); *AS; ++AS)
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if (LIS->hasInterval(*AS) && IntA.overlaps(LIS->getInterval(*AS))) {
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dbgs() << "\t\tInterfere with alias ";
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LIS->getInterval(*AS).print(dbgs(), TRI);
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dbgs() << "Extending: ";
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IntB.print(dbgs(), TRI);
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SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
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// We are about to delete CopyMI, so need to remove it as the 'instruction
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// that defines this value #'. Update the valnum with the new defining
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BValNo->def = FillerStart;
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// Okay, we can merge them. We need to insert a new liverange:
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// [ValLR.end, BLR.begin) of either value number, then we merge the
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// two value numbers.
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IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
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// If the IntB live range is assigned to a physical register, and if that
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// physreg has sub-registers, update their live intervals as well.
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if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
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for (const uint16_t *SR = TRI->getSubRegisters(IntB.reg); *SR; ++SR) {
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if (!LIS->hasInterval(*SR))
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LiveInterval &SRLI = LIS->getInterval(*SR);
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SRLI.addRange(LiveRange(FillerStart, FillerEnd,
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SRLI.getNextValue(FillerStart,
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LIS->getVNInfoAllocator())));
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// Okay, merge "B1" into the same value number as "B0".
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if (BValNo != ValLR->valno) {
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// If B1 is killed by a PHI, then the merged live range must also be killed
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// by the same PHI, as B0 and B1 can not overlap.
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bool HasPHIKill = BValNo->hasPHIKill();
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IntB.MergeValueNumberInto(BValNo, ValLR->valno);
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ValLR->valno->setHasPHIKill(true);
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dbgs() << " result = ";
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IntB.print(dbgs(), TRI);
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// If the source instruction was killing the source register before the
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// merge, unset the isKill marker given the live range has been extended.
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int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
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ValLREndInst->getOperand(UIdx).setIsKill(false);
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// Rewrite the copy. If the copy instruction was killing the destination
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// register before the merge, find the last use and trim the live range. That
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// will also add the isKill marker.
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CopyMI->substituteRegister(IntA.reg, IntB.reg, CP.getSubIdx(),
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if (ALR->end == CopyIdx)
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LIS->shrinkToUses(&IntA);
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/// HasOtherReachingDefs - Return true if there are definitions of IntB
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/// other than BValNo val# that can reach uses of AValno val# of IntA.
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bool RegisterCoalescer::HasOtherReachingDefs(LiveInterval &IntA,
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for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
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if (AI->valno != AValNo) continue;
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LiveInterval::Ranges::iterator BI =
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std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
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if (BI != IntB.ranges.begin())
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for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
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if (BI->valno == BValNo)
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if (BI->start <= AI->start && BI->end > AI->start)
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if (BI->start > AI->start && BI->start < AI->end)
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/// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with
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/// IntA being the source and IntB being the dest, thus this defines a value
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/// number in IntB. If the source value number (in IntA) is defined by a
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/// commutable instruction and its other operand is coalesced to the copy dest
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/// register, see if we can transform the copy into a noop by commuting the
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/// definition. For example,
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/// A3 = op A2 B0<kill>
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/// B1 = A3 <- this copy
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/// = op A3 <- more uses
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/// B2 = op B0 A2<kill>
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/// B1 = B2 <- now an identify copy
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/// = op B2 <- more uses
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/// This returns true if an interval was modified.
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bool RegisterCoalescer::RemoveCopyByCommutingDef(const CoalescerPair &CP,
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MachineInstr *CopyMI) {
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// FIXME: For now, only eliminate the copy by commuting its def when the
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// source register is a virtual register. We want to guard against cases
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// where the copy is a back edge copy and commuting the def lengthen the
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// live interval of the source register to the entire loop.
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if (CP.isPhys() && CP.isFlipped())
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// Bail if there is no dst interval.
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if (!LIS->hasInterval(CP.getDstReg()))
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SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
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LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
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LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
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// BValNo is a value number in B that is defined by a copy from A. 'B3' in
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// the example above.
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VNInfo *BValNo = IntB.getVNInfoAt(CopyIdx);
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if (!BValNo || BValNo->def != CopyIdx)
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assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
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// AValNo is the value number in A that defines the copy, A3 in the example.
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VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getRegSlot(true));
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assert(AValNo && "COPY source not live");
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// If other defs can reach uses of this def, then it's not safe to perform
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if (AValNo->isPHIDef() || AValNo->isUnused() || AValNo->hasPHIKill())
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MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
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if (!DefMI->isCommutable())
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// If DefMI is a two-address instruction then commuting it will change the
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// destination register.
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int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
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assert(DefIdx != -1);
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if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
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unsigned Op1, Op2, NewDstIdx;
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if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
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else if (Op2 == UseOpIdx)
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MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
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unsigned NewReg = NewDstMO.getReg();
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if (NewReg != IntB.reg || !NewDstMO.isKill())
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// Make sure there are no other definitions of IntB that would reach the
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// uses which the new definition can reach.
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if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
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// Abort if the aliases of IntB.reg have values that are not simply the
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// clobbers from the superreg.
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if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
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for (const uint16_t *AS = TRI->getAliasSet(IntB.reg); *AS; ++AS)
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if (LIS->hasInterval(*AS) &&
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HasOtherReachingDefs(IntA, LIS->getInterval(*AS), AValNo, 0))
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// If some of the uses of IntA.reg is already coalesced away, return false.
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// It's not possible to determine whether it's safe to perform the coalescing.
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for (MachineRegisterInfo::use_nodbg_iterator UI =
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MRI->use_nodbg_begin(IntA.reg),
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UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
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MachineInstr *UseMI = &*UI;
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SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
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LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
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if (ULR == IntA.end())
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if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
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DEBUG(dbgs() << "\tRemoveCopyByCommutingDef: " << AValNo->def << '\t'
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// At this point we have decided that it is legal to do this
679
// transformation. Start by commuting the instruction.
680
MachineBasicBlock *MBB = DefMI->getParent();
681
MachineInstr *NewMI = TII->commuteInstruction(DefMI);
684
if (TargetRegisterInfo::isVirtualRegister(IntA.reg) &&
685
TargetRegisterInfo::isVirtualRegister(IntB.reg) &&
686
!MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
688
if (NewMI != DefMI) {
689
LIS->ReplaceMachineInstrInMaps(DefMI, NewMI);
690
MachineBasicBlock::iterator Pos = DefMI;
691
MBB->insert(Pos, NewMI);
694
unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
695
NewMI->getOperand(OpIdx).setIsKill();
697
// If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
706
// Update uses of IntA of the specific Val# with IntB.
707
for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(IntA.reg),
708
UE = MRI->use_end(); UI != UE;) {
709
MachineOperand &UseMO = UI.getOperand();
710
MachineInstr *UseMI = &*UI;
712
if (JoinedCopies.count(UseMI))
714
if (UseMI->isDebugValue()) {
715
// FIXME These don't have an instruction index. Not clear we have enough
716
// info to decide whether to do this replacement or not. For now do it.
717
UseMO.setReg(NewReg);
720
SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true);
721
LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
722
if (ULR == IntA.end() || ULR->valno != AValNo)
724
if (TargetRegisterInfo::isPhysicalRegister(NewReg))
725
UseMO.substPhysReg(NewReg, *TRI);
727
UseMO.setReg(NewReg);
730
if (!UseMI->isCopy())
732
if (UseMI->getOperand(0).getReg() != IntB.reg ||
733
UseMI->getOperand(0).getSubReg())
736
// This copy will become a noop. If it's defining a new val#, merge it into
738
SlotIndex DefIdx = UseIdx.getRegSlot();
739
VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
742
DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
743
assert(DVNI->def == DefIdx);
744
BValNo = IntB.MergeValueNumberInto(BValNo, DVNI);
748
// Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
750
VNInfo *ValNo = BValNo;
751
ValNo->def = AValNo->def;
752
for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
754
if (AI->valno != AValNo) continue;
755
IntB.addRange(LiveRange(AI->start, AI->end, ValNo));
757
DEBUG(dbgs() << "\t\textended: " << IntB << '\n');
759
IntA.removeValNo(AValNo);
760
DEBUG(dbgs() << "\t\ttrimmed: " << IntA << '\n');
765
/// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
766
/// computation, replace the copy by rematerialize the definition.
767
bool RegisterCoalescer::ReMaterializeTrivialDef(LiveInterval &SrcInt,
770
MachineInstr *CopyMI) {
771
SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(true);
772
LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
773
assert(SrcLR != SrcInt.end() && "Live range not found!");
774
VNInfo *ValNo = SrcLR->valno;
775
if (ValNo->isPHIDef() || ValNo->isUnused())
777
MachineInstr *DefMI = LIS->getInstructionFromIndex(ValNo->def);
780
assert(DefMI && "Defining instruction disappeared");
781
if (!DefMI->isAsCheapAsAMove())
783
if (!TII->isTriviallyReMaterializable(DefMI, AA))
785
bool SawStore = false;
786
if (!DefMI->isSafeToMove(TII, AA, SawStore))
788
const MCInstrDesc &MCID = DefMI->getDesc();
789
if (MCID.getNumDefs() != 1)
791
if (!DefMI->isImplicitDef()) {
792
// Make sure the copy destination register class fits the instruction
793
// definition register class. The mismatch can happen as a result of earlier
794
// extract_subreg, insert_subreg, subreg_to_reg coalescing.
795
const TargetRegisterClass *RC = TII->getRegClass(MCID, 0, TRI);
796
if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
797
if (MRI->getRegClass(DstReg) != RC)
799
} else if (!RC->contains(DstReg))
803
MachineBasicBlock *MBB = CopyMI->getParent();
804
MachineBasicBlock::iterator MII =
805
llvm::next(MachineBasicBlock::iterator(CopyMI));
806
TII->reMaterialize(*MBB, MII, DstReg, 0, DefMI, *TRI);
807
MachineInstr *NewMI = prior(MII);
809
// NewMI may have dead implicit defs (E.g. EFLAGS for MOV<bits>r0 on X86).
810
// We need to remember these so we can add intervals once we insert
811
// NewMI into SlotIndexes.
812
SmallVector<unsigned, 4> NewMIImplDefs;
813
for (unsigned i = NewMI->getDesc().getNumOperands(),
814
e = NewMI->getNumOperands(); i != e; ++i) {
815
MachineOperand &MO = NewMI->getOperand(i);
817
assert(MO.isDef() && MO.isImplicit() && MO.isDead() &&
818
TargetRegisterInfo::isPhysicalRegister(MO.getReg()));
819
NewMIImplDefs.push_back(MO.getReg());
823
// CopyMI may have implicit operands, transfer them over to the newly
824
// rematerialized instruction. And update implicit def interval valnos.
825
for (unsigned i = CopyMI->getDesc().getNumOperands(),
826
e = CopyMI->getNumOperands(); i != e; ++i) {
827
MachineOperand &MO = CopyMI->getOperand(i);
829
assert(MO.isImplicit() && "No explicit operands after implict operands.");
830
// Discard VReg implicit defs.
831
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
832
NewMI->addOperand(MO);
837
LIS->ReplaceMachineInstrInMaps(CopyMI, NewMI);
839
SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
840
for (unsigned i = 0, e = NewMIImplDefs.size(); i != e; ++i) {
841
unsigned reg = NewMIImplDefs[i];
842
LiveInterval &li = LIS->getInterval(reg);
843
VNInfo *DeadDefVN = li.getNextValue(NewMIIdx.getRegSlot(),
844
LIS->getVNInfoAllocator());
845
LiveRange lr(NewMIIdx.getRegSlot(), NewMIIdx.getDeadSlot(), DeadDefVN);
849
CopyMI->eraseFromParent();
850
ReMatCopies.insert(CopyMI);
851
ReMatDefs.insert(DefMI);
852
DEBUG(dbgs() << "Remat: " << *NewMI);
855
// The source interval can become smaller because we removed a use.
857
LIS->shrinkToUses(&SrcInt);
862
/// eliminateUndefCopy - ProcessImpicitDefs may leave some copies of <undef>
863
/// values, it only removes local variables. When we have a copy like:
865
/// %vreg1 = COPY %vreg2<undef>
867
/// We delete the copy and remove the corresponding value number from %vreg1.
868
/// Any uses of that value number are marked as <undef>.
869
bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI,
870
const CoalescerPair &CP) {
871
SlotIndex Idx = LIS->getInstructionIndex(CopyMI);
872
LiveInterval *SrcInt = &LIS->getInterval(CP.getSrcReg());
873
if (SrcInt->liveAt(Idx))
875
LiveInterval *DstInt = &LIS->getInterval(CP.getDstReg());
876
if (DstInt->liveAt(Idx))
879
// No intervals are live-in to CopyMI - it is undef.
884
VNInfo *DeadVNI = DstInt->getVNInfoAt(Idx.getRegSlot());
885
assert(DeadVNI && "No value defined in DstInt");
886
DstInt->removeValNo(DeadVNI);
888
// Find new undef uses.
889
for (MachineRegisterInfo::reg_nodbg_iterator
890
I = MRI->reg_nodbg_begin(DstInt->reg), E = MRI->reg_nodbg_end();
892
MachineOperand &MO = I.getOperand();
893
if (MO.isDef() || MO.isUndef())
895
MachineInstr *MI = MO.getParent();
896
SlotIndex Idx = LIS->getInstructionIndex(MI);
897
if (DstInt->liveAt(Idx))
900
DEBUG(dbgs() << "\tnew undef: " << Idx << '\t' << *MI);
905
/// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
906
/// update the subregister number if it is not zero. If DstReg is a
907
/// physical register and the existing subregister number of the def / use
908
/// being updated is not zero, make sure to set it to the correct physical
911
RegisterCoalescer::UpdateRegDefsUses(const CoalescerPair &CP) {
912
bool DstIsPhys = CP.isPhys();
913
unsigned SrcReg = CP.getSrcReg();
914
unsigned DstReg = CP.getDstReg();
915
unsigned SubIdx = CP.getSubIdx();
917
// Update LiveDebugVariables.
918
LDV->renameRegister(SrcReg, DstReg, SubIdx);
920
for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg);
921
MachineInstr *UseMI = I.skipInstruction();) {
922
// A PhysReg copy that won't be coalesced can perhaps be rematerialized
925
if (UseMI->isFullCopy() &&
926
UseMI->getOperand(1).getReg() == SrcReg &&
927
UseMI->getOperand(0).getReg() != SrcReg &&
928
UseMI->getOperand(0).getReg() != DstReg &&
929
!JoinedCopies.count(UseMI) &&
930
ReMaterializeTrivialDef(LIS->getInterval(SrcReg), false,
931
UseMI->getOperand(0).getReg(), UseMI))
935
SmallVector<unsigned,8> Ops;
937
tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
939
// Replace SrcReg with DstReg in all UseMI operands.
940
for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
941
MachineOperand &MO = UseMI->getOperand(Ops[i]);
943
// Make sure we don't create read-modify-write defs accidentally. We
944
// assume here that a SrcReg def cannot be joined into a live DstReg. If
945
// RegisterCoalescer starts tracking partially live registers, we will
946
// need to check the actual LiveInterval to determine if DstReg is live
948
if (SubIdx && !Reads)
952
MO.substPhysReg(DstReg, *TRI);
954
MO.substVirtReg(DstReg, SubIdx, *TRI);
957
// This instruction is a copy that will be removed.
958
if (JoinedCopies.count(UseMI))
962
dbgs() << "\t\tupdated: ";
963
if (!UseMI->isDebugValue())
964
dbgs() << LIS->getInstructionIndex(UseMI) << "\t";
970
/// removeIntervalIfEmpty - Check if the live interval of a physical register
971
/// is empty, if so remove it and also remove the empty intervals of its
972
/// sub-registers. Return true if live interval is removed.
973
static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *LIS,
974
const TargetRegisterInfo *TRI) {
976
if (TargetRegisterInfo::isPhysicalRegister(li.reg))
977
for (const uint16_t* SR = TRI->getSubRegisters(li.reg); *SR; ++SR) {
978
if (!LIS->hasInterval(*SR))
980
LiveInterval &sli = LIS->getInterval(*SR);
982
LIS->removeInterval(*SR);
984
LIS->removeInterval(li.reg);
990
/// RemoveDeadDef - If a def of a live interval is now determined dead, remove
991
/// the val# it defines. If the live interval becomes empty, remove it as well.
992
bool RegisterCoalescer::RemoveDeadDef(LiveInterval &li,
993
MachineInstr *DefMI) {
994
SlotIndex DefIdx = LIS->getInstructionIndex(DefMI).getRegSlot();
995
LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
996
if (DefIdx != MLR->valno->def)
998
li.removeValNo(MLR->valno);
999
return removeIntervalIfEmpty(li, LIS, TRI);
1002
/// shouldJoinPhys - Return true if a copy involving a physreg should be joined.
1003
/// We need to be careful about coalescing a source physical register with a
1004
/// virtual register. Once the coalescing is done, it cannot be broken and these
1005
/// are not spillable! If the destination interval uses are far away, think
1006
/// twice about coalescing them!
1007
bool RegisterCoalescer::shouldJoinPhys(CoalescerPair &CP) {
1008
bool Allocatable = LIS->isAllocatable(CP.getDstReg());
1009
LiveInterval &JoinVInt = LIS->getInterval(CP.getSrcReg());
1011
/// Always join simple intervals that are defined by a single copy from a
1012
/// reserved register. This doesn't increase register pressure, so it is
1013
/// always beneficial.
1014
if (!Allocatable && CP.isFlipped() && JoinVInt.containsOneValue())
1017
if (!EnablePhysicalJoin) {
1018
DEBUG(dbgs() << "\tPhysreg joins disabled.\n");
1022
// Only coalesce to allocatable physreg, we don't want to risk modifying
1023
// reserved registers.
1025
DEBUG(dbgs() << "\tRegister is an unallocatable physreg.\n");
1026
return false; // Not coalescable.
1029
// Don't join with physregs that have a ridiculous number of live
1030
// ranges. The data structure performance is really bad when that
1032
if (LIS->hasInterval(CP.getDstReg()) &&
1033
LIS->getInterval(CP.getDstReg()).ranges.size() > 1000) {
1036
<< "\tPhysical register live interval too complicated, abort!\n");
1040
// FIXME: Why are we skipping this test for partial copies?
1041
// CodeGen/X86/phys_subreg_coalesce-3.ll needs it.
1042
if (!CP.isPartial()) {
1043
const TargetRegisterClass *RC = MRI->getRegClass(CP.getSrcReg());
1044
unsigned Threshold = RegClassInfo.getNumAllocatableRegs(RC) * 2;
1045
unsigned Length = LIS->getApproximateInstructionCount(JoinVInt);
1046
if (Length > Threshold) {
1048
DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
1055
/// isWinToJoinCrossClass - Return true if it's profitable to coalesce
1056
/// two virtual registers from different register classes.
1058
RegisterCoalescer::isWinToJoinCrossClass(unsigned SrcReg,
1060
const TargetRegisterClass *SrcRC,
1061
const TargetRegisterClass *DstRC,
1062
const TargetRegisterClass *NewRC) {
1063
unsigned NewRCCount = RegClassInfo.getNumAllocatableRegs(NewRC);
1064
// This heuristics is good enough in practice, but it's obviously not *right*.
1065
// 4 is a magic number that works well enough for x86, ARM, etc. It filter
1066
// out all but the most restrictive register classes.
1067
if (NewRCCount > 4 ||
1068
// Early exit if the function is fairly small, coalesce aggressively if
1069
// that's the case. For really special register classes with 3 or
1070
// fewer registers, be a bit more careful.
1071
(LIS->getFuncInstructionCount() / NewRCCount) < 8)
1073
LiveInterval &SrcInt = LIS->getInterval(SrcReg);
1074
LiveInterval &DstInt = LIS->getInterval(DstReg);
1075
unsigned SrcSize = LIS->getApproximateInstructionCount(SrcInt);
1076
unsigned DstSize = LIS->getApproximateInstructionCount(DstInt);
1078
// Coalesce aggressively if the intervals are small compared to the number of
1079
// registers in the new class. The number 4 is fairly arbitrary, chosen to be
1080
// less aggressive than the 8 used for the whole function size.
1081
const unsigned ThresSize = 4 * NewRCCount;
1082
if (SrcSize <= ThresSize && DstSize <= ThresSize)
1085
// Estimate *register use density*. If it doubles or more, abort.
1086
unsigned SrcUses = std::distance(MRI->use_nodbg_begin(SrcReg),
1087
MRI->use_nodbg_end());
1088
unsigned DstUses = std::distance(MRI->use_nodbg_begin(DstReg),
1089
MRI->use_nodbg_end());
1090
unsigned NewUses = SrcUses + DstUses;
1091
unsigned NewSize = SrcSize + DstSize;
1092
if (SrcRC != NewRC && SrcSize > ThresSize) {
1093
unsigned SrcRCCount = RegClassInfo.getNumAllocatableRegs(SrcRC);
1094
if (NewUses*SrcSize*SrcRCCount > 2*SrcUses*NewSize*NewRCCount)
1097
if (DstRC != NewRC && DstSize > ThresSize) {
1098
unsigned DstRCCount = RegClassInfo.getNumAllocatableRegs(DstRC);
1099
if (NewUses*DstSize*DstRCCount > 2*DstUses*NewSize*NewRCCount)
1106
/// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1107
/// which are the src/dst of the copy instruction CopyMI. This returns true
1108
/// if the copy was successfully coalesced away. If it is not currently
1109
/// possible to coalesce this interval, but it may be possible if other
1110
/// things get coalesced, then it returns true by reference in 'Again'.
1111
bool RegisterCoalescer::JoinCopy(MachineInstr *CopyMI, bool &Again) {
1114
if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
1115
return false; // Already done.
1117
DEBUG(dbgs() << LIS->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
1119
CoalescerPair CP(*TII, *TRI);
1120
if (!CP.setRegisters(CopyMI)) {
1121
DEBUG(dbgs() << "\tNot coalescable.\n");
1125
// If they are already joined we continue.
1126
if (CP.getSrcReg() == CP.getDstReg()) {
1127
markAsJoined(CopyMI);
1128
DEBUG(dbgs() << "\tCopy already coalesced.\n");
1129
return false; // Not coalescable.
1132
// Eliminate undefs.
1133
if (!CP.isPhys() && eliminateUndefCopy(CopyMI, CP)) {
1134
markAsJoined(CopyMI);
1135
DEBUG(dbgs() << "\tEliminated copy of <undef> value.\n");
1136
return false; // Not coalescable.
1139
DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), TRI)
1140
<< " with " << PrintReg(CP.getDstReg(), TRI, CP.getSubIdx())
1143
// Enforce policies.
1145
if (!shouldJoinPhys(CP)) {
1146
// Before giving up coalescing, if definition of source is defined by
1147
// trivial computation, try rematerializing it.
1148
if (!CP.isFlipped() &&
1149
ReMaterializeTrivialDef(LIS->getInterval(CP.getSrcReg()), true,
1150
CP.getDstReg(), CopyMI))
1155
// Avoid constraining virtual register regclass too much.
1156
if (CP.isCrossClass()) {
1157
DEBUG(dbgs() << "\tCross-class to " << CP.getNewRC()->getName() << ".\n");
1158
if (DisableCrossClassJoin) {
1159
DEBUG(dbgs() << "\tCross-class joins disabled.\n");
1162
if (!isWinToJoinCrossClass(CP.getSrcReg(), CP.getDstReg(),
1163
MRI->getRegClass(CP.getSrcReg()),
1164
MRI->getRegClass(CP.getDstReg()),
1166
DEBUG(dbgs() << "\tAvoid coalescing to constrained register class.\n");
1167
Again = true; // May be possible to coalesce later.
1172
// When possible, let DstReg be the larger interval.
1173
if (!CP.getSubIdx() && LIS->getInterval(CP.getSrcReg()).ranges.size() >
1174
LIS->getInterval(CP.getDstReg()).ranges.size())
1178
// Okay, attempt to join these two intervals. On failure, this returns false.
1179
// Otherwise, if one of the intervals being joined is a physreg, this method
1180
// always canonicalizes DstInt to be it. The output "SrcInt" will not have
1181
// been modified, so we can use this information below to update aliases.
1182
if (!JoinIntervals(CP)) {
1183
// Coalescing failed.
1185
// If definition of source is defined by trivial computation, try
1186
// rematerializing it.
1187
if (!CP.isFlipped() &&
1188
ReMaterializeTrivialDef(LIS->getInterval(CP.getSrcReg()), true,
1189
CP.getDstReg(), CopyMI))
1192
// If we can eliminate the copy without merging the live ranges, do so now.
1193
if (!CP.isPartial()) {
1194
if (AdjustCopiesBackFrom(CP, CopyMI) ||
1195
RemoveCopyByCommutingDef(CP, CopyMI)) {
1196
markAsJoined(CopyMI);
1197
DEBUG(dbgs() << "\tTrivial!\n");
1202
// Otherwise, we are unable to join the intervals.
1203
DEBUG(dbgs() << "\tInterference!\n");
1204
Again = true; // May be possible to coalesce later.
1208
// Coalescing to a virtual register that is of a sub-register class of the
1209
// other. Make sure the resulting register is set to the right register class.
1210
if (CP.isCrossClass()) {
1212
MRI->setRegClass(CP.getDstReg(), CP.getNewRC());
1215
// Remember to delete the copy instruction.
1216
markAsJoined(CopyMI);
1218
UpdateRegDefsUses(CP);
1220
// If we have extended the live range of a physical register, make sure we
1221
// update live-in lists as well.
1223
SmallVector<MachineBasicBlock*, 16> BlockSeq;
1224
// JoinIntervals invalidates the VNInfos in SrcInt, but we only need the
1225
// ranges for this, and they are preserved.
1226
LiveInterval &SrcInt = LIS->getInterval(CP.getSrcReg());
1227
for (LiveInterval::const_iterator I = SrcInt.begin(), E = SrcInt.end();
1229
LIS->findLiveInMBBs(I->start, I->end, BlockSeq);
1230
for (unsigned idx = 0, size = BlockSeq.size(); idx != size; ++idx) {
1231
MachineBasicBlock &block = *BlockSeq[idx];
1232
if (!block.isLiveIn(CP.getDstReg()))
1233
block.addLiveIn(CP.getDstReg());
1239
// SrcReg is guaranteed to be the register whose live interval that is
1241
LIS->removeInterval(CP.getSrcReg());
1243
// Update regalloc hint.
1244
TRI->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
1247
LiveInterval &DstInt = LIS->getInterval(CP.getDstReg());
1248
dbgs() << "\tJoined. Result = ";
1249
DstInt.print(dbgs(), TRI);
1257
/// ComputeUltimateVN - Assuming we are going to join two live intervals,
1258
/// compute what the resultant value numbers for each value in the input two
1259
/// ranges will be. This is complicated by copies between the two which can
1260
/// and will commonly cause multiple value numbers to be merged into one.
1262
/// VN is the value number that we're trying to resolve. InstDefiningValue
1263
/// keeps track of the new InstDefiningValue assignment for the result
1264
/// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1265
/// whether a value in this or other is a copy from the opposite set.
1266
/// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1267
/// already been assigned.
1269
/// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1270
/// contains the value number the copy is from.
1272
static unsigned ComputeUltimateVN(VNInfo *VNI,
1273
SmallVector<VNInfo*, 16> &NewVNInfo,
1274
DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1275
DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1276
SmallVector<int, 16> &ThisValNoAssignments,
1277
SmallVector<int, 16> &OtherValNoAssignments) {
1278
unsigned VN = VNI->id;
1280
// If the VN has already been computed, just return it.
1281
if (ThisValNoAssignments[VN] >= 0)
1282
return ThisValNoAssignments[VN];
1283
assert(ThisValNoAssignments[VN] != -2 && "Cyclic value numbers");
1285
// If this val is not a copy from the other val, then it must be a new value
1286
// number in the destination.
1287
DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1288
if (I == ThisFromOther.end()) {
1289
NewVNInfo.push_back(VNI);
1290
return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1292
VNInfo *OtherValNo = I->second;
1294
// Otherwise, this *is* a copy from the RHS. If the other side has already
1295
// been computed, return it.
1296
if (OtherValNoAssignments[OtherValNo->id] >= 0)
1297
return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1299
// Mark this value number as currently being computed, then ask what the
1300
// ultimate value # of the other value is.
1301
ThisValNoAssignments[VN] = -2;
1302
unsigned UltimateVN =
1303
ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1304
OtherValNoAssignments, ThisValNoAssignments);
1305
return ThisValNoAssignments[VN] = UltimateVN;
1309
// Find out if we have something like
1312
// if so, we can pretend this is actually
1315
// which allows us to coalesce A and B.
1316
// VNI is the definition of B. LR is the life range of A that includes
1317
// the slot just before B. If we return true, we add "B = X" to DupCopies.
1318
// This implies that A dominates B.
1319
static bool RegistersDefinedFromSameValue(LiveIntervals &li,
1320
const TargetRegisterInfo &tri,
1324
SmallVector<MachineInstr*, 8> &DupCopies) {
1325
// FIXME: This is very conservative. For example, we don't handle
1326
// physical registers.
1328
MachineInstr *MI = li.getInstructionFromIndex(VNI->def);
1330
if (!MI || !MI->isFullCopy() || CP.isPartial() || CP.isPhys())
1333
unsigned Dst = MI->getOperand(0).getReg();
1334
unsigned Src = MI->getOperand(1).getReg();
1336
if (!TargetRegisterInfo::isVirtualRegister(Src) ||
1337
!TargetRegisterInfo::isVirtualRegister(Dst))
1340
unsigned A = CP.getDstReg();
1341
unsigned B = CP.getSrcReg();
1347
VNInfo *Other = LR->valno;
1348
const MachineInstr *OtherMI = li.getInstructionFromIndex(Other->def);
1350
if (!OtherMI || !OtherMI->isFullCopy())
1353
unsigned OtherDst = OtherMI->getOperand(0).getReg();
1354
unsigned OtherSrc = OtherMI->getOperand(1).getReg();
1356
if (!TargetRegisterInfo::isVirtualRegister(OtherSrc) ||
1357
!TargetRegisterInfo::isVirtualRegister(OtherDst))
1360
assert(OtherDst == B);
1362
if (Src != OtherSrc)
1365
// If the copies use two different value numbers of X, we cannot merge
1367
LiveInterval &SrcInt = li.getInterval(Src);
1368
// getVNInfoBefore returns NULL for undef copies. In this case, the
1369
// optimization is still safe.
1370
if (SrcInt.getVNInfoBefore(Other->def) != SrcInt.getVNInfoBefore(VNI->def))
1373
DupCopies.push_back(MI);
1378
/// JoinIntervals - Attempt to join these two intervals. On failure, this
1380
bool RegisterCoalescer::JoinIntervals(CoalescerPair &CP) {
1381
LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
1382
DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), TRI); dbgs() << "\n"; });
1384
// If a live interval is a physical register, check for interference with any
1385
// aliases. The interference check implemented here is a bit more conservative
1386
// than the full interfeence check below. We allow overlapping live ranges
1387
// only when one is a copy of the other.
1389
// Optimization for reserved registers like ESP.
1390
// We can only merge with a reserved physreg if RHS has a single value that
1391
// is a copy of CP.DstReg(). The live range of the reserved register will
1392
// look like a set of dead defs - we don't properly track the live range of
1393
// reserved registers.
1394
if (RegClassInfo.isReserved(CP.getDstReg())) {
1395
assert(CP.isFlipped() && RHS.containsOneValue() &&
1396
"Invalid join with reserved register");
1397
// Deny any overlapping intervals. This depends on all the reserved
1398
// register live ranges to look like dead defs.
1399
for (const uint16_t *AS = TRI->getOverlaps(CP.getDstReg()); *AS; ++AS) {
1400
if (!LIS->hasInterval(*AS)) {
1401
// Make sure at least DstReg itself exists before attempting a join.
1402
if (*AS == CP.getDstReg())
1403
LIS->getOrCreateInterval(CP.getDstReg());
1406
if (RHS.overlaps(LIS->getInterval(*AS))) {
1407
DEBUG(dbgs() << "\t\tInterference: " << PrintReg(*AS, TRI) << '\n');
1411
// Skip any value computations, we are not adding new values to the
1412
// reserved register. Also skip merging the live ranges, the reserved
1413
// register live range doesn't need to be accurate as long as all the
1418
// Check if a register mask clobbers DstReg.
1419
BitVector UsableRegs;
1420
if (LIS->checkRegMaskInterference(RHS, UsableRegs) &&
1421
!UsableRegs.test(CP.getDstReg())) {
1422
DEBUG(dbgs() << "\t\tRegister mask interference.\n");
1426
for (const uint16_t *AS = TRI->getAliasSet(CP.getDstReg()); *AS; ++AS){
1427
if (!LIS->hasInterval(*AS))
1429
const LiveInterval &LHS = LIS->getInterval(*AS);
1430
LiveInterval::const_iterator LI = LHS.begin();
1431
for (LiveInterval::const_iterator RI = RHS.begin(), RE = RHS.end();
1433
LI = std::lower_bound(LI, LHS.end(), RI->start);
1434
// Does LHS have an overlapping live range starting before RI?
1435
if ((LI != LHS.begin() && LI[-1].end > RI->start) &&
1436
(RI->start != RI->valno->def ||
1437
!CP.isCoalescable(LIS->getInstructionFromIndex(RI->start)))) {
1439
dbgs() << "\t\tInterference from alias: ";
1440
LHS.print(dbgs(), TRI);
1441
dbgs() << "\n\t\tOverlap at " << RI->start << " and no copy.\n";
1446
// Check that LHS ranges beginning in this range are copies.
1447
for (; LI != LHS.end() && LI->start < RI->end; ++LI) {
1448
if (LI->start != LI->valno->def ||
1449
!CP.isCoalescable(LIS->getInstructionFromIndex(LI->start))) {
1451
dbgs() << "\t\tInterference from alias: ";
1452
LHS.print(dbgs(), TRI);
1453
dbgs() << "\n\t\tDef at " << LI->start << " is not a copy.\n";
1462
// Compute the final value assignment, assuming that the live ranges can be
1464
SmallVector<int, 16> LHSValNoAssignments;
1465
SmallVector<int, 16> RHSValNoAssignments;
1466
DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
1467
DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
1468
SmallVector<VNInfo*, 16> NewVNInfo;
1470
SmallVector<MachineInstr*, 8> DupCopies;
1472
LiveInterval &LHS = LIS->getOrCreateInterval(CP.getDstReg());
1473
DEBUG({ dbgs() << "\t\tLHS = "; LHS.print(dbgs(), TRI); dbgs() << "\n"; });
1475
// Loop over the value numbers of the LHS, seeing if any are defined from
1477
for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1480
if (VNI->isUnused() || VNI->isPHIDef())
1482
MachineInstr *MI = LIS->getInstructionFromIndex(VNI->def);
1483
assert(MI && "Missing def");
1484
if (!MI->isCopyLike()) // Src not defined by a copy?
1487
// Figure out the value # from the RHS.
1488
LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1489
// The copy could be to an aliased physreg.
1492
// DstReg is known to be a register in the LHS interval. If the src is
1493
// from the RHS interval, we can use its value #.
1494
if (!CP.isCoalescable(MI) &&
1495
!RegistersDefinedFromSameValue(*LIS, *TRI, CP, VNI, lr, DupCopies))
1498
LHSValsDefinedFromRHS[VNI] = lr->valno;
1501
// Loop over the value numbers of the RHS, seeing if any are defined from
1503
for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1506
if (VNI->isUnused() || VNI->isPHIDef())
1508
MachineInstr *MI = LIS->getInstructionFromIndex(VNI->def);
1509
assert(MI && "Missing def");
1510
if (!MI->isCopyLike()) // Src not defined by a copy?
1513
// Figure out the value # from the LHS.
1514
LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1515
// The copy could be to an aliased physreg.
1518
// DstReg is known to be a register in the RHS interval. If the src is
1519
// from the LHS interval, we can use its value #.
1520
if (!CP.isCoalescable(MI) &&
1521
!RegistersDefinedFromSameValue(*LIS, *TRI, CP, VNI, lr, DupCopies))
1524
RHSValsDefinedFromLHS[VNI] = lr->valno;
1527
LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1528
RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1529
NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1531
for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1534
unsigned VN = VNI->id;
1535
if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1537
ComputeUltimateVN(VNI, NewVNInfo,
1538
LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1539
LHSValNoAssignments, RHSValNoAssignments);
1541
for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1544
unsigned VN = VNI->id;
1545
if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1547
// If this value number isn't a copy from the LHS, it's a new number.
1548
if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
1549
NewVNInfo.push_back(VNI);
1550
RHSValNoAssignments[VN] = NewVNInfo.size()-1;
1554
ComputeUltimateVN(VNI, NewVNInfo,
1555
RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1556
RHSValNoAssignments, LHSValNoAssignments);
1559
// Armed with the mappings of LHS/RHS values to ultimate values, walk the
1560
// interval lists to see if these intervals are coalescable.
1561
LiveInterval::const_iterator I = LHS.begin();
1562
LiveInterval::const_iterator IE = LHS.end();
1563
LiveInterval::const_iterator J = RHS.begin();
1564
LiveInterval::const_iterator JE = RHS.end();
1566
// Skip ahead until the first place of potential sharing.
1567
if (I != IE && J != JE) {
1568
if (I->start < J->start) {
1569
I = std::upper_bound(I, IE, J->start);
1570
if (I != LHS.begin()) --I;
1571
} else if (J->start < I->start) {
1572
J = std::upper_bound(J, JE, I->start);
1573
if (J != RHS.begin()) --J;
1577
while (I != IE && J != JE) {
1578
// Determine if these two live ranges overlap.
1580
if (I->start < J->start) {
1581
Overlaps = I->end > J->start;
1583
Overlaps = J->end > I->start;
1586
// If so, check value # info to determine if they are really different.
1588
// If the live range overlap will map to the same value number in the
1589
// result liverange, we can still coalesce them. If not, we can't.
1590
if (LHSValNoAssignments[I->valno->id] !=
1591
RHSValNoAssignments[J->valno->id])
1595
if (I->end < J->end)
1601
// Update kill info. Some live ranges are extended due to copy coalescing.
1602
for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
1603
E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
1604
VNInfo *VNI = I->first;
1605
unsigned LHSValID = LHSValNoAssignments[VNI->id];
1606
if (VNI->hasPHIKill())
1607
NewVNInfo[LHSValID]->setHasPHIKill(true);
1610
// Update kill info. Some live ranges are extended due to copy coalescing.
1611
for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
1612
E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
1613
VNInfo *VNI = I->first;
1614
unsigned RHSValID = RHSValNoAssignments[VNI->id];
1615
if (VNI->hasPHIKill())
1616
NewVNInfo[RHSValID]->setHasPHIKill(true);
1619
if (LHSValNoAssignments.empty())
1620
LHSValNoAssignments.push_back(-1);
1621
if (RHSValNoAssignments.empty())
1622
RHSValNoAssignments.push_back(-1);
1624
SmallVector<unsigned, 8> SourceRegisters;
1625
for (SmallVector<MachineInstr*, 8>::iterator I = DupCopies.begin(),
1626
E = DupCopies.end(); I != E; ++I) {
1627
MachineInstr *MI = *I;
1629
// We have pretended that the assignment to B in
1632
// was actually a copy from A. Now that we decided to coalesce A and B,
1633
// transform the code into
1636
// and mark the X as coalesced to keep the illusion.
1637
unsigned Src = MI->getOperand(1).getReg();
1638
SourceRegisters.push_back(Src);
1639
MI->getOperand(0).substVirtReg(Src, 0, *TRI);
1644
// If B = X was the last use of X in a liverange, we have to shrink it now
1645
// that B = X is gone.
1646
for (SmallVector<unsigned, 8>::iterator I = SourceRegisters.begin(),
1647
E = SourceRegisters.end(); I != E; ++I) {
1648
LIS->shrinkToUses(&LIS->getInterval(*I));
1651
// If we get here, we know that we can coalesce the live ranges. Ask the
1652
// intervals to coalesce themselves now.
1653
LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
1659
// DepthMBBCompare - Comparison predicate that sort first based on the loop
1660
// depth of the basic block (the unsigned), and then on the MBB number.
1661
struct DepthMBBCompare {
1662
typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1663
bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1664
// Deeper loops first
1665
if (LHS.first != RHS.first)
1666
return LHS.first > RHS.first;
1668
// Prefer blocks that are more connected in the CFG. This takes care of
1669
// the most difficult copies first while intervals are short.
1670
unsigned cl = LHS.second->pred_size() + LHS.second->succ_size();
1671
unsigned cr = RHS.second->pred_size() + RHS.second->succ_size();
1675
// As a last resort, sort by block number.
1676
return LHS.second->getNumber() < RHS.second->getNumber();
1681
void RegisterCoalescer::CopyCoalesceInMBB(MachineBasicBlock *MBB,
1682
std::vector<MachineInstr*> &TryAgain) {
1683
DEBUG(dbgs() << MBB->getName() << ":\n");
1685
SmallVector<MachineInstr*, 8> VirtCopies;
1686
SmallVector<MachineInstr*, 8> PhysCopies;
1687
SmallVector<MachineInstr*, 8> ImpDefCopies;
1688
for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1690
MachineInstr *Inst = MII++;
1692
// If this isn't a copy nor a extract_subreg, we can't join intervals.
1693
unsigned SrcReg, DstReg;
1694
if (Inst->isCopy()) {
1695
DstReg = Inst->getOperand(0).getReg();
1696
SrcReg = Inst->getOperand(1).getReg();
1697
} else if (Inst->isSubregToReg()) {
1698
DstReg = Inst->getOperand(0).getReg();
1699
SrcReg = Inst->getOperand(2).getReg();
1703
bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1704
bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1705
if (LIS->hasInterval(SrcReg) && LIS->getInterval(SrcReg).empty())
1706
ImpDefCopies.push_back(Inst);
1707
else if (SrcIsPhys || DstIsPhys)
1708
PhysCopies.push_back(Inst);
1710
VirtCopies.push_back(Inst);
1713
// Try coalescing implicit copies and insert_subreg <undef> first,
1714
// followed by copies to / from physical registers, then finally copies
1715
// from virtual registers to virtual registers.
1716
for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
1717
MachineInstr *TheCopy = ImpDefCopies[i];
1719
if (!JoinCopy(TheCopy, Again))
1721
TryAgain.push_back(TheCopy);
1723
for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
1724
MachineInstr *TheCopy = PhysCopies[i];
1726
if (!JoinCopy(TheCopy, Again))
1728
TryAgain.push_back(TheCopy);
1730
for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
1731
MachineInstr *TheCopy = VirtCopies[i];
1733
if (!JoinCopy(TheCopy, Again))
1735
TryAgain.push_back(TheCopy);
1739
void RegisterCoalescer::joinIntervals() {
1740
DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
1742
std::vector<MachineInstr*> TryAgainList;
1743
if (Loops->empty()) {
1744
// If there are no loops in the function, join intervals in function order.
1745
for (MachineFunction::iterator I = MF->begin(), E = MF->end();
1747
CopyCoalesceInMBB(I, TryAgainList);
1749
// Otherwise, join intervals in inner loops before other intervals.
1750
// Unfortunately we can't just iterate over loop hierarchy here because
1751
// there may be more MBB's than BB's. Collect MBB's for sorting.
1753
// Join intervals in the function prolog first. We want to join physical
1754
// registers with virtual registers before the intervals got too long.
1755
std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1756
for (MachineFunction::iterator I = MF->begin(), E = MF->end();I != E;++I){
1757
MachineBasicBlock *MBB = I;
1758
MBBs.push_back(std::make_pair(Loops->getLoopDepth(MBB), I));
1761
// Sort by loop depth.
1762
std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1764
// Finally, join intervals in loop nest order.
1765
for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1766
CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
1769
// Joining intervals can allow other intervals to be joined. Iteratively join
1770
// until we make no progress.
1771
bool ProgressMade = true;
1772
while (ProgressMade) {
1773
ProgressMade = false;
1775
for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
1776
MachineInstr *&TheCopy = TryAgainList[i];
1781
bool Success = JoinCopy(TheCopy, Again);
1782
if (Success || !Again) {
1783
TheCopy= 0; // Mark this one as done.
1784
ProgressMade = true;
1790
void RegisterCoalescer::releaseMemory() {
1791
JoinedCopies.clear();
1792
ReMatCopies.clear();
1796
bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
1798
MRI = &fn.getRegInfo();
1799
TM = &fn.getTarget();
1800
TRI = TM->getRegisterInfo();
1801
TII = TM->getInstrInfo();
1802
LIS = &getAnalysis<LiveIntervals>();
1803
LDV = &getAnalysis<LiveDebugVariables>();
1804
AA = &getAnalysis<AliasAnalysis>();
1805
Loops = &getAnalysis<MachineLoopInfo>();
1807
DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
1808
<< "********** Function: "
1809
<< ((Value*)MF->getFunction())->getName() << '\n');
1811
if (VerifyCoalescing)
1812
MF->verify(this, "Before register coalescing");
1814
RegClassInfo.runOnMachineFunction(fn);
1816
// Join (coalesce) intervals if requested.
1817
if (EnableJoining) {
1820
dbgs() << "********** INTERVALS POST JOINING **********\n";
1821
for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end();
1823
I->second->print(dbgs(), TRI);
1829
// Perform a final pass over the instructions and compute spill weights
1830
// and remove identity moves.
1831
SmallVector<unsigned, 4> DeadDefs, InflateRegs;
1832
for (MachineFunction::iterator mbbi = MF->begin(), mbbe = MF->end();
1833
mbbi != mbbe; ++mbbi) {
1834
MachineBasicBlock* mbb = mbbi;
1835
for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
1837
MachineInstr *MI = mii;
1838
if (JoinedCopies.count(MI)) {
1839
// Delete all coalesced copies.
1840
bool DoDelete = true;
1841
assert(MI->isCopyLike() && "Unrecognized copy instruction");
1842
unsigned SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
1843
unsigned DstReg = MI->getOperand(0).getReg();
1845
// Collect candidates for register class inflation.
1846
if (TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1847
RegClassInfo.isProperSubClass(MRI->getRegClass(SrcReg)))
1848
InflateRegs.push_back(SrcReg);
1849
if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
1850
RegClassInfo.isProperSubClass(MRI->getRegClass(DstReg)))
1851
InflateRegs.push_back(DstReg);
1853
if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
1854
MI->getNumOperands() > 2)
1855
// Do not delete extract_subreg, insert_subreg of physical
1856
// registers unless the definition is dead. e.g.
1857
// %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
1858
// or else the scavenger may complain. LowerSubregs will
1859
// delete them later.
1862
if (MI->allDefsAreDead()) {
1863
if (TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1864
LIS->hasInterval(SrcReg))
1865
LIS->shrinkToUses(&LIS->getInterval(SrcReg));
1869
// We need the instruction to adjust liveness, so make it a KILL.
1870
if (MI->isSubregToReg()) {
1871
MI->RemoveOperand(3);
1872
MI->RemoveOperand(1);
1874
MI->setDesc(TII->get(TargetOpcode::KILL));
1875
mii = llvm::next(mii);
1877
LIS->RemoveMachineInstrFromMaps(MI);
1878
mii = mbbi->erase(mii);
1884
// Now check if this is a remat'ed def instruction which is now dead.
1885
if (ReMatDefs.count(MI)) {
1887
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1888
const MachineOperand &MO = MI->getOperand(i);
1891
unsigned Reg = MO.getReg();
1894
DeadDefs.push_back(Reg);
1895
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1896
// Remat may also enable register class inflation.
1897
if (RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)))
1898
InflateRegs.push_back(Reg);
1902
if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
1903
!MRI->use_nodbg_empty(Reg)) {
1909
while (!DeadDefs.empty()) {
1910
unsigned DeadDef = DeadDefs.back();
1911
DeadDefs.pop_back();
1912
RemoveDeadDef(LIS->getInterval(DeadDef), MI);
1914
LIS->RemoveMachineInstrFromMaps(mii);
1915
mii = mbbi->erase(mii);
1923
// Check for now unnecessary kill flags.
1924
if (LIS->isNotInMIMap(MI)) continue;
1925
SlotIndex DefIdx = LIS->getInstructionIndex(MI).getRegSlot();
1926
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1927
MachineOperand &MO = MI->getOperand(i);
1928
if (!MO.isReg() || !MO.isKill()) continue;
1929
unsigned reg = MO.getReg();
1930
if (!reg || !LIS->hasInterval(reg)) continue;
1931
if (!LIS->getInterval(reg).killedAt(DefIdx)) {
1932
MO.setIsKill(false);
1935
// When leaving a kill flag on a physreg, check if any subregs should
1937
if (!TargetRegisterInfo::isPhysicalRegister(reg))
1939
for (const uint16_t *SR = TRI->getSubRegisters(reg);
1940
unsigned S = *SR; ++SR)
1941
if (LIS->hasInterval(S) && LIS->getInterval(S).liveAt(DefIdx))
1942
MI->addRegisterDefined(S, TRI);
1947
// After deleting a lot of copies, register classes may be less constrained.
1948
// Removing sub-register opreands may alow GR32_ABCD -> GR32 and DPR_VFP2 ->
1950
array_pod_sort(InflateRegs.begin(), InflateRegs.end());
1951
InflateRegs.erase(std::unique(InflateRegs.begin(), InflateRegs.end()),
1953
DEBUG(dbgs() << "Trying to inflate " << InflateRegs.size() << " regs.\n");
1954
for (unsigned i = 0, e = InflateRegs.size(); i != e; ++i) {
1955
unsigned Reg = InflateRegs[i];
1956
if (MRI->reg_nodbg_empty(Reg))
1958
if (MRI->recomputeRegClass(Reg, *TM)) {
1959
DEBUG(dbgs() << PrintReg(Reg) << " inflated to "
1960
<< MRI->getRegClass(Reg)->getName() << '\n');
1967
if (VerifyCoalescing)
1968
MF->verify(this, "After register coalescing");
1972
/// print - Implement the dump method.
1973
void RegisterCoalescer::print(raw_ostream &O, const Module* m) const {
added
removed
lib/CodeGen/RegisterCoalescer.cpp
