1
; RUN: llc < %s -march=cellspu > %t1.s
2
; RUN: grep and %t1.s | count 234
3
; RUN: grep andc %t1.s | count 85
4
; RUN: grep andi %t1.s | count 37
5
; RUN: grep andhi %t1.s | count 30
6
; RUN: grep andbi %t1.s | count 4
8
; CellSPU legalization is over-sensitive to Legalize's traversal order.
11
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
14
; AND instruction generation:
15
define <4 x i32> @and_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
16
%A = and <4 x i32> %arg1, %arg2
20
define <4 x i32> @and_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
21
%A = and <4 x i32> %arg2, %arg1
25
define <8 x i16> @and_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) {
26
%A = and <8 x i16> %arg1, %arg2
30
define <8 x i16> @and_v8i16_2(<8 x i16> %arg1, <8 x i16> %arg2) {
31
%A = and <8 x i16> %arg2, %arg1
35
define <16 x i8> @and_v16i8_1(<16 x i8> %arg1, <16 x i8> %arg2) {
36
%A = and <16 x i8> %arg2, %arg1
40
define <16 x i8> @and_v16i8_2(<16 x i8> %arg1, <16 x i8> %arg2) {
41
%A = and <16 x i8> %arg1, %arg2
45
define i32 @and_i32_1(i32 %arg1, i32 %arg2) {
46
%A = and i32 %arg2, %arg1
50
define i32 @and_i32_2(i32 %arg1, i32 %arg2) {
51
%A = and i32 %arg1, %arg2
55
define i16 @and_i16_1(i16 %arg1, i16 %arg2) {
56
%A = and i16 %arg2, %arg1
60
define i16 @and_i16_2(i16 %arg1, i16 %arg2) {
61
%A = and i16 %arg1, %arg2
65
define i8 @and_i8_1(i8 %arg1, i8 %arg2) {
66
%A = and i8 %arg2, %arg1
70
define i8 @and_i8_2(i8 %arg1, i8 %arg2) {
71
%A = and i8 %arg1, %arg2
75
; ANDC instruction generation:
76
define <4 x i32> @andc_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
77
%A = xor <4 x i32> %arg2, < i32 -1, i32 -1, i32 -1, i32 -1 >
78
%B = and <4 x i32> %arg1, %A
82
define <4 x i32> @andc_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
83
%A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 >
84
%B = and <4 x i32> %arg2, %A
88
define <4 x i32> @andc_v4i32_3(<4 x i32> %arg1, <4 x i32> %arg2) {
89
%A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 >
90
%B = and <4 x i32> %A, %arg2
94
define <8 x i16> @andc_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) {
95
%A = xor <8 x i16> %arg2, < i16 -1, i16 -1, i16 -1, i16 -1,
96
i16 -1, i16 -1, i16 -1, i16 -1 >
97
%B = and <8 x i16> %arg1, %A
101
define <8 x i16> @andc_v8i16_2(<8 x i16> %arg1, <8 x i16> %arg2) {
102
%A = xor <8 x i16> %arg1, < i16 -1, i16 -1, i16 -1, i16 -1,
103
i16 -1, i16 -1, i16 -1, i16 -1 >
104
%B = and <8 x i16> %arg2, %A
108
define <16 x i8> @andc_v16i8_1(<16 x i8> %arg1, <16 x i8> %arg2) {
109
%A = xor <16 x i8> %arg1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
110
i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
111
i8 -1, i8 -1, i8 -1, i8 -1 >
112
%B = and <16 x i8> %arg2, %A
116
define <16 x i8> @andc_v16i8_2(<16 x i8> %arg1, <16 x i8> %arg2) {
117
%A = xor <16 x i8> %arg2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
118
i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
119
i8 -1, i8 -1, i8 -1, i8 -1 >
120
%B = and <16 x i8> %arg1, %A
124
define <16 x i8> @andc_v16i8_3(<16 x i8> %arg1, <16 x i8> %arg2) {
125
%A = xor <16 x i8> %arg2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
126
i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
127
i8 -1, i8 -1, i8 -1, i8 -1 >
128
%B = and <16 x i8> %A, %arg1
132
define i32 @andc_i32_1(i32 %arg1, i32 %arg2) {
133
%A = xor i32 %arg2, -1
134
%B = and i32 %A, %arg1
138
define i32 @andc_i32_2(i32 %arg1, i32 %arg2) {
139
%A = xor i32 %arg1, -1
140
%B = and i32 %A, %arg2
144
define i32 @andc_i32_3(i32 %arg1, i32 %arg2) {
145
%A = xor i32 %arg2, -1
146
%B = and i32 %arg1, %A
150
define i16 @andc_i16_1(i16 %arg1, i16 %arg2) {
151
%A = xor i16 %arg2, -1
152
%B = and i16 %A, %arg1
156
define i16 @andc_i16_2(i16 %arg1, i16 %arg2) {
157
%A = xor i16 %arg1, -1
158
%B = and i16 %A, %arg2
162
define i16 @andc_i16_3(i16 %arg1, i16 %arg2) {
163
%A = xor i16 %arg2, -1
164
%B = and i16 %arg1, %A
168
define i8 @andc_i8_1(i8 %arg1, i8 %arg2) {
169
%A = xor i8 %arg2, -1
170
%B = and i8 %A, %arg1
174
define i8 @andc_i8_2(i8 %arg1, i8 %arg2) {
175
%A = xor i8 %arg1, -1
176
%B = and i8 %A, %arg2
180
define i8 @andc_i8_3(i8 %arg1, i8 %arg2) {
181
%A = xor i8 %arg2, -1
182
%B = and i8 %arg1, %A
186
; ANDI instruction generation (i32 data type):
187
define <4 x i32> @andi_v4i32_1(<4 x i32> %in) {
188
%tmp2 = and <4 x i32> %in, < i32 511, i32 511, i32 511, i32 511 >
192
define <4 x i32> @andi_v4i32_2(<4 x i32> %in) {
193
%tmp2 = and <4 x i32> %in, < i32 510, i32 510, i32 510, i32 510 >
197
define <4 x i32> @andi_v4i32_3(<4 x i32> %in) {
198
%tmp2 = and <4 x i32> %in, < i32 -1, i32 -1, i32 -1, i32 -1 >
202
define <4 x i32> @andi_v4i32_4(<4 x i32> %in) {
203
%tmp2 = and <4 x i32> %in, < i32 -512, i32 -512, i32 -512, i32 -512 >
207
define zeroext i32 @andi_u32(i32 zeroext %in) {
208
%tmp37 = and i32 %in, 37
212
define signext i32 @andi_i32(i32 signext %in) {
213
%tmp38 = and i32 %in, 37
217
define i32 @andi_i32_1(i32 %in) {
218
%tmp37 = and i32 %in, 37
222
; ANDHI instruction generation (i16 data type):
223
define <8 x i16> @andhi_v8i16_1(<8 x i16> %in) {
224
%tmp2 = and <8 x i16> %in, < i16 511, i16 511, i16 511, i16 511,
225
i16 511, i16 511, i16 511, i16 511 >
229
define <8 x i16> @andhi_v8i16_2(<8 x i16> %in) {
230
%tmp2 = and <8 x i16> %in, < i16 510, i16 510, i16 510, i16 510,
231
i16 510, i16 510, i16 510, i16 510 >
235
define <8 x i16> @andhi_v8i16_3(<8 x i16> %in) {
236
%tmp2 = and <8 x i16> %in, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1,
237
i16 -1, i16 -1, i16 -1 >
241
define <8 x i16> @andhi_v8i16_4(<8 x i16> %in) {
242
%tmp2 = and <8 x i16> %in, < i16 -512, i16 -512, i16 -512, i16 -512,
243
i16 -512, i16 -512, i16 -512, i16 -512 >
247
define zeroext i16 @andhi_u16(i16 zeroext %in) {
248
%tmp37 = and i16 %in, 37 ; <i16> [#uses=1]
252
define signext i16 @andhi_i16(i16 signext %in) {
253
%tmp38 = and i16 %in, 37 ; <i16> [#uses=1]
257
; i8 data type (s/b ANDBI if 8-bit registers were supported):
258
define <16 x i8> @and_v16i8(<16 x i8> %in) {
259
; ANDBI generated for vector types
260
%tmp2 = and <16 x i8> %in, < i8 42, i8 42, i8 42, i8 42, i8 42, i8 42,
261
i8 42, i8 42, i8 42, i8 42, i8 42, i8 42,
262
i8 42, i8 42, i8 42, i8 42 >
266
define zeroext i8 @and_u8(i8 zeroext %in) {
268
%tmp37 = and i8 %in, 37
272
define signext i8 @and_sext8(i8 signext %in) {
274
%tmp38 = and i8 %in, 37
278
define i8 @and_i8(i8 %in) {
280
%tmp38 = and i8 %in, 205