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/*====================================================================
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* Project: Board Support Package (BSP)
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* Function: Standard definitions for ATMEL ARM7TDMI controller
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* Copyright HighTec EDV-Systeme GmbH 1982-2006
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*====================================================================*/
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#ifndef __AT91SAM7A3_H__
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#define __AT91SAM7A3_H__
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/* general register definition macro */
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#define __REG32(x) ((volatile unsigned int *)(x))
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#define __REG16(x) ((volatile unsigned short *)(x))
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#define __REG8(x) ((volatile unsigned char *)(x))
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/*-------------------------------------*/
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/* Peripheral and Interrupt Identifier */
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/*-------------------------------------*/
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#define FIQ_ID 0 /* Fast Interrupt */
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#define SYS_ID 1 /* System Peripheral interrupt */
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#define PIOA_ID 2 /* Parallel I/O Controller A interrupt */
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#define PIOB_ID 3 /* Parallel I/O Controller B interrupt */
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#define CAN0_ID 4 /* CAN Controller 0 interrupt */
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#define CAN1_ID 5 /* CAN Controller 0 interrupt */
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#define US0_ID 6 /* USART Channel 0 interrupt */
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#define US1_ID 7 /* USART Channel 1 interrupt */
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#define US2_ID 8 /* USART Channel 2 interrupt */
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#define MCI_ID 9 /* Multimedia Card Interface interrupt */
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#define TWI_ID 10 /* Two-Wire Interface interrupt */
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#define SPI0_ID 11 /* Serial Peripheral Interface 0 interrupt */
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#define SPI1_ID 12 /* Serial Peripheral Interface 1 interrupt */
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#define SSC0_ID 13 /* Synchronous Serial Controller 0 interrupt */
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#define SSC1_ID 14 /* Synchronous Serial Controller 1 interrupt */
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#define TC0_ID 15 /* Timer Channel 0 interrupt */
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#define TC1_ID 16 /* Timer Channel 1 interrupt */
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#define TC2_ID 17 /* Timer Channel 2 interrupt */
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#define TC3_ID 18 /* Timer Channel 3 interrupt */
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#define TC4_ID 19 /* Timer Channel 4 interrupt */
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#define TC5_ID 20 /* Timer Channel 5 interrupt */
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#define TC6_ID 21 /* Timer Channel 6 interrupt */
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#define TC7_ID 22 /* Timer Channel 7 interrupt */
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#define TC8_ID 23 /* Timer Channel 8 interrupt */
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#define ADC0_ID 24 /* Analog to Digital Converter 0 interrupt */
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#define ADC1_ID 25 /* Analog to Digital Converter 1 interrupt */
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#define PWMC_ID 26 /* PWM Controller interrupt */
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#define UDP_ID 27 /* USB Device Port interrupt */
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#define IRQ0_ID 28 /* External interrupt 0 */
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#define IRQ1_ID 29 /* External interrupt 1 */
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#define IRQ2_ID 30 /* External interrupt 2 */
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#define IRQ3_ID 31 /* External interrupt 3 */
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#define ISR_VALID_MASK 0xFFFFFFF7
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#define MAXIRQNUM (ISR_MAX)
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#define MAXFIQNUM (MAXIRQNUM)
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#define NR_IRQS (MAXIRQNUM + 1)
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/*---------------------------------------*/
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/* Power Management Controller Registers */
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/*---------------------------------------*/
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#define PMC_BASE 0xFFFFFC00
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#define PMC_SCER __REG32(PMC_BASE + 0x00) /* System Clock Enable Register */
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#define PMC_SCDR __REG32(PMC_BASE + 0x04) /* System Clock Disable Register */
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#define PMC_SCSR __REG32(PMC_BASE + 0x08) /* System Clock Status Register */
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#define PMC_PCER __REG32(PMC_BASE + 0x10) /* Peripheral Clock Enable Register */
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#define PMC_PCDR __REG32(PMC_BASE + 0x14) /* Peripheral Clock Disable Register */
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#define PMC_PCSR __REG32(PMC_BASE + 0x18) /* Peripheral Clock Status Register */
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#define PMC_MOR __REG32(PMC_BASE + 0x20) /* Main Oscillator Register */
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#define PMC_MCFR __REG32(PMC_BASE + 0x24) /* Main Clock Frequency Register */
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#define PMC_PLLR __REG32(PMC_BASE + 0x2C) /* PLL Register */
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#define PMC_MCKR __REG32(PMC_BASE + 0x30) /* Master Clock Register */
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#define PMC_PCKR0 __REG32(PMC_BASE + 0x40) /* Programmable Clock Register 0 */
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#define PMC_PCKR1 __REG32(PMC_BASE + 0x44) /* Programmable Clock Register 1 */
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#define PMC_PCKR2 __REG32(PMC_BASE + 0x48) /* Programmable Clock Register 2 */
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#define PMC_IER __REG32(PMC_BASE + 0x60) /* Interrupt Enable Register */
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#define PMC_IDR __REG32(PMC_BASE + 0x64) /* Interrupt Disable Register */
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#define PMC_SR __REG32(PMC_BASE + 0x68) /* Status Register */
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#define PMC_IMR __REG32(PMC_BASE + 0x6C) /* Interrupt Mask Register */
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/* bits in System Clock Registers (PMC_SCER, PMC_SCDR, PMC_SCSR) */
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#define PMC_SCR_PCK (1 << 0) /* Processor Clock */
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#define PMC_SCR_UDP (1 << 7) /* USB Device Port Clock */
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#define PMC_SCR_PCK0 (1 << 8) /* Programmable Clock Output 0 */
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#define PMC_SCR_PCK1 (1 << 9) /* Programmable Clock Output 1 */
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#define PMC_SCR_PCK2 (1 << 10) /* Programmable Clock Output 2 */
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/* bits in PMC_MCKR: Master Clock Register */
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#define PMC_MCKR_CSS (0x03 << 0) /* Programmable Clock Selection */
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#define PMC_MCKR_CSS_SLOW (0x00 << 0) /* Slow Clock is selected */
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#define PMC_MCKR_CSS_MAIN (0x01 << 0) /* Main Clock is selected */
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#define PMC_MCKR_CSS_PLL (0x03 << 0) /* Clock from PLL is selected */
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#define PMC_MCKR_PRES (0x07 << 2) /* Programmable Clock Prescaler */
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#define PMC_MCKR_PRES_NONE (0x00 << 2) /* Selected Clock */
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#define PMC_MCKR_PRES_DIV2 (0x01 << 2) /* Selected Clock divided by 2 */
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#define PMC_MCKR_PRES_DIV4 (0x02 << 2) /* Selected Clock divided by 4 */
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#define PMC_MCKR_PRES_DIV8 (0x03 << 2) /* Selected Clock divided by 8 */
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#define PMC_MCKR_PRES_DIV16 (0x04 << 2) /* Selected Clock divided by 16 */
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#define PMC_MCKR_PRES_DIV32 (0x05 << 2) /* Selected Clock divided by 32 */
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#define PMC_MCKR_PRES_DIV64 (0x06 << 2) /* Selected Clock divided by 64 */
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/* bits in PMC_PCKx: Programmable Clock Register */
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#define PMC_PCK_CSS (0x03 << 0) /* Programmable Clock Selection */
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#define PMC_PCK_CSS_SLOW (0x00 << 0) /* Slow Clock is selected */
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#define PMC_PCK_CSS_MAIN (0x01 << 0) /* Main Clock is selected */
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#define PMC_PCK_CSS_PLL (0x03 << 0) /* Clock from PLL is selected */
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#define PMC_PCK_PRES (0x07 << 2) /* Programmable Clock Prescaler */
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#define PMC_PCK_PRES_SHFT 2
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#define PMC_PCK_PRES_NONE (0x00 << 2) /* Selected Clock */
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#define PMC_PCK_PRES_DIV2 (0x01 << 2) /* Selected Clock divided by 2 */
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#define PMC_PCK_PRES_DIV4 (0x02 << 2) /* Selected Clock divided by 4 */
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#define PMC_PCK_PRES_DIV8 (0x03 << 2) /* Selected Clock divided by 8 */
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#define PMC_PCK_PRES_DIV16 (0x04 << 2) /* Selected Clock divided by 16 */
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#define PMC_PCK_PRES_DIV32 (0x05 << 2) /* Selected Clock divided by 32 */
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#define PMC_PCK_PRES_DIV64 (0x06 << 2) /* Selected Clock divided by 64 */
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/* bits in PMC_IER, PMC_IDR, PMC_SR, PMC_IMR */
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#define PMC_CK_MOSC (1 << 0) /* MOSC Status */
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#define PMC_CK_LOCK (1 << 2) /* PLL Status */
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#define PMC_CK_MCKRDY (1 << 3) /* MCK_RDY Status */
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#define PMC_CK_PCK0RDY (1 << 8) /* PCK0_RDY Status */
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#define PMC_CK_PCK1RDY (1 << 9) /* PCK1_RDY Status */
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#define PMC_CK_PCK2RDY (1 << 10) /* PCK2_RDY Status */
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/*--------------------------------------*/
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/* Clock Generator Controller Registers */
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/*--------------------------------------*/
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#define CKGR_BASE (PMC_BASE + 0x20)
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#define CKGR_MOR __REG32(CKGR_BASE + 0x00) /* Main Oscillator Register */
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#define CKGR_MCFR __REG32(CKGR_BASE + 0x04) /* Main Clock Frequency Register */
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#define CKGR_PLLR __REG32(CKGR_BASE + 0x0C) /* PLL Register */
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/* CKGR_MOR: Main Oscillator Register */
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#define CKGR_MOR_MOSCEN (1 << 0) /* Main Oscillator Enable */
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#define CKGR_MOR_OSCBYPASS (1 << 1) /* Main Oscillator Bypass */
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#define CKGR_MOR_OSCCOUNT (0xFF << 8) /* Main Oscillator Start-up Time */
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/* CKGR_MCFR: Main Clock Frequency Register */
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#define CKGR_MCFR_MAINF (0xFFFF << 0) /* Main Clock Frequency */
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#define CKGR_MCFR_MAINRDY (1 << 16) /* Main Clock Ready */
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/* CKGR_PLLR: PLL Register */
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#define CKGR_PLLR_DIV (0xFF << 0) /* Divider Selected */
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#define CKGR_PLLR_DIV_0 (0x00) /* Divider output is 0 */
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#define CKGR_PLLR_DIV_BYPASS (0x01) /* Divider is bypassed */
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#define CKGR_PLLR_PLLCOUNT (0x3F << 8) /* PLL Counter */
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#define CKGR_PLLR_OUT (0x03 << 14) /* PLL Output Frequency Range */
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#define CKGR_PLLR_MUL (0x7FF << 16) /* PLL Multiplier */
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#define CKGR_PLLR_USBDIV (0x03 << 28) /* Divider for USB Clocks */
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#define CKGR_PLLR_USBDIV_0 (0x01 << 28) /* USB Clock == PLL */
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#define CKGR_PLLR_USBDIV_2 (0x01 << 28) /* USB Clock == PLL / 2 */
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#define CKGR_PLLR_USBDIV_4 (0x02 << 28) /* USB Clock == PLL / 4 */
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/*----------------------------*/
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/* Reset Controller Interface */
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/*----------------------------*/
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#define RSTC_BASE 0xFFFFFD00
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#define RSTC_CR __REG32(RSTC_BASE + 0x00) /* Control Register */
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#define RSTC_SR __REG32(RSTC_BASE + 0x04) /* Status Register */
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#define RSTC_MR __REG32(RSTC_BASE + 0x08) /* Mode Register */
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/* RSTC_CR: Reset Controller Control Register */
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#define RSTC_CR_PROCRST (1 << 0) /* Processor Reset */
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#define RSTC_CR_PERRST (1 << 2) /* Peripheral Reset */
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#define RSTC_CR_EXTRST (1 << 3) /* External Reset */
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#define RSTC_CR_KEY (0xFFu << 24) /* Password */
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/* RSTC_SR: Reset Controller Status Register */
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#define RSTC_SR_URSTS (1 << 0) /* User Reset Status */
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#define RSTC_SR_BODSTS (1 << 1) /* Brownout Reset Status */
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#define RSTC_SR_RSTTYP (0x07 << 8) /* Reset Type */
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#define RSTC_SR_RSTTYP_POWERUP (0 << 8) /* Power-up Reset */
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#define RSTC_SR_RSTTYP_WAKEUP (1 << 8) /* WakeUp Reset */
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#define RSTC_SR_RSTTYP_WATCHDOG (2 << 8) /* Watchdog Reset */
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#define RSTC_SR_RSTTYP_SOFTWARE (3 << 8) /* Software Reset */
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#define RSTC_SR_RSTTYP_USER (4 << 8) /* User Reset */
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#define RSTC_SR_RSTTYP_BROWNOUT (5 << 8) /* Brownout Reset */
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#define RSTC_SR_NRSTL (1 << 16) /* NRST pin level */
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#define RSTC_SR_SRCMP (1 << 17) /* Software Reset Command in Progress */
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/* RSTC_MR: Reset Controller Mode Register */
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#define RSTC_MR_URSTEN (0x01 << 0) /* User Reset Enable */
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#define RSTC_MR_URSTIEN (0x01 << 4) /* User Reset Interrupt Enable */
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#define RSTC_MR_ERSTL (0x0F << 8) /* User Reset Length */
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#define RSTC_MR_BODIEN (0x01 << 16) /* Brownout Detection Interrupt */
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/*---------------------*/
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/* Shutdown Controller */
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/*---------------------*/
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#define SHDC_BASE 0xFFFFFD10
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#define SHDC_CR __REG32(SHDC_BASE + 0x00) /* Control Register */
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#define SHDC_MR __REG32(SHDC_BASE + 0x04) /* Mode Register */
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#define SHDC_SR __REG32(SHDC_BASE + 0x08) /* Status Register */
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/* SHDC_CR: Shutdown Controller Control Register */
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#define SHDC_CR_SHDW (1 << 0) /* Shut Down Command */
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#define SHDC_CR_KEY (0xFFu << 24) /* Shutdown Password */
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/* SHDC_MR: Shutdown Controller Mode Register */
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#define SHDC_MR_WKMODE0 (0x03 << 0) /* Wake-up 0 Input Transition Selection */
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#define SHDC_MR_WKMODE0_NO (0x00 << 0) /* No detection is performed */
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#define SHDC_MR_WKMODE0_LH (0x01 << 0) /* Low to high level */
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#define SHDC_MR_WKMODE0_HL (0x02 << 0) /* High to low level */
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#define SHDC_MR_WKMODE0_BL (0x03 << 0) /* Both levels change */
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#define SHDC_MR_CPTWK0 (0x0F << 4) /* Counter on Wake-up 0 */
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#define SHDC_MR_WKMODE1 (0x03 << 8) /* Wake-up 1 Input Transition Selection */
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#define SHDC_MR_WKMODE1_NO (0x00 << 8) /* No detection is performed */
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#define SHDC_MR_WKMODE1_LH (0x01 << 8) /* Low to high level */
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#define SHDC_MR_WKMODE1_HL (0x02 << 8) /* High to low level */
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#define SHDC_MR_WKMODE1_BL (0x03 << 8) /* Both levels change */
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#define SHDC_MR_CPTWK1 (0x0F << 12) /* Counter on Wake-up 1 */
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#define SHDC_MR_RTTWKEN (1 << 16) /* Real-time Timer Wake-up Enable */
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/* SHDC_SR: Shutdown Controller Status Register */
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#define SHDC_SR_WAKEUP0 (1 << 0) /* Wake-up 0 Status */
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#define SHDC_SR_WAKEUP1 (1 << 1) /* Wake-up 1 Status */
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#define SHDC_SR_FWKUP (1 << 2) /* Force Wake-Up Status */
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#define SHDC_SR_RTTWK (1 << 16) /* Real-time Timer Wake-up Status */
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/*-----------------*/
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/* Real-time Timer */
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/*-----------------*/
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#define RTT_BASE 0xFFFFFD20
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#define RTT_MR __REG32(RTT_BASE + 0x00) /* Real-time Timer Mode Register */
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#define RTT_AR __REG32(RTT_BASE + 0x04) /* Real-time Timer Alarm Register */
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#define RTT_VR __REG32(RTT_BASE + 0x08) /* Real-time Timer Value Register */
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#define RTT_SR __REG32(RTT_BASE + 0x0C) /* Real-time Timer Status Register */
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/* RTT_MR: Real-time Timer Mode Register */
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#define RTT_MR_RTPRES (0xFFFF << 0) /* Real Time Timer Prescaler Value */
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#define RTT_MR_ALMIEN (1 << 16) /* Alarm Interrupt Enable */
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#define RTT_MR_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */
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#define RTT_MR_RTTRST (1 << 18) /* Real Time Timer Restart */
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/* RTT_AR: Real-time Timer Alarm Register */
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#define RTT_AR_ALMV (0x0 << 0) /* Alarm Value */
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/* RTT_VR: Real-time Timer Value Register */
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#define RTT_VR_CRTV (0x0 << 0) /* Current Real Time Value */
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/* RTT_SR: Real-time Timer Status Register */
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#define RTT_SR_ALMS (1 << 0) /* Alarm Status */
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#define RTT_SR_RTTINC (1 << 1) /* Real Time Timer Increment */
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/*-------------------------*/
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/* Periodic Interval Timer */
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/*-------------------------*/
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#define PIT_BASE 0xFFFFFD30
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#define PIT_MR __REG32(PIT_BASE + 0x00) /* Period Interval Mode Register */
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#define PIT_SR __REG32(PIT_BASE + 0x04) /* Period Interval Status Register */
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#define PIT_PIVR __REG32(PIT_BASE + 0x08) /* Period Interval Value Register */
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#define PIT_PIIR __REG32(PIT_BASE + 0x0C) /* Period Interval Image Register */
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/* PIT_MR: Periodic Interval Timer Mode Register */
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#define PIT_MR_PIV (0xFFFFF << 0) /* Periodic Interval Value */
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#define PIT_MR_PITEN (1 << 24) /* Periodic Interval Timer Enabled */
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#define PIT_MR_PITIEN (1 << 25) /* Periodic Interval Timer Interrupt Enabled */
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/* PIT_SR: Periodic Interval Timer Status Register */
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#define PIT_SR_PITS (1 << 0) /* Periodic Interval Timer Status */
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/* PIT_PIVR: Periodic Interval Timer Value Register */
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#define PIT_PIVR_CPIV (0xFFFFF << 0) /* Current Periodic Interval Value */
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#define PIT_PIVR_PICNT (0xFFFu << 20) /* Periodic Interval Counter */
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#define WDT_BASE 0xFFFFFD40
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#define WDT_CR __REG32(WDT_BASE + 0x00) /* Watchdog Control Register */
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#define WDT_MR __REG32(WDT_BASE + 0x04) /* Watchdog Mode Register */
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#define WDT_SR __REG32(WDT_BASE + 0x08) /* Watchdog Status Register */
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/* WDT_CR: Watchdog Timer Control Register */
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#define WDT_CR_WDRSTT (1 << 0) /* Watchdog Restart */
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#define WDT_CR_KEY (0xFFu << 24) /* Watchdog KEY Password */
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/* WDT_MR: Watchdog Timer Mode Register */
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#define WDT_MR_WDV (0xFFF << 0) /* Watchdog Counter Value */
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#define WDT_MR_WDFIEN (1 << 12) /* Watchdog Fault Interrupt Enable */
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#define WDT_MR_WDRSTEN (1 << 13) /* Watchdog Reset Enable */
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#define WDT_MR_WDRPROC (1 << 14) /* Watchdog Reset Processor */
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#define WDT_MR_WDDIS (1 << 15) /* Watchdog Disable */
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#define WDT_MR_WDD (0xFFF << 16) /* Watchdog Delta Value */
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#define WDT_MR_WDDBGHLT (1 << 28) /* Watchdog Debug Halt */
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#define WDT_MR_WDIDLEHLT (1 << 29) /* Watchdog Idle Halt */
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/* WDT_SR: Watchdog Timer Status Register */
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#define WDT_SR_WDUNF (1 << 0) /* Watchdog Underflow */
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#define WDT_SR_WDERR (1 << 1) /* Watchdog Error */
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/*---------------------------------------------*/
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/* Voltage Regulator Mode Controller Registers */
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/*---------------------------------------------*/
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#define VREG_BASE 0xFFFFFD60
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#define VREG_MR __REG32(VREG_BASE + 0x00) /* Voltage Regulator Mode Register */
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#define VREG_MR_PSTDBY (1 << 0) /* Voltage Regulator Power Standby Mode */
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/*-----------------------------------------*/
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/* Advanced Interrupt Controller Registers */
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/*-----------------------------------------*/
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#define AIC_BASE 0xFFFFF000
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/* Source Mode Register */
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#define AIC_SMR0 __REG32(AIC_BASE + 0x000)
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#define AIC_SMR1 __REG32(AIC_BASE + 0x004)
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#define AIC_SMR2 __REG32(AIC_BASE + 0x008)
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#define AIC_SMR3 __REG32(AIC_BASE + 0x00C)
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#define AIC_SMR4 __REG32(AIC_BASE + 0x010)
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#define AIC_SMR5 __REG32(AIC_BASE + 0x014)
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#define AIC_SMR6 __REG32(AIC_BASE + 0x018)
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#define AIC_SMR7 __REG32(AIC_BASE + 0x01C)
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#define AIC_SMR8 __REG32(AIC_BASE + 0x020)
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#define AIC_SMR9 __REG32(AIC_BASE + 0x024)
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#define AIC_SMR10 __REG32(AIC_BASE + 0x028)
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#define AIC_SMR11 __REG32(AIC_BASE + 0x02C)
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#define AIC_SMR12 __REG32(AIC_BASE + 0x030)
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#define AIC_SMR13 __REG32(AIC_BASE + 0x034)
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#define AIC_SMR14 __REG32(AIC_BASE + 0x038)
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#define AIC_SMR15 __REG32(AIC_BASE + 0x03C)
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#define AIC_SMR16 __REG32(AIC_BASE + 0x040)
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#define AIC_SMR17 __REG32(AIC_BASE + 0x044)
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#define AIC_SMR18 __REG32(AIC_BASE + 0x048)
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#define AIC_SMR19 __REG32(AIC_BASE + 0x04C)
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#define AIC_SMR20 __REG32(AIC_BASE + 0x050)
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#define AIC_SMR21 __REG32(AIC_BASE + 0x054)
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#define AIC_SMR22 __REG32(AIC_BASE + 0x058)
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#define AIC_SMR23 __REG32(AIC_BASE + 0x05C)
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#define AIC_SMR24 __REG32(AIC_BASE + 0x060)
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#define AIC_SMR25 __REG32(AIC_BASE + 0x064)
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#define AIC_SMR26 __REG32(AIC_BASE + 0x068)
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#define AIC_SMR27 __REG32(AIC_BASE + 0x06C)
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#define AIC_SMR28 __REG32(AIC_BASE + 0x070)
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#define AIC_SMR29 __REG32(AIC_BASE + 0x074)
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#define AIC_SMR30 __REG32(AIC_BASE + 0x078)
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#define AIC_SMR31 __REG32(AIC_BASE + 0x07C)
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/* Source Vector Register */
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#define AIC_SVR0 __REG32(AIC_BASE + 0x080)
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#define AIC_SVR1 __REG32(AIC_BASE + 0x084)
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#define AIC_SVR2 __REG32(AIC_BASE + 0x088)
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#define AIC_SVR3 __REG32(AIC_BASE + 0x08C)
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#define AIC_SVR4 __REG32(AIC_BASE + 0x090)
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#define AIC_SVR5 __REG32(AIC_BASE + 0x094)
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#define AIC_SVR6 __REG32(AIC_BASE + 0x098)
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#define AIC_SVR7 __REG32(AIC_BASE + 0x09C)
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#define AIC_SVR8 __REG32(AIC_BASE + 0x0A0)
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#define AIC_SVR9 __REG32(AIC_BASE + 0x0A4)
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#define AIC_SVR10 __REG32(AIC_BASE + 0x0A8)
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#define AIC_SVR11 __REG32(AIC_BASE + 0x0AC)
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#define AIC_SVR12 __REG32(AIC_BASE + 0x0B0)
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#define AIC_SVR13 __REG32(AIC_BASE + 0x0B4)
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#define AIC_SVR14 __REG32(AIC_BASE + 0x0B8)
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#define AIC_SVR15 __REG32(AIC_BASE + 0x0BC)
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#define AIC_SVR16 __REG32(AIC_BASE + 0x0C0)
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#define AIC_SVR17 __REG32(AIC_BASE + 0x0C4)
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#define AIC_SVR18 __REG32(AIC_BASE + 0x0C8)
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#define AIC_SVR19 __REG32(AIC_BASE + 0x0CC)
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#define AIC_SVR20 __REG32(AIC_BASE + 0x0D0)
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#define AIC_SVR21 __REG32(AIC_BASE + 0x0D4)
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#define AIC_SVR22 __REG32(AIC_BASE + 0x0D8)
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#define AIC_SVR23 __REG32(AIC_BASE + 0x0DC)
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#define AIC_SVR24 __REG32(AIC_BASE + 0x0E0)
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#define AIC_SVR25 __REG32(AIC_BASE + 0x0E4)
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#define AIC_SVR26 __REG32(AIC_BASE + 0x0E8)
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#define AIC_SVR27 __REG32(AIC_BASE + 0x0EC)
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#define AIC_SVR28 __REG32(AIC_BASE + 0x0F0)
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#define AIC_SVR29 __REG32(AIC_BASE + 0x0F4)
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#define AIC_SVR30 __REG32(AIC_BASE + 0x0F8)
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#define AIC_SVR31 __REG32(AIC_BASE + 0x0FC)
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#define AIC_IVR __REG32(AIC_BASE + 0x100) /* IRQ Vector Register */
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#define AIC_FVR __REG32(AIC_BASE + 0x104) /* FIQ Vector Register */
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#define AIC_ISR __REG32(AIC_BASE + 0x108) /* Interrupt Status Register */
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#define AIC_IPR __REG32(AIC_BASE + 0x10C) /* Interrupt Pending Register */
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#define AIC_IMR __REG32(AIC_BASE + 0x110) /* Interrupt Mask Register */
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#define AIC_CISR __REG32(AIC_BASE + 0x114) /* Core Interrupt Status Register */
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#define AIC_IECR __REG32(AIC_BASE + 0x120) /* Interrupt Enable Command Register */
397
#define AIC_IDCR __REG32(AIC_BASE + 0x124) /* Interrupt Disable Command Register */
398
#define AIC_ICCR __REG32(AIC_BASE + 0x128) /* Interrupt Clear Command Register */
399
#define AIC_ISCR __REG32(AIC_BASE + 0x12C) /* Interrupt Set Command Register */
400
#define AIC_EOICR __REG32(AIC_BASE + 0x130) /* End of Interrupt Command Register */
401
#define AIC_SPU __REG32(AIC_BASE + 0x134) /* Spurious Vector Register */
402
#define AIC_DCR __REG32(AIC_BASE + 0x138) /* Debug Control Register (Protect) */
403
#define AIC_FFER __REG32(AIC_BASE + 0x140) /* Fast Forcing Enable Register */
404
#define AIC_FFDR __REG32(AIC_BASE + 0x144) /* Fast Forcing Disable Register */
405
#define AIC_FFSR __REG32(AIC_BASE + 0x148) /* Fast Forcing Status Register */
407
/* AIC_SMR[]: Interrupt Source Mode Registers */
408
#define AIC_PRIOR 0x07 /* Priority */
409
#define AIC_PRIOR_LOWEST 0 /* lowest priority level */
410
#define AIC_PRIOR_HIGHEST 7 /* highest priority level */
412
#define AIC_SRCTYPE 0x60 /* Source Type Definition */
414
/* Internal Interrupts */
415
#define AIC_SRCTYPE_INT_LEVEL_SENSITIVE 0x00 /* Level Sensitive */
416
#define AIC_SRCTYPE_INT_EDGE_TRIGGERED 0x20 /* Edge Triggered */
418
/* External Interrupts */
419
#define AIC_SRCTYPE_EXT_LOW_LEVEL 0x00 /* Low Level */
420
#define AIC_SRCTYPE_EXT_NEGATIVE_EDGE 0x20 /* Negative Edge */
421
#define AIC_SRCTYPE_EXT_HIGH_LEVEL 0x40 /* High Level */
422
#define AIC_SRCTYPE_EXT_POSITIVE_EDGE 0x60 /* Positive Edge */
424
/* AIC_ISR: Interrupt Status Register */
425
#define AIC_IRQID 0x1F /* Current source interrupt */
427
/* AIC_CISR: Interrupt Core Status Register */
428
#define AIC_NFIQ 0x01 /* Core FIQ Status */
429
#define AIC_NIRQ 0x02 /* Core IRQ Status */
431
/* AIC_DCR: Debug Control Register (Protect) */
432
#define AIC_DCR_PROT 0x01 /* Protection Mode */
433
#define AIC_DCR_GMSK 0x02 /* General Mask */
436
/*-----------------------------*/
437
/* Memory Controller Interface */
438
/*-----------------------------*/
439
#define MC_BASE 0xFFFFFF00
440
#define MC_RCR __REG32(MC_BASE + 0x00) /* Remap Control Register */
441
#define MC_ASR __REG32(MC_BASE + 0x04) /* Abort Status Register */
442
#define MC_AASR __REG32(MC_BASE + 0x08) /* Abort Address Status Register */
443
#define MC_PUIA0 __REG32(MC_BASE + 0x10) /* MC Protection Unit Area 0 */
444
#define MC_PUIA1 __REG32(MC_BASE + 0x14) /* MC Protection Unit Area 1 */
445
#define MC_PUIA2 __REG32(MC_BASE + 0x18) /* MC Protection Unit Area 2 */
446
#define MC_PUIA3 __REG32(MC_BASE + 0x1C) /* MC Protection Unit Area 3 */
447
#define MC_PUIA4 __REG32(MC_BASE + 0x20) /* MC Protection Unit Area 4 */
448
#define MC_PUIA5 __REG32(MC_BASE + 0x24) /* MC Protection Unit Area 5 */
449
#define MC_PUIA6 __REG32(MC_BASE + 0x28) /* MC Protection Unit Area 6 */
450
#define MC_PUIA7 __REG32(MC_BASE + 0x2C) /* MC Protection Unit Area 7 */
451
#define MC_PUIA8 __REG32(MC_BASE + 0x30) /* MC Protection Unit Area 8 */
452
#define MC_PUIA9 __REG32(MC_BASE + 0x34) /* MC Protection Unit Area 9 */
453
#define MC_PUIA10 __REG32(MC_BASE + 0x38) /* MC Protection Unit Area 10 */
454
#define MC_PUIA11 __REG32(MC_BASE + 0x3C) /* MC Protection Unit Area 11 */
455
#define MC_PUIA12 __REG32(MC_BASE + 0x40) /* MC Protection Unit Area 12 */
456
#define MC_PUIA13 __REG32(MC_BASE + 0x44) /* MC Protection Unit Area 13 */
457
#define MC_PUIA14 __REG32(MC_BASE + 0x48) /* MC Protection Unit Area 14 */
458
#define MC_PUIA15 __REG32(MC_BASE + 0x4C) /* MC Protection Unit Area 15 */
459
#define MC_PUP __REG32(MC_BASE + 0x50) /* MC Protection Unit Peripherals */
460
#define MC_PUER __REG32(MC_BASE + 0x54) /* MC Protection Unit Enable Register */
461
#define MC_FMR __REG32(MC_BASE + 0x60) /* Flash Mode Register */
462
#define MC_FCR __REG32(MC_BASE + 0x64) /* Flash Command Register */
463
#define MC_FSR __REG32(MC_BASE + 0x68) /* Flash Status Register */
465
/* MC_RCR: Remap Control Register */
466
#define MC_RCR_RCB (1 << 0) /* Remap Command Bit */
468
/* MC_ASR: Abort Status Register */
469
#define MC_ASR_UNDADD (1 << 0) /* Undefined Address */
470
#define MC_ASR_MISADD (1 << 1) /* Misaligned Address */
471
#define MC_ASR_MPU (1 << 2) /* Memory Protection Unit */
472
#define MC_ASR_ABTSZ (0x03 << 8) /* Abort Size */
473
#define MC_ASR_ABTSZ_BYTE (0 << 8) /* Byte */
474
#define MC_ASR_ABTSZ_HWORD (1 << 8) /* Half-word */
475
#define MC_ASR_ABTSZ_WORD (2 << 8) /* Word */
476
#define MC_ASR_ABTTYP (0x03 << 10) /* Abort Type */
477
#define MC_ASR_ABTTYP_DATAR (0 << 10) /* Data Read */
478
#define MC_ASR_ABTTYP_DATAW (1 << 10) /* Data Write */
479
#define MC_ASR_ABTTYP_FETCH (2 << 10) /* Code Fetch */
480
#define MC_ASR_MST0 (1 << 16) /* Master 0 Abort Source */
481
#define MC_ASR_MST1 (1 << 17) /* Master 1 Abort Source */
482
#define MC_ASR_SVMST0 (1 << 24) /* Saved Master 0 Abort Source */
483
#define MC_ASR_SVMST1 (1 << 25) /* Saved Master 1 Abort Source */
485
/* MC_PUIAx: MC Protection Unit Area Registers */
486
#define MC_PUIA_PROT_MSK (3 << 0) /* Protection mode */
487
#define MC_PUIA_SIZE_MSK (0x0F << 4) /* Internal Area Size (0 = 1kB .. 14 = 4MB) */
488
#define MC_PUIA_SIZE_SHFT 4
489
#define MC_PUIA_BA_MSK (0xFFF << 12) /* Internal Area Base Address */
490
#define MC_PUIA_BA_SHFT 12
492
/* MC_PUP: MC Protection Unit Peripheral */
493
#define MC_PUP_PROT_MSK (3 << 0) /* Protection mode */
495
/* MC_PUER: MC Protection Unit Enable Register */
496
#define MC_PUER_PUEB (1 << 0) /* Protection Unit Enable Bit */
498
/* MC_FMR: Flash Mode Register */
499
#define MC_FMR_EOP (1 << 0) /* End of Programming Interrupt Enable */
500
#define MC_FMR_EOL (1 << 1) /* End of Lock/Unlock Interrupt Enable */
501
#define MC_FMR_LOCKE (1 << 2) /* Lock Error Interrupt Enable */
502
#define MC_FMR_PROGE (1 << 3) /* Programming Error Interrupt Enable */
503
#define MC_FMR_NEBP (1 << 7) /* No Erase Before Programming */
504
#define MC_FMR_FWS (0x03 << 8) /* Flash Wait State */
505
#define MC_FMR_FWS_0FWS (0 << 8) /* 1 cycle for Read, 2 for Write operations */
506
#define MC_FMR_FWS_1FWS (1 << 8) /* 2 cycle for Read, 3 for Write operations */
507
#define MC_FMR_FWS_2FWS (2 << 8) /* 3 cycle for Read, 4 for Write operations */
508
#define MC_FMR_FWS_3FWS (3 << 8) /* 4 cycle for Read, 4 for Write operations */
509
#define MC_FMR_FMCN (0xFF << 16) /* Flash Microsecond Cycle Number */
511
/* MC_FCR: Flash Command Register */
512
#define MC_FCR_FCMD (0x0F << 0) /* Flash Command */
513
#define MC_FCR_FCMD_WP (1 << 0) /* Write Page */
514
#define MC_FCR_FCMD_SLB (2 << 0) /* Set Lock Bit */
515
#define MC_FCR_FCMD_WPL (3 << 0) /* Write Page and Lock */
516
#define MC_FCR_FCMD_CLB (4 << 0) /* Clear Lock Bit */
517
#define MC_FCR_FCMD_EA (8 << 0) /* Erase All */
518
#define MC_FCR_PAGEN (0x3FF << 8) /* Page Number */
519
#define MC_FCR_KEY (0xFFu << 24) /* Write Protection Key */
521
/* MC_FSR: Flash Status Register */
522
#define MC_FSR_EOP (1 << 0) /* End of Programming Status */
523
#define MC_FSR_EOL (1 << 1) /* End of Lock Status */
524
#define MC_FSR_LOCKE (1 << 2) /* Lock Error Status */
525
#define MC_FSR_PROGE (1 << 3) /* Programming Error Status */
526
#define MC_FSR_LOCKS0 (1 << 16) /* Sector 0 Lock Status */
527
#define MC_FSR_LOCKS1 (1 << 17) /* Sector 1 Lock Status */
528
#define MC_FSR_LOCKS2 (1 << 18) /* Sector 2 Lock Status */
529
#define MC_FSR_LOCKS3 (1 << 19) /* Sector 3 Lock Status */
530
#define MC_FSR_LOCKS4 (1 << 20) /* Sector 4 Lock Status */
531
#define MC_FSR_LOCKS5 (1 << 21) /* Sector 5 Lock Status */
532
#define MC_FSR_LOCKS6 (1 << 22) /* Sector 6 Lock Status */
533
#define MC_FSR_LOCKS7 (1 << 23) /* Sector 7 Lock Status */
534
#define MC_FSR_LOCKS8 (1 << 24) /* Sector 8 Lock Status */
535
#define MC_FSR_LOCKS9 (1 << 25) /* Sector 9 Lock Status */
536
#define MC_FSR_LOCKS10 (1 << 26) /* Sector 10 Lock Status */
537
#define MC_FSR_LOCKS11 (1 << 27) /* Sector 11 Lock Status */
538
#define MC_FSR_LOCKS12 (1 << 28) /* Sector 12 Lock Status */
539
#define MC_FSR_LOCKS13 (1 << 29) /* Sector 13 Lock Status */
540
#define MC_FSR_LOCKS14 (1 << 30) /* Sector 14 Lock Status */
541
#define MC_FSR_LOCKS15 (1u << 31) /* Sector 15 Lock Status */
548
#define DBGU_BASE 0xFFFFF200
549
#define DBGU_CR __REG32(DBGU_BASE + 0x000) /* Control Register */
550
#define DBGU_MR __REG32(DBGU_BASE + 0x004) /* Mode Register */
551
#define DBGU_IER __REG32(DBGU_BASE + 0x008) /* Interrupt Enable Register */
552
#define DBGU_IDR __REG32(DBGU_BASE + 0x00C) /* Interrupt Disable Register */
553
#define DBGU_IMR __REG32(DBGU_BASE + 0x010) /* Interrupt Mask Register */
554
#define DBGU_SR __REG32(DBGU_BASE + 0x014) /* Status Register */
555
#define DBGU_RHR __REG32(DBGU_BASE + 0x018) /* Receive Holding Register */
556
#define DBGU_THR __REG32(DBGU_BASE + 0x01C) /* Transmit Holding Register */
557
#define DBGU_BRGR __REG32(DBGU_BASE + 0x020) /* Baud Rate Generator Register */
558
#define DBGU_CIDR __REG32(DBGU_BASE + 0x040) /* Chip ID Register */
559
#define DBGU_EXID __REG32(DBGU_BASE + 0x044) /* Chip ID Extension Register */
561
#define DBGU_RPR __REG32(DBGU_BASE + 0x100) /* Receiver Pointer Register */
562
#define DBGU_RCR __REG32(DBGU_BASE + 0x104) /* Receiver Counter Register */
563
#define DBGU_TPR __REG32(DBGU_BASE + 0x108) /* Transmitter Pointer Register */
564
#define DBGU_TCR __REG32(DBGU_BASE + 0x10C) /* Transmitter Counter Register */
565
#define DBGU_RNPR __REG32(DBGU_BASE + 0x110) /* Receiver Next Pointer Register */
566
#define DBGU_RNCR __REG32(DBGU_BASE + 0x114) /* Receiver Next Counter Register */
567
#define DBGU_TNPR __REG32(DBGU_BASE + 0x118) /* Transmitter Next Pointer Register */
568
#define DBGU_TNCR __REG32(DBGU_BASE + 0x11C) /* Transmitter Next Counter Register */
569
#define DBGU_PTCR __REG32(DBGU_BASE + 0x120) /* PDC Transfer Control Register */
570
#define DBGU_PTSR __REG32(DBGU_BASE + 0x124) /* PDC Transfer Status Register */
572
/* DBGU_CIDR: Chip ID Register */
573
#define DBGU_CIDR_VERSION (0x1F << 0) /* Version of device */
574
#define DBGU_CIDR_EPROC (0x07 << 5) /* Embedded Processor */
575
#define DBGU_CIDR_NVPSIZ (0x0F << 8) /* Non Volatile Program Memory Size */
576
#define DBGU_CIDR_NVPSIZ2 (0x0F << 12) /* Second Non Volatile Program Memory Size */
577
#define DBGU_CIDR_SRAMSIZ (0x0F << 16) /* Internal SRAM Size */
578
#define DBGU_CIDR_ARCH (0xFF << 20) /* Architecture Identifier */
579
#define DBGU_CIDR_NVPTYP (0x07 << 28) /* Non Volatile Program Memory Type*/
580
#define DBGU_CIDR_EXT (1u << 31) /* Extension Flag */
583
/*---------------------------------------*/
584
/* User Interface Parallel I/O Interface */
585
/*---------------------------------------*/
586
/* Parallel I/O Controller A */
587
#define PIOA_BASE 0xFFFFF400
588
#define PIOA_PER __REG32(PIOA_BASE + 0x00) /* PIO Enable Register */
589
#define PIOA_PDR __REG32(PIOA_BASE + 0x04) /* PIO Disable Register */
590
#define PIOA_PSR __REG32(PIOA_BASE + 0x08) /* PIO Status Register */
591
#define PIOA_OER __REG32(PIOA_BASE + 0x10) /* Output Enable Register */
592
#define PIOA_ODR __REG32(PIOA_BASE + 0x14) /* Output Disable Register */
593
#define PIOA_OSR __REG32(PIOA_BASE + 0x18) /* Output Status Register */
594
#define PIOA_IFER __REG32(PIOA_BASE + 0x20) /* Input Filter Enable Register */
595
#define PIOA_IFDR __REG32(PIOA_BASE + 0x24) /* Input Filter Disable Register */
596
#define PIOA_IFSR __REG32(PIOA_BASE + 0x28) /* Input Filter Status Register */
597
#define PIOA_SODR __REG32(PIOA_BASE + 0x30) /* Set Output Data Register */
598
#define PIOA_CODR __REG32(PIOA_BASE + 0x34) /* Clear Output Data Register */
599
#define PIOA_ODSR __REG32(PIOA_BASE + 0x38) /* Output Data Status Register */
600
#define PIOA_PDSR __REG32(PIOA_BASE + 0x3C) /* Pin Data Status Register */
601
#define PIOA_IER __REG32(PIOA_BASE + 0x40) /* Interrupt Enable Register */
602
#define PIOA_IDR __REG32(PIOA_BASE + 0x44) /* Interrupt Disable Register */
603
#define PIOA_IMR __REG32(PIOA_BASE + 0x48) /* Interrupt Mask Register */
604
#define PIOA_ISR __REG32(PIOA_BASE + 0x4C) /* Interrupt Status Register */
605
#define PIOA_MDER __REG32(PIOA_BASE + 0x50) /* Multi Driver Enable Register */
606
#define PIOA_MDDR __REG32(PIOA_BASE + 0x54) /* Multi Driver Disable Register */
607
#define PIOA_MDSR __REG32(PIOA_BASE + 0x58) /* Multi Driver Status Register */
608
#define PIOA_PUDR __REG32(PIOA_BASE + 0x60) /* Pull-Up Disable Register */
609
#define PIOA_PUER __REG32(PIOA_BASE + 0x64) /* Pull-Up Enable Register */
610
#define PIOA_PUSR __REG32(PIOA_BASE + 0x68) /* Pull-Up Status Register */
611
#define PIOA_ASR __REG32(PIOA_BASE + 0x70) /* Select A Register */
612
#define PIOA_BSR __REG32(PIOA_BASE + 0x74) /* Select B Register */
613
#define PIOA_ABSR __REG32(PIOA_BASE + 0x78) /* AB Select Status Register */
614
#define PIOA_OWER __REG32(PIOA_BASE + 0xA0) /* Output Write Enable Register */
615
#define PIOA_OWDR __REG32(PIOA_BASE + 0xA4) /* Output Write Disable Register */
616
#define PIOA_OWSR __REG32(PIOA_BASE + 0xA8) /* Output Write Status Register */
619
/*------------------*/
620
/* Pin Multiplexing */
621
/*------------------*/
622
#define PIO_PA0 (1 << 0) /* Pin controlled by PIO */
623
#define PA0_TWD (1 << 0) /* TWI Serial Data */
624
#define PA0_ADC0_ADTRG (1 << 0) /* ADC0 External Trigger */
626
#define PIO_PA1 (1 << 1) /* Pin controlled by PIO */
627
#define PA1_TWCK (1 << 1) /* TWI Serial Clock */
628
#define PA1_ADC1_ADTRG (1 << 1) /* ADC1 External Trigger */
630
#define PIO_PA2 (1 << 2) /* Pin controlled by PIO */
631
#define PA2_RXD0 (1 << 2) /* USART 0 Receive Data */
633
#define PIO_PA3 (1 << 3) /* Pin controlled by PIO */
634
#define PA3_TXD0 (1 << 3) /* USART 0 Transmit Data */
636
#define PIO_PA4 (1 << 4) /* Pin controlled by PIO */
637
#define PA4_SCK0 (1 << 4) /* USART 0 Serial Clock */
638
#define PA4_SPI1_NPSC0 (1 << 4) /* SPI1 Peripheral Chip Select 0 */
640
#define PIO_PA5 (1 << 5) /* Pin controlled by PIO */
641
#define PA5_RTS0 (1 << 5) /* USART 0 Ready To Send */
642
#define PA5_SPI1_NPCS1 (1 << 5) /* SPI1 Peripheral Chip Select 1 */
644
#define PIO_PA6 (1 << 6) /* Pin controlled by PIO */
645
#define PA6_CTS0 (1 << 6) /* USART 0 Clear To Send */
646
#define PA6_SPI1_NPCS2 (1 << 6) /* SPI1 Peripheral Chip Select 2 */
648
#define PIO_PA7 (1 << 7) /* Pin controlled by PIO */
649
#define PA7_RXD1 (1 << 7) /* USART 1 Receive Data */
650
#define PA7_SPI1_NPCS3 (1 << 7) /* SPI1 Peripheral Chip Select 3 */
652
#define PIO_PA8 (1 << 8) /* Pin controlled by PIO */
653
#define PA8_TXD1 (1 << 8) /* USART 1 Transmit Data */
654
#define PA8_SPI1_MISO (1 << 8) /* SPI1 Master In Slave Out */
656
#define PIO_PA9 (1 << 9) /* Pin controlled by PIO */
657
#define PA9_RXD2 (1 << 9) /* USART 2 Receive Data */
658
#define PA9_SPI1_MOSI (1 << 9) /* SPI1 Master Out Slave In */
660
#define PIO_PA10 (1 << 10) /* Pin controlled by PIO */
661
#define PA10_TXD2 (1 << 10) /* USART 2 Transmit Data */
662
#define PA10_SPI1_SPCK (1 << 10) /* SPI1 Serial Clock */
664
#define PIO_PA11 (1 << 11) /* Pin controlled by PIO */
665
#define PA11_SPI0_NPCS0 (1 << 11) /* SPI0 Peripheral Chip Select 0 */
667
#define PIO_PA12 (1 << 12) /* Pin controlled by PIO */
668
#define PA12_SPI0_NPCS1 (1 << 12) /* SPI0 Peripheral Chip Select 1 */
669
#define PA12_MCDA1 (1 << 12) /* Multimedia Card Data 1 */
671
#define PIO_PA13 (1 << 13) /* Pin controlled by PIO */
672
#define PA13_SPI0_NPCS2 (1 << 13) /* SPI0 Peripheral Chip Select 2 */
673
#define PA13_MCDA2 (1 << 13) /* Multimedia Card Data 2 */
675
#define PIO_PA14 (1 << 14) /* Pin controlled by PIO */
676
#define PA14_SPI0_NPCS3 (1 << 14) /* SPI0 Peripheral Chip Select 3 */
677
#define PA14_MCDA3 (1 << 14) /* Multimedia Card Data 3 */
679
#define PIO_PA15 (1 << 15) /* Pin controlled by PIO */
680
#define PA15_SPI0_MISO (1 << 15) /* SPI0 Master In Slave Out */
681
#define PA15_MCDA0 (1 << 15) /* Multimedia Card Data 0 */
683
#define PIO_PA16 (1 << 16) /* Pin controlled by PIO */
684
#define PA16_SPI0_MOSI (1 << 16) /* SPI0 Master Out Slave In */
685
#define PA16_MCCDA (1 << 16) /* Multimedia Card Command/Response */
687
#define PIO_PA17 (1 << 17) /* Pin controlled by PIO */
688
#define PA17_SPI0_SPCK (1 << 17) /* SPI0 Serial Clock */
689
#define PA17_MCCK (1 << 17) /* Multimedia Card Serial Clock */
691
#define PIO_PA18 (1 << 18) /* Pin controlled by PIO */
692
#define PA18_PWM0 (1 << 18) /* PWM Channel 0 */
693
#define PA18_PCK0 (1 << 18) /* PMC Programmable Clock Output 0 */
695
#define PIO_PA19 (1 << 19) /* Pin controlled by PIO */
696
#define PA19_PWM1 (1 << 19) /* PWM Channel 1 */
697
#define PA19_PCK1 (1 << 19) /* PMC Programmable Clock Output 1 */
699
#define PIO_PA20 (1 << 20) /* Pin controlled by PIO */
700
#define PA20_PWM2 (1 << 20) /* PWM Channel 2 */
701
#define PA20_PCK2 (1 << 20) /* PMC Programmable Clock Output 2 */
703
#define PIO_PA21 (1 << 21) /* Pin controlled by PIO */
704
#define PA21_PWM3 (1 << 21) /* PWM Channel 3 */
705
#define PA21_PCK3 (1 << 21) /* PMC Programmable Clock Output 3 */
707
#define PIO_PA22 (1 << 22) /* Pin controlled by PIO */
708
#define PA22_PWM4 (1 << 22) /* PWM Channel 4 */
709
#define PA22_IRQ0 (1 << 22) /* External Interrupt 0 */
711
#define PIO_PA23 (1 << 23) /* Pin controlled by PIO */
712
#define PA23_PWM5 (1 << 23) /* PWM Channel 5 */
713
#define PA23_IRQ1 (1 << 23) /* External Interrupt 1 */
715
#define PIO_PA24 (1 << 24) /* Pin controlled by PIO */
716
#define PA24_PWM6 (1 << 24) /* PWM Channel 6 */
717
#define PA24_TCLK4 (1 << 24) /* Timer Counter 4 external clock input */
719
#define PIO_PA25 (1 << 25) /* Pin controlled by PIO */
720
#define PA25_PWM7 (1 << 25) /* PWM Channel 7 */
721
#define PA25_TCLK5 (1 << 25) /* Timer Counter 5 external clock input */
723
#define PIO_PA26 (1 << 26) /* Pin controlled by PIO */
724
#define PA26_CANRX0 (1 << 26) /* CAN Controller 0 Receive Data */
726
#define PIO_PA27 (1 << 27) /* Pin controlled by PIO */
727
#define PA27_CANTX0 (1 << 27) /* CAN Controller 0 Transmit Data */
729
#define PIO_PA28 (1 << 28) /* Pin controlled by PIO */
730
#define PA28_CANRX1 (1 << 28) /* CAN Controller 1 Receive Data */
731
#define PA28_TCLK3 (1 << 28) /* Timer Counter 3 external clock input */
733
#define PIO_PA29 (1 << 29) /* Pin controlled by PIO */
734
#define PA29_CANTX1 (1 << 29) /* CAN Controller 1 Transmit Data */
735
#define PA29_TCLK6 (1 << 29) /* Timer Counter 6 external clock input */
737
#define PIO_PA30 (1 << 30) /* Pin controlled by PIO */
738
#define PA30_DRXD (1 << 30) /* Debug Unit Receive Data */
739
#define PA30_TCLK7 (1 << 30) /* Timer Counter 7 external clock input */
741
#define PIO_PA31 (1u << 31) /* Pin controlled by PIO */
742
#define PA31_DTXD (1u << 31) /* Debug Unit Transmit Data */
743
#define PA31_TCLK8 (1u << 31) /* Timer Counter 8 external clock input */
745
/* Parallel I/O Controller B */
746
#define PIOB_BASE 0xFFFFF600
747
#define PIOB_PER __REG32(PIOB_BASE + 0x00) /* PIO Enable Register */
748
#define PIOB_PDR __REG32(PIOB_BASE + 0x04) /* PIO Disable Register */
749
#define PIOB_PSR __REG32(PIOB_BASE + 0x08) /* PIO Status Register */
750
#define PIOB_OER __REG32(PIOB_BASE + 0x10) /* Output Enable Register */
751
#define PIOB_ODR __REG32(PIOB_BASE + 0x14) /* Output Disable Register */
752
#define PIOB_OSR __REG32(PIOB_BASE + 0x18) /* Output Status Register */
753
#define PIOB_IFER __REG32(PIOB_BASE + 0x20) /* Input Filter Enable Register */
754
#define PIOB_IFDR __REG32(PIOB_BASE + 0x24) /* Input Filter Disable Register */
755
#define PIOB_IFSR __REG32(PIOB_BASE + 0x28) /* Input Filter Status Register */
756
#define PIOB_SODR __REG32(PIOB_BASE + 0x30) /* Set Output Data Register */
757
#define PIOB_CODR __REG32(PIOB_BASE + 0x34) /* Clear Output Data Register */
758
#define PIOB_ODSR __REG32(PIOB_BASE + 0x38) /* Output Data Status Register */
759
#define PIOB_PDSR __REG32(PIOB_BASE + 0x3C) /* Pin Data Status Register */
760
#define PIOB_IER __REG32(PIOB_BASE + 0x40) /* Interrupt Enable Register */
761
#define PIOB_IDR __REG32(PIOB_BASE + 0x44) /* Interrupt Disable Register */
762
#define PIOB_IMR __REG32(PIOB_BASE + 0x48) /* Interrupt Mask Register */
763
#define PIOB_ISR __REG32(PIOB_BASE + 0x4C) /* Interrupt Status Register */
764
#define PIOB_MDER __REG32(PIOB_BASE + 0x50) /* Multi Driver Enable Register */
765
#define PIOB_MDDR __REG32(PIOB_BASE + 0x54) /* Multi Driver Disable Register */
766
#define PIOB_MDSR __REG32(PIOB_BASE + 0x58) /* Multi Driver Status Register */
767
#define PIOB_PUDR __REG32(PIOB_BASE + 0x60) /* Pull-Up Disable Register */
768
#define PIOB_PUER __REG32(PIOB_BASE + 0x64) /* Pull-Up Enable Register */
769
#define PIOB_PUSR __REG32(PIOB_BASE + 0x68) /* Pull-Up Status Register */
770
#define PIOB_ASR __REG32(PIOB_BASE + 0x70) /* Select A Register */
771
#define PIOB_BSR __REG32(PIOB_BASE + 0x74) /* Select B Register */
772
#define PIOB_ABSR __REG32(PIOB_BASE + 0x78) /* AB Select Status Register */
773
#define PIOB_OWER __REG32(PIOB_BASE + 0xA0) /* Output Write Enable Register */
774
#define PIOB_OWDR __REG32(PIOB_BASE + 0xA4) /* Output Write Disable Register */
775
#define PIOB_OWSR __REG32(PIOB_BASE + 0xA8) /* Output Write Status Register */
778
/*------------------*/
779
/* Pin Multiplexing */
780
/*------------------*/
781
#define PIO_PB0 (1 << 0) /* Pin controlled by PIO */
782
#define PB0_IRQ2 (1 << 0) /* External Interrupt 2 */
783
#define PB0_PWM5 (1 << 0) /* PWM Channel 5 */
785
#define PIO_PB1 (1 << 1) /* Pin controlled by PIO */
786
#define PB1_IRQ3 (1 << 1) /* External Interrupt 3 */
787
#define PB1_PWM6 (1 << 1) /* PWM Channel 6 */
789
#define PIO_PB2 (1 << 2) /* Pin controlled by PIO */
790
#define PB2_TF0 (1 << 2) /* SSC0 Transmit Frame Sync */
791
#define PB2_PWM7 (1 << 2) /* PWM Channel 7 */
793
#define PIO_PB3 (1 << 3) /* Pin controlled by PIO */
794
#define PB3_TK0 (1 << 3) /* SSC0 Transmit Clock */
795
#define PB3_PCK0 (1 << 3) /* PMC Programmable Clock Output 0 */
797
#define PIO_PB4 (1 << 4) /* Pin controlled by PIO */
798
#define PB4_TD0 (1 << 4) /* SSC0 Transmit Data */
799
#define PB4_PCK1 (1 << 4) /* PMC Programmable Clock Output 1 */
801
#define PIO_PB5 (1 << 5) /* Pin controlled by PIO */
802
#define PB5_RD0 (1 << 5) /* SSC0 Receive Data */
803
#define PB5_PCK2 (1 << 5) /* PMC Programmable Clock Output 2 */
805
#define PIO_PB6 (1 << 6) /* Pin controlled by PIO */
806
#define PB6_RK0 (1 << 6) /* SSC0 Receive Clock */
807
#define PB6_PCK3 (1 << 6) /* PMC Programmable Clock Output 3 */
809
#define PIO_PB7 (1 << 7) /* Pin controlled by PIO */
810
#define PB7_RF0 (1 << 7) /* SSC0 Receive Frame Sync */
811
#define PB7_CANTX1 (1 << 7) /* CAN Controller 1 Transmit Data */
813
#define PIO_PB8 (1 << 8) /* Pin controlled by PIO */
814
#define PB8_FIQ (1 << 8) /* AIC Fast Interrupt Input */
815
#define PB8_TF1 (1 << 8) /* SSC1 Transmit Frame Sync */
817
#define PIO_PB9 (1 << 9) /* Pin controlled by PIO */
818
#define PB9_TCLK0 (1 << 9) /* Timer Counter 0 external clock input */
819
#define PB9_TK1 (1 << 9) /* SSC1 Transmit Clock */
821
#define PIO_PB10 (1 << 10) /* Pin controlled by PIO */
822
#define PB10_TCLK1 (1 << 10) /* Timer Counter 1 external clock input */
823
#define PB10_RK1 (1 << 10) /* SSC1 Receive Clock */
825
#define PIO_PB11 (1 << 11) /* Pin controlled by PIO */
826
#define PB11_TCLK2 (1 << 11) /* Timer Counter 2 external clock input */
827
#define PB11_RF1 (1 << 11) /* SSC1 Receive Frame Sync */
829
#define PIO_PB12 (1 << 12) /* Pin controlled by PIO */
830
#define PB12_TIOA0 (1 << 12) /* Timer Counter 0 multi purpose I/O pin A */
831
#define PB12_TD1 (1 << 12) /* SSC1 Transmit Data */
833
#define PIO_PB13 (1 << 13) /* Pin controlled by PIO */
834
#define PB13_TIOB0 (1 << 13) /* Timer Counter 0 multi purpose I/O pin B */
835
#define PB13_RD1 (1 << 13) /* SSC1 Receive Data */
837
#define PIO_PB14 (1 << 14) /* Pin controlled by PIO (ADC0_AD0) */
838
#define PB14_TIOA1 (1 << 14) /* Timer Counter 1 multi purpose I/O pin A */
839
#define PB14_PWM0 (1 << 14) /* PWM Channel 0 */
841
#define PIO_PB15 (1 << 15) /* Pin controlled by PIO (ADC0_AD1) */
842
#define PB15_TIOB1 (1 << 15) /* Timer Counter 1 multi purpose I/O pin B */
843
#define PB15_PWM1 (1 << 15) /* PWM Channel 1 */
845
#define PIO_PB16 (1 << 16) /* Pin controlled by PIO (ADC0_AD2) */
846
#define PB16_TIOA2 (1 << 16) /* Timer Counter 2 multi purpose I/O pin A */
847
#define PB16_PWM2 (1 << 16) /* PWM Channel 2 */
849
#define PIO_PB17 (1 << 17) /* Pin controlled by PIO (ADC0_AD3) */
850
#define PB17_TIOB2 (1 << 17) /* Timer Counter 2 multi purpose I/O pin B */
851
#define PB17_PWM3 (1 << 17) /* PWM Channel 3 */
853
#define PIO_PB18 (1 << 18) /* Pin controlled by PIO (ADC0_AD4) */
854
#define PB18_TIOA3 (1 << 18) /* Timer Counter 3 multi purpose I/O pin A */
855
#define PB18_PWM4 (1 << 18) /* PWM Channel 4 */
857
#define PIO_PB19 (1 << 19) /* Pin controlled by PIO (ADC0_AD5) */
858
#define PB19_TIOB3 (1 << 19) /* Timer Counter 3 multi purpose I/O pin B */
859
#define PB19_SPI1_NPCS1 (1 << 19) /* SPI1 Peripheral Chip Select 1 */
861
#define PIO_PB20 (1 << 20) /* Pin controlled by PIO (ADC0_AD6) */
862
#define PB20_TIOA4 (1 << 20) /* Timer Counter 4 multi purpose I/O pin A */
863
#define PB20_SPI1_NPCS2 (1 << 20) /* SPI1 Peripheral Chip Select 2 */
865
#define PIO_PB21 (1 << 21) /* Pin controlled by PIO (ADC0_AD7) */
866
#define PB21_TIOB4 (1 << 21) /* Timer Counter 4 multi purpose I/O pin B */
867
#define PB21_SPI1_NPCS3 (1 << 21) /* SPI1 Peripheral Chip Select 3 */
869
#define PIO_PB22 (1 << 22) /* Pin controlled by PIO (ADC1_AD0) */
870
#define PB22_TIOA5 (1 << 22) /* Timer Counter 5 multi purpose I/O pin A */
872
#define PIO_PB23 (1 << 23) /* Pin controlled by PIO (ADC1_AD1) */
873
#define PB23_TIOB5 (1 << 23) /* Timer Counter 5 multi purpose I/O pin B */
875
#define PIO_PB24 (1 << 24) /* Pin controlled by PIO (ADC1_AD2) */
876
#define PB24_TIOA6 (1 << 24) /* Timer Counter 6 multi purpose I/O pin A */
877
#define PB24_RTS1 (1 << 24) /* USART 1 Ready To Send */
879
#define PIO_PB25 (1 << 25) /* Pin controlled by PIO (ADC1_AD3) */
880
#define PB25_TIOB6 (1 << 25) /* Timer Counter 6 multi purpose I/O pin B */
881
#define PB25_CTS1 (1 << 25) /* USART 1 Clear To Send */
883
#define PIO_PB26 (1 << 26) /* Pin controlled by PIO (ADC1_AD4) */
884
#define PB26_TIOA7 (1 << 26) /* Timer Counter 7 multi purpose I/O pin A */
885
#define PB26_SCK1 (1 << 26) /* USART 1 Serial Clock */
887
#define PIO_PB27 (1 << 27) /* Pin controlled by PIO (ADC1_AD5) */
888
#define PB27_TIOB7 (1 << 27) /* Timer Counter 7 multi purpose I/O pin B */
889
#define PB27_RTS2 (1 << 27) /* USART 2 Ready To Send */
891
#define PIO_PB28 (1 << 28) /* Pin controlled by PIO (ADC1_AD6) */
892
#define PB28_TIOA8 (1 << 28) /* Timer Counter 8 multi purpose I/O pin A */
893
#define PB28_CTS2 (1 << 28) /* USART 2 Clear To Send */
895
#define PIO_PB29 (1 << 29) /* Pin controlled by PIO (ADC1_AD7) */
896
#define PB29_TIOB8 (1 << 29) /* Timer Counter 8 multi purpose I/O pin B */
897
#define PB29_SCK2 (1 << 29) /* USART 2 Serial Clock */
901
/*-----------------------------------*/
902
/* User Interface Timer/Counter Unit */
903
/*-----------------------------------*/
905
/* Timer Control Block 0: Channels 0, 1, 2 */
906
#define TCB0_BASE 0xFFFA0000
907
#define TC0_CCR __REG32(TCB0_BASE + 0x00) /* Control Register */
908
#define TC0_CMR __REG32(TCB0_BASE + 0x04) /* Mode Register */
909
#define TC0_CV __REG32(TCB0_BASE + 0x10) /* Counter value */
910
#define TC0_RA __REG32(TCB0_BASE + 0x14) /* Register A */
911
#define TC0_RB __REG32(TCB0_BASE + 0x18) /* Register B */
912
#define TC0_RC __REG32(TCB0_BASE + 0x1C) /* Register C */
913
#define TC0_SR __REG32(TCB0_BASE + 0x20) /* Status Register */
914
#define TC0_IER __REG32(TCB0_BASE + 0x24) /* Interrupt Enable Register */
915
#define TC0_IDR __REG32(TCB0_BASE + 0x28) /* Interrupt Disable Register */
916
#define TC0_IMR __REG32(TCB0_BASE + 0x2C) /* Interrupt Mask Register */
918
#define TC1_CCR __REG32(TCB0_BASE + 0x40) /* Control Register */
919
#define TC1_CMR __REG32(TCB0_BASE + 0x44) /* Mode Register */
920
#define TC1_CV __REG32(TCB0_BASE + 0x50) /* Counter value */
921
#define TC1_RA __REG32(TCB0_BASE + 0x54) /* Register A */
922
#define TC1_RB __REG32(TCB0_BASE + 0x58) /* Register B */
923
#define TC1_RC __REG32(TCB0_BASE + 0x5C) /* Register C */
924
#define TC1_SR __REG32(TCB0_BASE + 0x60) /* Status Register */
925
#define TC1_IER __REG32(TCB0_BASE + 0x64) /* Interrupt Enable Register */
926
#define TC1_IDR __REG32(TCB0_BASE + 0x68) /* Interrupt Disable Register */
927
#define TC1_IMR __REG32(TCB0_BASE + 0x6C) /* Interrupt Mask Register */
929
#define TC2_CCR __REG32(TCB0_BASE + 0x80) /* Control Register */
930
#define TC2_CMR __REG32(TCB0_BASE + 0x84) /* Mode Register */
931
#define TC2_CV __REG32(TCB0_BASE + 0x90) /* Counter value */
932
#define TC2_RA __REG32(TCB0_BASE + 0x94) /* Register A */
933
#define TC2_RB __REG32(TCB0_BASE + 0x98) /* Register B */
934
#define TC2_RC __REG32(TCB0_BASE + 0x9C) /* Register C */
935
#define TC2_SR __REG32(TCB0_BASE + 0xA0) /* Status Register */
936
#define TC2_IER __REG32(TCB0_BASE + 0xA4) /* Interrupt Enable Register */
937
#define TC2_IDR __REG32(TCB0_BASE + 0xA8) /* Interrupt Disable Register */
938
#define TC2_IMR __REG32(TCB0_BASE + 0xAC) /* Interrupt Mask Register */
940
#define TCB0_BCR __REG32(TCB0_BASE + 0xC0) /* Block Control Register */
941
#define TCB0_BMR __REG32(TCB0_BASE + 0xC4) /* Block Mode Register */
943
/* Timer Control Block 1: Channels 3, 4, 5 */
944
#define TCB1_BASE 0xFFFA4000
945
#define TC3_CCR __REG32(TCB1_BASE + 0x00) /* Control Register */
946
#define TC3_CMR __REG32(TCB1_BASE + 0x04) /* Mode Register */
947
#define TC3_CV __REG32(TCB1_BASE + 0x10) /* Counter value */
948
#define TC3_RA __REG32(TCB1_BASE + 0x14) /* Register A */
949
#define TC3_RB __REG32(TCB1_BASE + 0x18) /* Register B */
950
#define TC3_RC __REG32(TCB1_BASE + 0x1C) /* Register C */
951
#define TC3_SR __REG32(TCB1_BASE + 0x20) /* Status Register */
952
#define TC3_IER __REG32(TCB1_BASE + 0x24) /* Interrupt Enable Register */
953
#define TC3_IDR __REG32(TCB1_BASE + 0x28) /* Interrupt Disable Register */
954
#define TC3_IMR __REG32(TCB1_BASE + 0x2C) /* Interrupt Mask Register */
956
#define TC4_CCR __REG32(TCB1_BASE + 0x40) /* Control Register */
957
#define TC4_CMR __REG32(TCB1_BASE + 0x44) /* Mode Register */
958
#define TC4_CV __REG32(TCB1_BASE + 0x50) /* Counter value */
959
#define TC4_RA __REG32(TCB1_BASE + 0x54) /* Register A */
960
#define TC4_RB __REG32(TCB1_BASE + 0x58) /* Register B */
961
#define TC4_RC __REG32(TCB1_BASE + 0x5C) /* Register C */
962
#define TC4_SR __REG32(TCB1_BASE + 0x60) /* Status Register */
963
#define TC4_IER __REG32(TCB1_BASE + 0x64) /* Interrupt Enable Register */
964
#define TC4_IDR __REG32(TCB1_BASE + 0x68) /* Interrupt Disable Register */
965
#define TC4_IMR __REG32(TCB1_BASE + 0x6C) /* Interrupt Mask Register */
967
#define TC5_CCR __REG32(TCB1_BASE + 0x80) /* Control Register */
968
#define TC5_CMR __REG32(TCB1_BASE + 0x84) /* Mode Register */
969
#define TC5_CV __REG32(TCB1_BASE + 0x90) /* Counter value */
970
#define TC5_RA __REG32(TCB1_BASE + 0x94) /* Register A */
971
#define TC5_RB __REG32(TCB1_BASE + 0x98) /* Register B */
972
#define TC5_RC __REG32(TCB1_BASE + 0x9C) /* Register C */
973
#define TC5_SR __REG32(TCB1_BASE + 0xA0) /* Status Register */
974
#define TC5_IER __REG32(TCB1_BASE + 0xA4) /* Interrupt Enable Register */
975
#define TC5_IDR __REG32(TCB1_BASE + 0xA8) /* Interrupt Disable Register */
976
#define TC5_IMR __REG32(TCB1_BASE + 0xAC) /* Interrupt Mask Register */
978
#define TCB1_BCR __REG32(TCB1_BASE + 0xC0) /* Block Control Register */
979
#define TCB1_BMR __REG32(TCB1_BASE + 0xC4) /* Block Mode Register */
981
/* Timer Control Block 2: Channels 6, 7, 8 */
982
#define TCB2_BASE 0xFFFA8000
983
#define TC6_CCR __REG32(TCB2_BASE + 0x00) /* Control Register */
984
#define TC6_CMR __REG32(TCB2_BASE + 0x04) /* Mode Register */
985
#define TC6_CV __REG32(TCB2_BASE + 0x10) /* Counter value */
986
#define TC6_RA __REG32(TCB2_BASE + 0x14) /* Register A */
987
#define TC6_RB __REG32(TCB2_BASE + 0x18) /* Register B */
988
#define TC6_RC __REG32(TCB2_BASE + 0x1C) /* Register C */
989
#define TC6_SR __REG32(TCB2_BASE + 0x20) /* Status Register */
990
#define TC6_IER __REG32(TCB2_BASE + 0x24) /* Interrupt Enable Register */
991
#define TC6_IDR __REG32(TCB2_BASE + 0x28) /* Interrupt Disable Register */
992
#define TC6_IMR __REG32(TCB2_BASE + 0x2C) /* Interrupt Mask Register */
994
#define TC7_CCR __REG32(TCB2_BASE + 0x40) /* Control Register */
995
#define TC7_CMR __REG32(TCB2_BASE + 0x44) /* Mode Register */
996
#define TC7_CV __REG32(TCB2_BASE + 0x50) /* Counter value */
997
#define TC7_RA __REG32(TCB2_BASE + 0x54) /* Register A */
998
#define TC7_RB __REG32(TCB2_BASE + 0x58) /* Register B */
999
#define TC7_RC __REG32(TCB2_BASE + 0x5C) /* Register C */
1000
#define TC7_SR __REG32(TCB2_BASE + 0x60) /* Status Register */
1001
#define TC7_IER __REG32(TCB2_BASE + 0x64) /* Interrupt Enable Register */
1002
#define TC7_IDR __REG32(TCB2_BASE + 0x68) /* Interrupt Disable Register */
1003
#define TC7_IMR __REG32(TCB2_BASE + 0x6C) /* Interrupt Mask Register */
1005
#define TC8_CCR __REG32(TCB2_BASE + 0x80) /* Control Register */
1006
#define TC8_CMR __REG32(TCB2_BASE + 0x84) /* Mode Register */
1007
#define TC8_CV __REG32(TCB2_BASE + 0x90) /* Counter value */
1008
#define TC8_RA __REG32(TCB2_BASE + 0x94) /* Register A */
1009
#define TC8_RB __REG32(TCB2_BASE + 0x98) /* Register B */
1010
#define TC8_RC __REG32(TCB2_BASE + 0x9C) /* Register C */
1011
#define TC8_SR __REG32(TCB2_BASE + 0xA0) /* Status Register */
1012
#define TC8_IER __REG32(TCB2_BASE + 0xA4) /* Interrupt Enable Register */
1013
#define TC8_IDR __REG32(TCB2_BASE + 0xA8) /* Interrupt Disable Register */
1014
#define TC8_IMR __REG32(TCB2_BASE + 0xAC) /* Interrupt Mask Register */
1016
#define TCB2_BCR __REG32(TCB2_BASE + 0xC0) /* Block Control Register */
1017
#define TCB2_BMR __REG32(TCB2_BASE + 0xC4) /* Block Mode Register */
1020
/*--------------------------------------------------------*/
1021
/* TC_CCR: Timer Counter Control Register Bits Definition */
1022
/*--------------------------------------------------------*/
1023
#define TC_CLKEN (1 << 0) /* Counter Clock Enable */
1024
#define TC_CLKDIS (1 << 1) /* Counter Clock Disable */
1025
#define TC_SWTRG (1 << 2) /* Software Trigger */
1027
/* TC_CMR: Timer Counter Channel Mode Register Bits Definition */
1029
/* Clock Selection */
1030
#define TC_CLKS (0x07 << 0)
1031
#define TC_CLKS_MCK2 (0x00 << 0)
1032
#define TC_CLKS_MCK8 (0x01 << 0)
1033
#define TC_CLKS_MCK32 (0x02 << 0)
1034
#define TC_CLKS_MCK128 (0x03 << 0)
1035
#define TC_CLKS_MCK1024 (0x04 << 0)
1037
#define TC_CLKS_SLCK (0x04 << 0)
1039
#define TC_CLKS_XC0 (0x05 << 0)
1040
#define TC_CLKS_XC1 (0x06 << 0)
1041
#define TC_CLKS_XC2 (0x07 << 0)
1044
/* Clock Inversion */
1045
#define TC_CLKI (1 << 3)
1047
/* Burst Signal Selection */
1048
#define TC_BURST (0x03 << 4)
1049
#define TC_BURST_NONE (0x00 << 4)
1050
#define TC_BUSRT_XC0 (0x01 << 4)
1051
#define TC_BURST_XC1 (0x02 << 4)
1052
#define TC_BURST_XC2 (0x03 << 4)
1054
/* Capture Mode : Counter Clock Stopped with RB Loading */
1055
#define TC_LDBSTOP (1 << 6)
1057
/* Waveform Mode : Counter Clock Stopped with RC Compare */
1058
#define TC_CPCSTOP (1 << 6)
1060
/* Capture Mode : Counter Clock Disabled with RB Loading */
1061
#define TC_LDBDIS (1 << 7)
1063
/* Waveform Mode : Counter Clock Disabled with RC Compare */
1064
#define TC_CPCDIS (1 << 7)
1066
/* Capture Mode : External Trigger Edge Selection */
1067
#define TC_ETRGEDG (0x03 << 8)
1068
#define TC_ETRGEDG_NONE (0x00 << 8)
1069
#define TC_ETRGEDG_RISING (0x01 << 8)
1070
#define TC_ETRGEDG_FALLING (0x02 << 8)
1071
#define TC_ETRGEDG_BOTH (0x03 << 8)
1073
/* Waveform Mode : External Event Edge Selection */
1074
#define TC_EEVTEDG (0x03 << 8)
1075
#define TC_EEVTEDG_NONE (0x00 << 8)
1076
#define TC_EEVTEDG_RISING (0x01 << 8)
1077
#define TC_EEVTEDG_FALLING (0x02 << 8)
1078
#define TC_EEVTEDG_BOTH (0x03 << 8)
1080
/* Capture Mode : TIOA or TIOB External Trigger Selection */
1081
#define TC_ABETRG (0x01 << 10)
1082
#define TC_ABETRG_TIOB (0x00 << 10)
1083
#define TC_ABETRG_TIOA (0x01 << 10)
1085
/* Waveform Mode : External Event Selection */
1086
#define TC_EEVT (0x03 << 10)
1087
#define TC_EEVT_TIOB (0x00 << 10)
1088
#define TC_EEVT_XC0 (0x01 << 10)
1089
#define TC_EEVT_XC1 (0x02 << 10)
1090
#define TC_EEVT_XC2 (0x03 << 10)
1093
#define TC_ENETRG (1 << 12) /* Waveform Mode : External Event Trigger enable */
1095
#define TC_CPCTRG (1 << 14) /* RC Compare Trigger Enable */
1097
/* Mode Selection */
1098
#define TC_WAVE (1 << 15)
1099
#define TC_CAPT (0 << 15)
1101
/* Capture Mode : RA Loading Selection */
1102
#define TC_LDRA (0x03 << 16)
1103
#define TC_LDRA_NONE (0x00 << 16)
1104
#define TC_LDRA_RISING (0x01 << 16)
1105
#define TC_LDRA_FALLING (0x02 << 16)
1106
#define TC_LDRA_BOTH (0x03 << 16)
1108
/* Waveform Mode : RA Compare Effect on TIOA */
1109
#define TC_ACPA (0x03 << 16)
1110
#define TC_ACPA_NONE (0x00 << 16)
1111
#define TC_ACPA_SET (0x01 << 16)
1112
#define TC_ACPA_CLEAR (0x02 << 16)
1113
#define TC_ACPA_TOGGLE (0x03 << 16)
1115
/* Capture Mode : RB Loading Selection */
1116
#define TC_LDRB (0x03 << 18)
1117
#define TC_LDRB_NONE (0x00 << 18)
1118
#define TC_LDRB_RISING (0x01 << 18)
1119
#define TC_LDRB_FALLING (0x02 << 18)
1120
#define TC_LDRB_BOTH (0x03 << 18)
1122
/* Waveform Mode : RC Compare Effect on TIOA */
1123
#define TC_ACPC (0x03 << 18)
1124
#define TC_ACPC_NONE (0x00 << 18)
1125
#define TC_ACPC_SET (0x01 << 18)
1126
#define TC_ACPC_CLEAR (0x02 << 18)
1127
#define TC_ACPC_TOGGLE (0x03 << 18)
1129
/* Waveform Mode : External Event Effect on TIOA */
1130
#define TC_AEEVT (0x03 << 20)
1131
#define TC_AEEVT_NONE (0x00 << 20)
1132
#define TC_AEEVT_SET (0x01 << 20)
1133
#define TC_AEEVT_CLEAR (0x02 << 20)
1134
#define TC_AEEVT_TOGGLE (0x03 << 20)
1136
/* Waveform Mode : Software Trigger Effect on TIOA */
1137
#define TC_ASWTRG (0x03 << 22)
1138
#define TC_ASWTRG_NONE (0x00 << 22)
1139
#define TC_ASWTRG_SET (0x01 << 22)
1140
#define TC_ASWTRG_CLEAR (0x02 << 22)
1141
#define TC_ASWTRG_TOGGLE (0x03 << 22)
1143
/* Waveform Mode : RB Compare Effect on TIOB */
1144
#define TC_BCPB (0x01 << 24)
1145
#define TC_BCPB_NONE (0x00 << 24)
1146
#define TC_BCPB_SET (0x01 << 24)
1147
#define TC_BCPB_CLEAR (0x02 << 24)
1148
#define TC_BCPB_TOGGLE (0x03 << 24)
1150
/* Waveform Mode : RC Compare Effect on TIOB */
1151
#define TC_BCPC (0x03 << 26)
1152
#define TC_BCPC_NONE (0x00 << 26)
1153
#define TC_BCPC_SET (0x01 << 26)
1154
#define TC_BCPC_CLEAR (0x02 << 26)
1155
#define TC_BCPC_TOGGLE (0x03 << 26)
1157
/* Waveform Mode : External Event Effect on TIOB */
1158
#define TC_BEEVT (0x03 << 28)
1159
#define TC_BEEVT_NONE (0x00 << 28)
1160
#define TC_BEEVT_SET (0x01 << 28)
1161
#define TC_BEEVT_CLEAR (0x02 << 28)
1162
#define TC_BEEVT_TOGGLE (0x03 << 28)
1164
/* Waveform Mode : Software Trigger Effect on TIOB */
1165
#define TC_BSWTRG (0x03u << 30)
1166
#define TC_BSWTRG_NONE (0x00u << 30)
1167
#define TC_BSWTRG_SET (0x01u << 30)
1168
#define TC_BSWTRG_CLEAR (0x02u << 30)
1169
#define TC_BSWTRG_TOGGLE (0x03u << 30)
1171
/* TC_SR: Timer Counter Status Register Bits Definition */
1172
#define TC_COVFS (1 << 0) /* Counter Overflow Status */
1173
#define TC_LOVRS (1 << 1) /* Load Overrun Status */
1174
#define TC_CPAS (1 << 2) /* RA Compare Status */
1175
#define TC_CPBS (1 << 3) /* RB Compare Status */
1176
#define TC_CPCS (1 << 4) /* RC Compare Status */
1177
#define TC_LDRAS (1 << 5) /* RA Loading Status */
1178
#define TC_LDRBS (1 << 6) /* RB Loading Status */
1179
#define TC_ETRGS (1 << 7) /* External Trigger Status */
1180
#define TC_CLKSTA (1 << 16) /* Clock Status */
1181
#define TC_MTIOA (1 << 17) /* TIOA Mirror */
1182
#define TC_MTIOB (1 << 18) /* TIOB Mirror */
1184
/* TC_BCR: Timer Counter Block Control Register Bits Definition */
1185
#define TC_SYNC (1 << 0) /* Synchronisation Trigger */
1187
/* TC_BMR: Timer Counter Block Mode Register Bits Definition */
1188
#define TC_TC0XC0S (0x03 << 0) /* External Clock Signal 0 Selection */
1189
#define TC_TC0XC0S_TCLK0 (0x00 << 0) /* TCLK0 connected to XC0 */
1190
#define TC_TC0XC0S_NONE (0x01 << 0) /* No signal connected to XC0 */
1191
#define TC_TC0XC0S_TIOA1 (0x02 << 0) /* TIOA1 connected to XC0 */
1192
#define TC_TC0XC0S_TIOA2 (0x03 << 0) /* TIOA2 connected to XC0 */
1194
#define TC_TC1XC1S (0x03 << 2) /* External Clock Signal 1 Selection */
1195
#define TC_TC1XC1S_TCLK1 (0x00 << 2) /* TCLK1 connected to XC1 */
1196
#define TC_TC1XC1S_NONE (0x01 << 2) /* No signal connected to XC1 */
1197
#define TC_TC1XC1S_TIOA0 (0x02 << 2) /* TIOA0 connected to XC1 */
1198
#define TC_TC1XC1S_TIOA2 (0x03 << 2) /* TIOA2 connected to XC1 */
1200
#define TC_TC2XC2S (0x03 << 4) /* External Clock Signal 2 Selection */
1201
#define TC_TC2XC2S_TCLK2 (0x00 << 4) /* TCLK2 connected to XC2 */
1202
#define TC_TC2XC2S_NONE (0x01 << 4) /* No signal connected to XC2 */
1203
#define TC_TC2XC2S_TIOA0 (0x02 << 4) /* TIOA0 connected to XC2 */
1204
#define TC_TC2XC2S_TIOA1 (0x03 << 4) /* TIOA1 connected to XC2 */
1208
/*----------------------*/
1209
/* User Interface USART */
1210
/*----------------------*/
1213
#define USART0_BASE 0xFFFC0000
1214
#define US0_CR __REG32(USART0_BASE + 0x000) /* Control Register */
1215
#define US0_MR __REG32(USART0_BASE + 0x004) /* Mode Register */
1216
#define US0_IER __REG32(USART0_BASE + 0x008) /* Interrupt Enable Register */
1217
#define US0_IDR __REG32(USART0_BASE + 0x00C) /* Interrupt Disable Register */
1218
#define US0_IMR __REG32(USART0_BASE + 0x010) /* Interrupt Mask Register */
1219
#define US0_CSR __REG32(USART0_BASE + 0x014) /* Channel Status Register */
1220
#define US0_RHR __REG32(USART0_BASE + 0x018) /* Receive Holding Register */
1221
#define US0_THR __REG32(USART0_BASE + 0x01C) /* Transmit Holding Register */
1222
#define US0_BRGR __REG32(USART0_BASE + 0x020) /* Baud Rate Generator Register */
1223
#define US0_RTOR __REG32(USART0_BASE + 0x024) /* Receiver Timeout Register */
1224
#define US0_TTGR __REG32(USART0_BASE + 0x028) /* Transmitter Time-guard Register */
1225
#define US0_FIDI __REG32(USART0_BASE + 0x040) /* FI_DI_Ratio Register */
1226
#define US0_NER __REG32(USART0_BASE + 0x044) /* Number of Errors Register */
1227
#define US0_IF __REG32(USART0_BASE + 0x04C) /* IrDA Filter Register */
1229
#define US0_RPR __REG32(USART0_BASE + 0x100) /* Receiver Pointer Register */
1230
#define US0_RCR __REG32(USART0_BASE + 0x104) /* Receiver Counter Register */
1231
#define US0_TPR __REG32(USART0_BASE + 0x108) /* Transmitter Pointer Register */
1232
#define US0_TCR __REG32(USART0_BASE + 0x10C) /* Transmitter Counter Register */
1233
#define US0_RNPR __REG32(USART0_BASE + 0x110) /* Receiver Next Pointer Register */
1234
#define US0_RNCR __REG32(USART0_BASE + 0x114) /* Receiver Next Counter Register */
1235
#define US0_TNPR __REG32(USART0_BASE + 0x118) /* Transmitter Next Pointer Register */
1236
#define US0_TNCR __REG32(USART0_BASE + 0x11C) /* Transmitter Next Counter Register */
1237
#define US0_PTCR __REG32(USART0_BASE + 0x120) /* PDC Transfer Control Register */
1238
#define US0_PTSR __REG32(USART0_BASE + 0x124) /* PDC Transfer Status Register */
1241
#define USART1_BASE 0xFFFC4000
1242
#define US1_CR __REG32(USART1_BASE + 0x000) /* Control Register */
1243
#define US1_MR __REG32(USART1_BASE + 0x004) /* Mode Register */
1244
#define US1_IER __REG32(USART1_BASE + 0x008) /* Interrupt Enable Register */
1245
#define US1_IDR __REG32(USART1_BASE + 0x00C) /* Interrupt Disable Register */
1246
#define US1_IMR __REG32(USART1_BASE + 0x010) /* Interrupt Mask Register */
1247
#define US1_CSR __REG32(USART1_BASE + 0x014) /* Channel Status Register */
1248
#define US1_RHR __REG32(USART1_BASE + 0x018) /* Receive Holding Register */
1249
#define US1_THR __REG32(USART1_BASE + 0x01C) /* Transmit Holding Register */
1250
#define US1_BRGR __REG32(USART1_BASE + 0x020) /* Baud Rate Generator Register */
1251
#define US1_RTOR __REG32(USART1_BASE + 0x024) /* Receiver Timeout Register */
1252
#define US1_TTGR __REG32(USART1_BASE + 0x028) /* Transmitter Time-guard Register */
1253
#define US1_FIDI __REG32(USART1_BASE + 0x040) /* FI_DI_Ratio Register */
1254
#define US1_NER __REG32(USART1_BASE + 0x044) /* Number of Errors Register */
1255
#define US1_IF __REG32(USART1_BASE + 0x04C) /* IrDA Filter Register */
1257
#define US1_RPR __REG32(USART1_BASE + 0x100) /* Receiver Pointer Register */
1258
#define US1_RCR __REG32(USART1_BASE + 0x104) /* Receiver Counter Register */
1259
#define US1_TPR __REG32(USART1_BASE + 0x108) /* Transmitter Pointer Register */
1260
#define US1_TCR __REG32(USART1_BASE + 0x10C) /* Transmitter Counter Register */
1261
#define US1_RNPR __REG32(USART1_BASE + 0x110) /* Receiver Next Pointer Register */
1262
#define US1_RNCR __REG32(USART1_BASE + 0x114) /* Receiver Next Counter Register */
1263
#define US1_TNPR __REG32(USART1_BASE + 0x118) /* Transmitter Next Pointer Register */
1264
#define US1_TNCR __REG32(USART1_BASE + 0x11C) /* Transmitter Next Counter Register */
1265
#define US1_PTCR __REG32(USART1_BASE + 0x120) /* PDC Transfer Control Register */
1266
#define US1_PTSR __REG32(USART1_BASE + 0x124) /* PDC Transfer Status Register */
1269
#define USART2_BASE 0xFFFC8000
1270
#define US2_CR __REG32(USART2_BASE + 0x000) /* Control Register */
1271
#define US2_MR __REG32(USART2_BASE + 0x004) /* Mode Register */
1272
#define US2_IER __REG32(USART2_BASE + 0x008) /* Interrupt Enable Register */
1273
#define US2_IDR __REG32(USART2_BASE + 0x00C) /* Interrupt Disable Register */
1274
#define US2_IMR __REG32(USART2_BASE + 0x010) /* Interrupt Mask Register */
1275
#define US2_CSR __REG32(USART2_BASE + 0x014) /* Channel Status Register */
1276
#define US2_RHR __REG32(USART2_BASE + 0x018) /* Receive Holding Register */
1277
#define US2_THR __REG32(USART2_BASE + 0x01C) /* Transmit Holding Register */
1278
#define US2_BRGR __REG32(USART2_BASE + 0x020) /* Baud Rate Generator Register */
1279
#define US2_RTOR __REG32(USART2_BASE + 0x024) /* Receiver Timeout Register */
1280
#define US2_TTGR __REG32(USART2_BASE + 0x028) /* Transmitter Time-guard Register */
1281
#define US2_FIDI __REG32(USART2_BASE + 0x040) /* FI_DI_Ratio Register */
1282
#define US2_NER __REG32(USART2_BASE + 0x044) /* Number of Errors Register */
1283
#define US2_IF __REG32(USART2_BASE + 0x04C) /* IrDA Filter Register */
1285
#define US2_RPR __REG32(USART2_BASE + 0x100) /* Receiver Pointer Register */
1286
#define US2_RCR __REG32(USART2_BASE + 0x104) /* Receiver Counter Register */
1287
#define US2_TPR __REG32(USART2_BASE + 0x108) /* Transmitter Pointer Register */
1288
#define US2_TCR __REG32(USART2_BASE + 0x10C) /* Transmitter Counter Register */
1289
#define US2_RNPR __REG32(USART2_BASE + 0x110) /* Receiver Next Pointer Register */
1290
#define US2_RNCR __REG32(USART2_BASE + 0x114) /* Receiver Next Counter Register */
1291
#define US2_TNPR __REG32(USART2_BASE + 0x118) /* Transmitter Next Pointer Register */
1292
#define US2_TNCR __REG32(USART2_BASE + 0x11C) /* Transmitter Next Counter Register */
1293
#define US2_PTCR __REG32(USART2_BASE + 0x120) /* PDC Transfer Control Register */
1294
#define US2_PTSR __REG32(USART2_BASE + 0x124) /* PDC Transfer Status Register */
1297
/* US_CR : Control Register */
1299
#define US_RSTRX (1 << 2) /* Reset Receiver */
1300
#define US_RSTTX (1 << 3) /* Reset Transmitter */
1301
#define US_RXEN (1 << 4) /* Receiver Enable */
1302
#define US_RXDIS (1 << 5) /* Receiver Disable */
1303
#define US_TXEN (1 << 6) /* Transmitter Enable */
1304
#define US_TXDIS (1 << 7) /* Transmitter Disable */
1305
#define US_RSTSTA (1 << 8) /* Reset Status Bits */
1306
#define US_STTBRK (1 << 9) /* Start Break */
1307
#define US_STPBRK (1 << 10) /* Stop Break */
1308
#define US_STTTO (1 << 11) /* Start Time-out */
1309
#define US_SENDA (1 << 12) /* Send Address */
1310
#define US_RSTIT (1 << 13) /* Reset Iterations */
1311
#define US_RSTNACK (1 << 14) /* Reset Non Acknowledge */
1312
#define US_RETTO (1 << 15) /* Rearm Time-out */
1313
#define US_DTREN (1 << 16) /* Data Terminal Ready Enable */
1314
#define US_DTRDIS (1 << 17) /* Data Terminal Ready Disable */
1315
#define US_RTSEN (1 << 18) /* Request To Send Enable */
1316
#define US_RTSDIS (1 << 19) /* Request To Send Disable */
1319
/* US_MR : Mode Register */
1320
#define US_USMODE (0x0F << 0) /* USART Mode */
1321
#define US_USMODE_NORMAL (0x00 << 0)
1322
#define US_USMODE_RS485 (0x01 << 0)
1323
#define US_USMODE_HWHSH (0x02 << 0) /* Hardware Handshaking */
1324
#define US_USMODE_MODEM (0x03 << 0)
1325
#define US_USMODE_ISO7816_0 (0x04 << 0)
1326
#define US_USMODE_ISO7816_1 (0x06 << 0)
1327
#define US_USMODE_IRDA (0x08 << 0)
1328
#define US_USMODE_SWHSH (0x0C << 0) /* Software Handshaking */
1330
#define US_CLKS (0x03 << 4) /* Clock Selection */
1331
#define US_CLKS_CLOCK (0x00 << 4) /* Clock */
1332
#define US_CLKS_FDIV1 (0x01 << 4) /* Clock divided by 8 */
1333
#define US_CLKS_SLOW (0x02 << 4) /* Slow Clock */
1334
#define US_CLKS_EXT (0x03 << 4) /* External Clock */
1336
#define US_CHRL (0x03 << 6) /* Byte Length */
1337
#define US_CHRL_5 (0x00 << 6) /* 5 bits */
1338
#define US_CHRL_6 (0x01 << 6) /* 6 bits */
1339
#define US_CHRL_7 (0x02 << 6) /* 7 bits */
1340
#define US_CHRL_8 (0x03 << 6) /* 8 bits */
1342
#define US_SYNC (1 << 8) /* Synchronous Mode Enable */
1344
#define US_PAR (0x07 << 9) /* Parity Mode */
1345
#define US_PAR_EVEN (0x00 << 9) /* Even Parity */
1346
#define US_PAR_ODD (0x01 << 9) /* Odd Parity */
1347
#define US_PAR_SPACE (0x02 << 9) /* Space Parity to 0 */
1348
#define US_PAR_MARK (0x03 << 9) /* Marked Parity to 1 */
1349
#define US_PAR_NO (0x04 << 9) /* No Parity */
1350
#define US_PAR_MULTIDROP (0x06 << 9) /* Multi-drop Mode */
1352
#define US_NBSTOP (0x03 << 12) /* Stop Bit Number */
1353
#define US_NBSTOP_1 (0x00 << 12) /* 1 Stop Bit */
1354
#define US_NBSTOP_1_5 (0x01 << 12) /* 1.5 Stop Bits */
1355
#define US_NBSTOP_2 (0x02 << 12) /* 2 Stop Bits */
1357
#define US_CHMODE (0x03 << 14) /* Channel Mode */
1358
#define US_CHMODE_NORMAL (0x00 << 14) /* Normal Mode */
1359
#define US_CHMODE_AUTOMATIC_ECHO (0x01 << 14) /* Automatic Echo */
1360
#define US_CHMODE_LOCAL_LOOPBACK (0x02 << 14) /* Local Loopback */
1361
#define US_CHMODE_REMOTE_LOOPBACK (0x03 << 14) /* Remote Loopback */
1363
#define US_MSBF (1 << 16) /* Bit order: MSB First */
1364
#define US_MODE9 (1 << 17) /* 9 Bit Mode */
1365
#define US_CLKO (1 << 18) /* Clock Output Select */
1366
#define US_OVER (1 << 19) /* Over Sampling Mode */
1367
#define US_INACK (1 << 20) /* Inhibit Non Acknowledge */
1368
#define US_DSNACK (1 << 21) /* Disable Successive NACK */
1369
#define US_MAX_ITER (1 << 24) /* Number of Repetitions */
1370
#define US_FILTER (1 << 28) /* Receive Line Filter */
1371
#define US_MAN (1 << 29) /* Manchester Encoder/Decoder Enable */
1372
#define US_ONEBIT (1u << 31) /* Start Frame Delimiter Selector */
1374
/* Mode Register model */
1376
/* Standard Asynchronous Mode : 8 bits , 1 stop , no parity */
1377
#define US_ASYNC_MODE ( US_CHMODE_NORMAL + \
1383
/* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity */
1384
#define US_ASYNC_EXT_MODE ( US_CHMODE_NORMAL + \
1390
/* Standard Synchronous Mode : 8 bits , 1 stop , no parity */
1391
#define US_SYNC_MODE ( US_SYNC + \
1392
US_CHMODE_NORMAL + \
1398
/* SCK used Label */
1399
#define SCK_USED (US_CLKO | US_CLKS_EXT)
1401
/*---------------------------------------------------------------*/
1402
/* US_IER, US_IDR, US_IMR, US_CSR: Status and Interrupt Register */
1403
/*---------------------------------------------------------------*/
1405
#define US_RXRDY (1 << 0) /* Receiver Ready */
1406
#define US_TXRDY (1 << 1) /* Transmitter Ready */
1407
#define US_RXBRK (1 << 2) /* Receiver Break */
1408
#define US_ENDRX (1 << 3) /* End of Receiver PDC Transfer */
1409
#define US_ENDTX (1 << 4) /* End of Transmitter PDC Transfer */
1410
#define US_OVRE (1 << 5) /* Overrun Error */
1411
#define US_FRAME (1 << 6) /* Framing Error */
1412
#define US_PARE (1 << 7) /* Parity Error */
1413
#define US_TIMEOUT (1 << 8) /* Receiver Timeout */
1414
#define US_TXEMPTY (1 << 9) /* Transmitter Empty */
1415
#define US_ITERATION (1 << 10) /* Iteration */
1416
#define US_TXBUFFE (1 << 11) /* TX Buffer Empty */
1417
#define US_RXBUFF (1 << 12) /* RX Buffer Full */
1418
#define US_NACK (1 << 13) /* Non Acknowledge */
1419
#define US_RIIC (1 << 16) /* Ring Indicator Input Change */
1420
#define US_DSRIC (1 << 17) /* Data Set Ready Input Change */
1421
#define US_DCDIC (1 << 18) /* Data Carrier Detect Input Change */
1422
#define US_CTSIC (1 << 19) /* Clear To Send Input Change */
1423
#define US_MANE (1 << 20) /* Manchester Error */
1425
#define US_MASK_IRQ_TX (US_TXRDY | US_ENDTX | US_TXEMPTY)
1426
#define US_MASK_IRQ_RX (US_RXRDY | US_ENDRX | US_TIMEOUT)
1427
#define US_MASK_IRQ_ERROR (US_PARE | US_FRAME | US_OVRE | US_RXBRK)
1432
/*---------------------------------------*/
1433
/* Analog to Digital Converter Registers */
1434
/*---------------------------------------*/
1436
#define ADC0_BASE 0xFFFD8000
1437
#define PDC_ADC0_BASE (ADC0_BASE + 0x100)
1439
#define ADC0_CR __REG32(ADC0_BASE + 0x000) /* Control Register */
1440
#define ADC0_MR __REG32(ADC0_BASE + 0x004) /* Mode Register */
1441
#define ADC0_CHER __REG32(ADC0_BASE + 0x010) /* Channel Enable Register */
1442
#define ADC0_CHDR __REG32(ADC0_BASE + 0x014) /* Channel Disable Register */
1443
#define ADC0_CHSR __REG32(ADC0_BASE + 0x018) /* Channel Status Register */
1444
#define ADC0_SR __REG32(ADC0_BASE + 0x01C) /* Status Register */
1445
#define ADC0_LCDR __REG32(ADC0_BASE + 0x020) /* Last Converted Data Register */
1446
#define ADC0_IER __REG32(ADC0_BASE + 0x024) /* Interrupt Enable Register */
1447
#define ADC0_IDR __REG32(ADC0_BASE + 0x028) /* Interrupt Disable Register */
1448
#define ADC0_IMR __REG32(ADC0_BASE + 0x02C) /* Interrupt Mask Register */
1449
#define ADC0_CDR0 __REG32(ADC0_BASE + 0x030) /* Channel Data Register 0 */
1450
#define ADC0_CDR1 __REG32(ADC0_BASE + 0x034) /* Channel Data Register 1 */
1451
#define ADC0_CDR2 __REG32(ADC0_BASE + 0x038) /* Channel Data Register 2 */
1452
#define ADC0_CDR3 __REG32(ADC0_BASE + 0x03C) /* Channel Data Register 3 */
1453
#define ADC0_CDR4 __REG32(ADC0_BASE + 0x040) /* Channel Data Register 4 */
1454
#define ADC0_CDR5 __REG32(ADC0_BASE + 0x044) /* Channel Data Register 5 */
1455
#define ADC0_CDR6 __REG32(ADC0_BASE + 0x048) /* Channel Data Register 6 */
1456
#define ADC0_CDR7 __REG32(ADC0_BASE + 0x04C) /* Channel Data Register 7 */
1457
#define ADC0_RPR __REG32(ADC0_BASE + 0x100) /* Receive Pointer Register */
1458
#define ADC0_RCR __REG32(ADC0_BASE + 0x104) /* Receive Counter Register */
1459
#define ADC0_TPR __REG32(ADC0_BASE + 0x108) /* Transmit Pointer Register */
1460
#define ADC0_TCR __REG32(ADC0_BASE + 0x10C) /* Transmit Counter Register */
1461
#define ADC0_RNPR __REG32(ADC0_BASE + 0x110) /* Receive Next Pointer Register */
1462
#define ADC0_RNCR __REG32(ADC0_BASE + 0x114) /* Receive Next Counter Register */
1463
#define ADC0_TNPR __REG32(ADC0_BASE + 0x118) /* Transmit Next Pointer Register */
1464
#define ADC0_TNCR __REG32(ADC0_BASE + 0x11C) /* Transmit Next Counter Register */
1465
#define ADC0_PTCR __REG32(ADC0_BASE + 0x120) /* PDC Transfer Control Register */
1466
#define ADC0_PTSR __REG32(ADC0_BASE + 0x124) /* PDC Transfer Status Register */
1469
#define ADC1_BASE 0xFFFDC000
1470
#define PDC_ADC1_BASE (ADC1_BASE + 0x100)
1472
#define ADC1_CR __REG32(ADC1_BASE + 0x000) /* Control Register */
1473
#define ADC1_MR __REG32(ADC1_BASE + 0x004) /* Mode Register */
1474
#define ADC1_CHER __REG32(ADC1_BASE + 0x010) /* Channel Enable Register */
1475
#define ADC1_CHDR __REG32(ADC1_BASE + 0x014) /* Channel Disable Register */
1476
#define ADC1_CHSR __REG32(ADC1_BASE + 0x018) /* Channel Status Register */
1477
#define ADC1_SR __REG32(ADC1_BASE + 0x01C) /* Status Register */
1478
#define ADC1_LCDR __REG32(ADC1_BASE + 0x020) /* Last Converted Data Register */
1479
#define ADC1_IER __REG32(ADC1_BASE + 0x024) /* Interrupt Enable Register */
1480
#define ADC1_IDR __REG32(ADC1_BASE + 0x028) /* Interrupt Disable Register */
1481
#define ADC1_IMR __REG32(ADC1_BASE + 0x02C) /* Interrupt Mask Register */
1482
#define ADC1_CDR0 __REG32(ADC1_BASE + 0x030) /* Channel Data Register 0 */
1483
#define ADC1_CDR1 __REG32(ADC1_BASE + 0x034) /* Channel Data Register 1 */
1484
#define ADC1_CDR2 __REG32(ADC1_BASE + 0x038) /* Channel Data Register 2 */
1485
#define ADC1_CDR3 __REG32(ADC1_BASE + 0x03C) /* Channel Data Register 3 */
1486
#define ADC1_CDR4 __REG32(ADC1_BASE + 0x040) /* Channel Data Register 4 */
1487
#define ADC1_CDR5 __REG32(ADC1_BASE + 0x044) /* Channel Data Register 5 */
1488
#define ADC1_CDR6 __REG32(ADC1_BASE + 0x048) /* Channel Data Register 6 */
1489
#define ADC1_CDR7 __REG32(ADC1_BASE + 0x04C) /* Channel Data Register 7 */
1490
#define ADC1_RPR __REG32(ADC1_BASE + 0x100) /* Receive Pointer Register */
1491
#define ADC1_RCR __REG32(ADC1_BASE + 0x104) /* Receive Counter Register */
1492
#define ADC1_TPR __REG32(ADC1_BASE + 0x108) /* Transmit Pointer Register */
1493
#define ADC1_TCR __REG32(ADC1_BASE + 0x10C) /* Transmit Counter Register */
1494
#define ADC1_RNPR __REG32(ADC1_BASE + 0x110) /* Receive Next Pointer Register */
1495
#define ADC1_RNCR __REG32(ADC1_BASE + 0x114) /* Receive Next Counter Register */
1496
#define ADC1_TNPR __REG32(ADC1_BASE + 0x118) /* Transmit Next Pointer Register */
1497
#define ADC1_TNCR __REG32(ADC1_BASE + 0x11C) /* Transmit Next Counter Register */
1498
#define ADC1_PTCR __REG32(ADC1_BASE + 0x120) /* PDC Transfer Control Register */
1499
#define ADC1_PTSR __REG32(ADC1_BASE + 0x124) /* PDC Transfer Status Register */
1502
/* ADC_CR: Control Register Bits Definition */
1503
#define ADC_SWRST (1 << 0) /* ADC Software Reset */
1504
#define ADC_START (1 << 1) /* ADC Start Conversion */
1506
/* ADC_MR: Mode Register Bits Definition */
1507
#define ADC_TRGEN_DIS (0 << 0) /* Trigger Disable */
1508
#define ADC_TRGEN_EN (1 << 0) /* Trigger Enable */
1509
#define ADC_TTRGSEL (0x07 << 1) /* Trigger Selection */
1510
#define ADC_TRGSEL_TIOA0 (0x0 << 1) /* TIOA0 Trigger Selection */
1511
#define ADC_TRGSEL_TIOA1 (0x1 << 1) /* TIOA1 Trigger Selection */
1512
#define ADC_TRGSEL_TIOA2 (0x2 << 1) /* TIOA2 Trigger Selection */
1513
#define ADC_TRGSEL_TIOA3 (0x3 << 1) /* TIOA3 Trigger Selection */
1514
#define ADC_TRGSEL_TIOA4 (0x4 << 1) /* TIOA4 Trigger Selection */
1515
#define ADC_TRGSEL_TIOA5 (0x5 << 1) /* TIOA5 Trigger Selection */
1516
#define ADC_TRGSEL_EXT (0x6 << 1) /* External Trigger Selection */
1517
#define ADC_LOWRES (1 << 4) /* Resolution */
1518
#define ADC_LOWRES_10_BIT (0 << 4) /* 10 bits ADC Resolution */
1519
#define ADC_LOWRES_8_BIT (1 << 4) /* 8 bits ADC Resolution */
1520
#define ADC_SLEEP (1 << 5) /* Sleep Mode */
1521
#define ADC_SLEEP_NORMAL_MODE (0 << 5) /* Normal Mode */
1522
#define ADC_SLEEP_MODE (1 << 5) /* Sleep Mode */
1523
#define ADC_PRESCAL (0x3F << 8) /* Prescaler rate selection */
1524
#define ADC_B_PRESCAL 8 /* Prescaler bit shift */
1525
#define ADC_STARTUP (0x1F << 16) /* Startup Time */
1526
#define ADC_B_STARTUP 16 /* Startup Time bit shift */
1527
#define ADC_SHTIM (0x0F << 24) /* Sample & Hold Time */
1528
#define ADC_B_SHTIM 24 /* Sample & Hold Time bit shift */
1530
/* ADC_CHER,ADC_CHDR,ADC_CHSR: Channel Enable, Disable and Status Registers */
1531
#define ADC_CH0 (1 << 0) /* Channel 0 */
1532
#define ADC_CH1 (1 << 1) /* Channel 1 */
1533
#define ADC_CH2 (1 << 2) /* Channel 2 */
1534
#define ADC_CH3 (1 << 3) /* Channel 3 */
1535
#define ADC_CH4 (1 << 4) /* Channel 4 */
1536
#define ADC_CH5 (1 << 5) /* Channel 5 */
1537
#define ADC_CH6 (1 << 6) /* Channel 6 */
1538
#define ADC_CH7 (1 << 7) /* Channel 7 */
1540
/* ADC_SR,ADC_IER,ADC_IDR,ADC_IMR: Status, Enable, Disable, Mask Registers */
1541
#define ADC_EOC0 (1 << 0) /* End of Conversion Channel 0 */
1542
#define ADC_EOC1 (1 << 1) /* End of Conversion Channel 1 */
1543
#define ADC_EOC2 (1 << 2) /* End of Conversion Channel 2 */
1544
#define ADC_EOC3 (1 << 3) /* End of Conversion Channel 3 */
1545
#define ADC_EOC4 (1 << 4) /* End of Conversion Channel 4 */
1546
#define ADC_EOC5 (1 << 5) /* End of Conversion Channel 5 */
1547
#define ADC_EOC6 (1 << 6) /* End of Conversion Channel 6 */
1548
#define ADC_EOC7 (1 << 7) /* End of Conversion Channel 7 */
1549
#define ADC_OVRE0 (1 << 8) /* Overrun Error Channel 0 */
1550
#define ADC_OVRE1 (1 << 9) /* Overrun Error Channel 1 */
1551
#define ADC_OVRE2 (1 << 10) /* Overrun Error Channel 2 */
1552
#define ADC_OVRE3 (1 << 11) /* Overrun Error Channel 3 */
1553
#define ADC_OVRE4 (1 << 12) /* Overrun Error Channel 4 */
1554
#define ADC_OVRE5 (1 << 13) /* Overrun Error Channel 5 */
1555
#define ADC_OVRE6 (1 << 14) /* Overrun Error Channel 6 */
1556
#define ADC_OVRE7 (1 << 15) /* Overrun Error Channel 7 */
1557
#define ADC_DRDY (1 << 16) /* Data Ready */
1558
#define ADC_GOVRE (1 << 17) /* General Overrun Error */
1559
#define ADC_ENDRX (1 << 18) /* End of Receiver Transfer */
1560
#define ADC_RXBUFF (1 << 19) /* RXBUFF Interrupt */
1562
/* ADC_CDRx, ADC_LCDR: Convert Data Register */
1563
#define ADC_DATA_10BITS 0x3FF
1564
#define ADC_DATA_8BITS 0x0FF
1567
/*---------------------------------------*/
1568
/* Serial Peripheral Interface Registers */
1569
/*---------------------------------------*/
1571
#define SPI0_BASE 0xFFFE0000
1572
#define PDC_SPI0_BASE (SPI0_BASE + 0x100)
1574
#define SPI0_CR __REG32(SPI0_BASE + 0x000) /* Control Register */
1575
#define SPI0_MR __REG32(SPI0_BASE + 0x004) /* Mode Register */
1576
#define SPI0_RDR __REG32(SPI0_BASE + 0x008) /* Receive Data Register */
1577
#define SPI0_TDR __REG32(SPI0_BASE + 0x00C) /* Transmit Data Register */
1578
#define SPI0_SR __REG32(SPI0_BASE + 0x010) /* Status Register */
1579
#define SPI0_IER __REG32(SPI0_BASE + 0x014) /* Interrupt Enable Register */
1580
#define SPI0_IDR __REG32(SPI0_BASE + 0x018) /* Interrupt Disable Register */
1581
#define SPI0_IMR __REG32(SPI0_BASE + 0x01C) /* Interrupt Mask Register */
1582
#define SPI0_CSR0 __REG32(SPI0_BASE + 0x030) /* Chip Select Register 0 */
1583
#define SPI0_CSR1 __REG32(SPI0_BASE + 0x034) /* Chip Select Register 1 */
1584
#define SPI0_CSR2 __REG32(SPI0_BASE + 0x038) /* Chip Select Register 2 */
1585
#define SPI0_CSR3 __REG32(SPI0_BASE + 0x03C) /* Chip Select Register 3 */
1587
#define SPI0_RPR __REG32(SPI0_BASE + 0x100) /* Receive Pointer Register */
1588
#define SPI0_RCR __REG32(SPI0_BASE + 0x104) /* Receive Counter Register */
1589
#define SPI0_TPR __REG32(SPI0_BASE + 0x108) /* Transmit Pointer Register */
1590
#define SPI0_TCR __REG32(SPI0_BASE + 0x10C) /* Transmit Counter Register */
1591
#define SPI0_RNPR __REG32(SPI0_BASE + 0x110) /* Receive Next Pointer Register */
1592
#define SPI0_RNCR __REG32(SPI0_BASE + 0x114) /* Receive Next Counter Register */
1593
#define SPI0_TNPR __REG32(SPI0_BASE + 0x118) /* Transmit Next Pointer Register */
1594
#define SPI0_TNCR __REG32(SPI0_BASE + 0x11C) /* Transmit Next Counter Register */
1595
#define SPI0_PTCR __REG32(SPI0_BASE + 0x120) /* PDC Transfer Control Register */
1596
#define SPI0_PTSR __REG32(SPI0_BASE + 0x124) /* PDC Transfer Status Register */
1599
#define SPI1_BASE 0xFFFE4000
1600
#define PDC_SPI1_BASE (SPI1_BASE + 0x100)
1602
#define SPI1_CR __REG32(SPI1_BASE + 0x000) /* Control Register */
1603
#define SPI1_MR __REG32(SPI1_BASE + 0x004) /* Mode Register */
1604
#define SPI1_RDR __REG32(SPI1_BASE + 0x008) /* Receive Data Register */
1605
#define SPI1_TDR __REG32(SPI1_BASE + 0x00C) /* Transmit Data Register */
1606
#define SPI1_SR __REG32(SPI1_BASE + 0x010) /* Status Register */
1607
#define SPI1_IER __REG32(SPI1_BASE + 0x014) /* Interrupt Enable Register */
1608
#define SPI1_IDR __REG32(SPI1_BASE + 0x018) /* Interrupt Disable Register */
1609
#define SPI1_IMR __REG32(SPI1_BASE + 0x01C) /* Interrupt Mask Register */
1610
#define SPI1_CSR0 __REG32(SPI1_BASE + 0x030) /* Chip Select Register 0 */
1611
#define SPI1_CSR1 __REG32(SPI1_BASE + 0x034) /* Chip Select Register 1 */
1612
#define SPI1_CSR2 __REG32(SPI1_BASE + 0x038) /* Chip Select Register 2 */
1613
#define SPI1_CSR3 __REG32(SPI1_BASE + 0x03C) /* Chip Select Register 3 */
1615
#define SPI1_RPR __REG32(SPI1_BASE + 0x100) /* Receive Pointer Register */
1616
#define SPI1_RCR __REG32(SPI1_BASE + 0x104) /* Receive Counter Register */
1617
#define SPI1_TPR __REG32(SPI1_BASE + 0x108) /* Transmit Pointer Register */
1618
#define SPI1_TCR __REG32(SPI1_BASE + 0x10C) /* Transmit Counter Register */
1619
#define SPI1_RNPR __REG32(SPI1_BASE + 0x110) /* Receive Next Pointer Register */
1620
#define SPI1_RNCR __REG32(SPI1_BASE + 0x114) /* Receive Next Counter Register */
1621
#define SPI1_TNPR __REG32(SPI1_BASE + 0x118) /* Transmit Next Pointer Register */
1622
#define SPI1_TNCR __REG32(SPI1_BASE + 0x11C) /* Transmit Next Counter Register */
1623
#define SPI1_PTCR __REG32(SPI1_BASE + 0x120) /* PDC Transfer Control Register */
1624
#define SPI1_PTSR __REG32(SPI1_BASE + 0x124) /* PDC Transfer Status Register */
1627
/* SPI_CR: Control Register */
1628
#define SPI_CR_SPIEN (1 << 0) /* SPI Enable */
1629
#define SPI_CR_SPIDIS (1 << 1) /* SPI Disable */
1630
#define SPI_CR_SWRST (1 << 7) /* SPI Software Reset */
1631
#define SPI_CR_LASTXFER (1 << 24) /* SPI Last Transfer */
1633
/* SPI_MR: Mode Register */
1634
#define SPI_MR_MSTR (1 << 0) /* Master/Slave Mode (0 = Slave, 1 = Master) */
1635
#define SPI_MR_PS (1 << 1) /* Peripheral Select (0 = Fixed, 1 = Variable) */
1636
#define SPI_MR_PCSDEV (1 << 2) /* Chip Select Decode (0 = direct, 1 = decoded) */
1637
#define SPI_MR_MODFDIS (1 << 4) /* Mode Fault Detection (0 = enabled, 1 = disabled) */
1638
#define SPI_MR_LLB (1 << 7) /* Local Loopback Enable */
1639
#define SPI_MR_PCS_SHFT 16
1640
#define SPI_MR_PCS_MSK (0x0F << 16) /* Peripheral Chip Select (for Fixed PS only) */
1641
#define SPI_MR_DLYBCS_SHFT 24
1642
#define SPI_MR_DLYBCS_MSK (0xFFu << 24) /* Delay Between Chip Selects */
1644
/* SPI_RDR: Receive Data Register */
1645
#define SPI_RDR_RD_MSK (0xFFFF << 0) /* Receive Data */
1646
#define SPI_RDR_PCS_MSK (0x0F << 16) /* Peripheral Chip Select (NPCS pin) */
1648
/* SPI_TDR: Transmit Data Register */
1649
#define SPI_TDR_TD_MSK (0xFFFF << 0) /* Transmit Data */
1650
#define SPI_TDR_PCS_MSK (0x0F << 16) /* Peripheral Chip Select (for Variable PS only) */
1651
#define SPI_TDR_LASTXFER (1 << 24) /* Last Transfer (for Variable PS only) */
1653
/* SPI_SR: Status Register */
1654
#define SPI_SR_RDRF (1 << 0) /* Receive Data Register Full */
1655
#define SPI_SR_TDRE (1 << 1) /* Transmit Data Register Empty */
1656
#define SPI_SR_MODF (1 << 2) /* Mode Fault Error */
1657
#define SPI_SR_OVRES (1 << 3) /* Overrun Error Status */
1658
#define SPI_SR_ENDRX (1 << 4) /* End of RX buffer */
1659
#define SPI_SR_ENDTX (1 << 5) /* End of TX buffer */
1660
#define SPI_SR_RXBUFF (1 << 6) /* RX Buffer Full */
1661
#define SPI_SR_TXBUFE (1 << 7) /* TX Buffer Empty */
1662
#define SPI_SR_NSSR (1 << 8) /* NSS Rising */
1663
#define SPI_SR_TXEMPTY (1 << 9) /* Transmission Registers Empty */
1664
#define SPI_SR_SPIENS (1 << 16) /* SPI Enable Status */
1666
/* SPI_IER, SPI_IDR, SPI_IMR: Interrupt xxx Register */
1667
#define SPI_IR_RDRF (1 << 0) /* Receive Data Register Full */
1668
#define SPI_IR_TDRE (1 << 1) /* Transmit Data Register Empty */
1669
#define SPI_IR_MODF (1 << 2) /* Mode Fault Error */
1670
#define SPI_IR_OVRES (1 << 3) /* Overrun Error Status */
1671
#define SPI_IR_ENDRX (1 << 4) /* End of RX buffer */
1672
#define SPI_IR_ENDTX (1 << 5) /* End of TX buffer */
1673
#define SPI_IR_RXBUFF (1 << 6) /* RX Buffer Full */
1674
#define SPI_IR_TXBUFE (1 << 7) /* TX Buffer Empty */
1675
#define SPI_IR_NSSR (1 << 8) /* NSS Rising */
1676
#define SPI_IR_TXEMPTY (1 << 9) /* Transmission Registers Empty */
1678
/* SPI_CSRx: SPI Chip Select Registers */
1679
#define SPI_CSR_CPOL (1 << 0) /* Clock Polarity */
1680
#define SPI_CSR_NCPHA (1 << 1) /* Clock Phase */
1681
#define SPI_CSR_CSAAT (1 << 3) /* Chip Select Active After Transfer */
1682
#define SPI_CSR_BITS_SHFT 4
1683
#define SPI_CSR_BITS_MSK (0x0F << 4) /* Bits Per Transfer */
1684
#define SPI_CSR_BITS_8 (0x00 << 4)
1685
#define SPI_CSR_BITS_9 (0x01 << 4)
1686
#define SPI_CSR_BITS_10 (0x02 << 4)
1687
#define SPI_CSR_BITS_11 (0x03 << 4)
1688
#define SPI_CSR_BITS_12 (0x04 << 4)
1689
#define SPI_CSR_BITS_13 (0x05 << 4)
1690
#define SPI_CSR_BITS_14 (0x06 << 4)
1691
#define SPI_CSR_BITS_15 (0x07 << 4)
1692
#define SPI_CSR_BITS_16 (0x08 << 4)
1693
#define SPI_CSR_SCBR_SHFT 8
1694
#define SPI_CSR_SCBR_MSK (0xFF << 8) /* Serial Clock Baud Rate */
1695
#define SPI_CSR_DLYBS_SHFT 16
1696
#define SPI_CSR_DLYBS_MSK (0xFF << 16) /* Delay Before SPCK */
1697
#define SPI_CSR_DLYBCT_SHFT 24
1698
#define SPI_CSR_DLYBCT_MSK (0xFFu << 24) /* Delay Between Consecutive Transfers */
1700
/* SPI_PTCR: PDC Transfer Control Register */
1701
#define SPI_PTCR_RXTEN (1 << 0) /* Receiver Transfer Enable */
1702
#define SPI_PTCR_RXTDIS (1 << 1) /* Receiver Transfer Disable */
1703
#define SPI_PTCR_TXTEN (1 << 8) /* Transmitter Transfer Enable */
1704
#define SPI_PTCR_TXTDIS (1 << 9) /* Transmitter Transfer Disable */
1706
/* SPI_PTSR: PDC Transfer Status Register */
1707
#define SPI_PTSR_RXTEN (1 << 0) /* Receiver Transfer Enable */
1708
#define SPI_PTSR_TXTEN (1 << 8) /* Transmitter Transfer Enable */
1711
/*-------------------------------*/
1712
/* Synchronous Serial Controller */
1713
/*-------------------------------*/
1715
#define SSC0_BASE 0xFFFD0000
1716
#define PDC_SSC0_BASE (SSC0_BASE + 0x100)
1718
#define SSC0_CR __REG32(SSC0_BASE + 0x000) /* Control Register */
1719
#define SSC0_CMR __REG32(SSC0_BASE + 0x004) /* Clock Mode Register */
1720
#define SSC0_RCMR __REG32(SSC0_BASE + 0x010) /* Receive Clock Mode Register */
1721
#define SSC0_RFMR __REG32(SSC0_BASE + 0x014) /* Receive Frame Mode Register */
1722
#define SSC0_TCMR __REG32(SSC0_BASE + 0x018) /* Transmit Clock Mode Register */
1723
#define SSC0_TFMR __REG32(SSC0_BASE + 0x01C) /* Transmit Frame Mode Register */
1724
#define SSC0_RHR __REG32(SSC0_BASE + 0x020) /* Receive Holding Register */
1725
#define SSC0_THR __REG32(SSC0_BASE + 0x024) /* Transmit Holding Register */
1726
#define SSC0_RSHR __REG32(SSC0_BASE + 0x030) /* Receive Sync Holding Register */
1727
#define SSC0_TSHR __REG32(SSC0_BASE + 0x034) /* Transmit Sync Holding Register */
1728
#define SSC0_RC0R __REG32(SSC0_BASE + 0x038) /* Receive Compare 0 Register */
1729
#define SSC0_RC1R __REG32(SSC0_BASE + 0x03C) /* Receive Compare 1 Register */
1730
#define SSC0_SR __REG32(SSC0_BASE + 0x040) /* Status Register */
1731
#define SSC0_IER __REG32(SSC0_BASE + 0x044) /* Interrupt Enable Register */
1732
#define SSC0_IDR __REG32(SSC0_BASE + 0x048) /* Interrupt Disable Register */
1733
#define SSC0_IMR __REG32(SSC0_BASE + 0x04C) /* Interrupt Mask Register */
1734
#define SSC0_RPR __REG32(SSC0_BASE + 0x100) /* Receive Pointer Register */
1735
#define SSC0_RCR __REG32(SSC0_BASE + 0x104) /* Receive Counter Register */
1736
#define SSC0_TPR __REG32(SSC0_BASE + 0x108) /* Transmit Pointer Register */
1737
#define SSC0_TCR __REG32(SSC0_BASE + 0x10C) /* Transmit Counter Register */
1738
#define SSC0_RNPR __REG32(SSC0_BASE + 0x110) /* Receive Next Pointer Register */
1739
#define SSC0_RNCR __REG32(SSC0_BASE + 0x114) /* Receive Next Counter Register */
1740
#define SSC0_TNPR __REG32(SSC0_BASE + 0x118) /* Transmit Next Pointer Register */
1741
#define SSC0_TNCR __REG32(SSC0_BASE + 0x11C) /* Transmit Next Counter Register */
1742
#define SSC0_PTCR __REG32(SSC0_BASE + 0x120) /* PDC Transfer Control Register */
1743
#define SSC0_PTSR __REG32(SSC0_BASE + 0x124) /* PDC Transfer Status Register */
1746
#define SSC1_BASE 0xFFFD4000
1747
#define PDC_SSC1_BASE (SSC1_BASE + 0x100)
1749
#define SSC1_CR __REG32(SSC1_BASE + 0x000) /* Control Register */
1750
#define SSC1_CMR __REG32(SSC1_BASE + 0x004) /* Clock Mode Register */
1751
#define SSC1_RCMR __REG32(SSC1_BASE + 0x010) /* Receive Clock Mode Register */
1752
#define SSC1_RFMR __REG32(SSC1_BASE + 0x014) /* Receive Frame Mode Register */
1753
#define SSC1_TCMR __REG32(SSC1_BASE + 0x018) /* Transmit Clock Mode Register */
1754
#define SSC1_TFMR __REG32(SSC1_BASE + 0x01C) /* Transmit Frame Mode Register */
1755
#define SSC1_RHR __REG32(SSC1_BASE + 0x020) /* Receive Holding Register */
1756
#define SSC1_THR __REG32(SSC1_BASE + 0x024) /* Transmit Holding Register */
1757
#define SSC1_RSHR __REG32(SSC1_BASE + 0x030) /* Receive Sync Holding Register */
1758
#define SSC1_TSHR __REG32(SSC1_BASE + 0x034) /* Transmit Sync Holding Register */
1759
#define SSC1_RC0R __REG32(SSC1_BASE + 0x038) /* Receive Compare 0 Register */
1760
#define SSC1_RC1R __REG32(SSC1_BASE + 0x03C) /* Receive Compare 1 Register */
1761
#define SSC1_SR __REG32(SSC1_BASE + 0x040) /* Status Register */
1762
#define SSC1_IER __REG32(SSC1_BASE + 0x044) /* Interrupt Enable Register */
1763
#define SSC1_IDR __REG32(SSC1_BASE + 0x048) /* Interrupt Disable Register */
1764
#define SSC1_IMR __REG32(SSC1_BASE + 0x04C) /* Interrupt Mask Register */
1765
#define SSC1_RPR __REG32(SSC1_BASE + 0x100) /* Receive Pointer Register */
1766
#define SSC1_RCR __REG32(SSC1_BASE + 0x104) /* Receive Counter Register */
1767
#define SSC1_TPR __REG32(SSC1_BASE + 0x108) /* Transmit Pointer Register */
1768
#define SSC1_TCR __REG32(SSC1_BASE + 0x10C) /* Transmit Counter Register */
1769
#define SSC1_RNPR __REG32(SSC1_BASE + 0x110) /* Receive Next Pointer Register */
1770
#define SSC1_RNCR __REG32(SSC1_BASE + 0x114) /* Receive Next Counter Register */
1771
#define SSC1_TNPR __REG32(SSC1_BASE + 0x118) /* Transmit Next Pointer Register */
1772
#define SSC1_TNCR __REG32(SSC1_BASE + 0x11C) /* Transmit Next Counter Register */
1773
#define SSC1_PTCR __REG32(SSC1_BASE + 0x120) /* PDC Transfer Control Register */
1774
#define SSC1_PTSR __REG32(SSC1_BASE + 0x124) /* PDC Transfer Status Register */
1776
/* SSC_CR: SSC Control Register */
1777
#define SSC_CR_RXEN (1 << 0) /* Receive Enable */
1778
#define SSC_CR_RXDIS (1 << 1) /* Receive Disable */
1779
#define SSC_CR_TXEN (1 << 8) /* Transmit Enable */
1780
#define SSC_CR_TXDIS (1 << 9) /* Transmit Disable */
1781
#define SSC_CR_SWRST (1 << 15) /* Software Reset */
1783
/* SSC_CMR: SSC Clock Mode Register */
1784
#define SSC_CMR_DIV (0xFFF << 0) /* Clock Divider */
1786
/* SSC_RCMR: SSC Receive Clock Mode Register */
1787
#define SSC_RCMR_CKS (0x03 << 0) /* Receive Clock Selection */
1788
#define SSC_RCMR_CKS_DIVC (0 << 0) /* Divided Clock */
1789
#define SSC_RCMR_CKS_TK (1 << 0) /* TK Clock signal */
1790
#define SSC_RCMR_CKS_RK (2 << 0) /* RK pin */
1791
#define SSC_RCMR_CKO (0x07 << 2) /* Receive Clock Output Mode Selection */
1792
#define SSC_RCMR_CKO_NONE (0 << 2) /* None (RK pin input-only) */
1793
#define SSC_RCMR_CKO_CONT (1 << 2) /* Continuous Receive Clock */
1794
#define SSC_RCMR_CKO_TRAN (2 << 2) /* Receive Clock only during data transfers */
1795
#define SSC_RCMR_CKI (1 << 5) /* Receive Clock Inversion */
1796
#define SSC_RCMR_CKG (0x03 << 6) /* Receive Clock Gating */
1797
#define SSC_RCMR_CKG_NONE (0 << 6) /* None, continuous clock */
1798
#define SSC_RCMR_CKG_RFL (1 << 6) /* Receive Clock enabled only if RF Low */
1799
#define SSC_RCMR_CKG_RFH (2 << 6) /* Receive Clock enabled only if RF High */
1800
#define SSC_RCMR_START (0x0F << 8) /* Receive Start Selection */
1801
#define SSC_RCMR_START_CONT (0 << 8) /* Continuous, as soon as receiver is enabled */
1802
#define SSC_RCMR_START_TS (1 << 8) /* Transmit start */
1803
#define SSC_RCMR_START_LL (2 << 8) /* Low Level on RF signal */
1804
#define SSC_RCMR_START_HL (3 << 8) /* High Level on RF signal */
1805
#define SSC_RCMR_START_FE (4 << 8) /* Falling Edge on RF signal */
1806
#define SSC_RCMR_START_RE (5 << 8) /* Rising Edge on RF signal */
1807
#define SSC_RCMR_START_AL (6 << 8) /* Any Level change on RF signal */
1808
#define SSC_RCMR_START_AE (7 << 8) /* Any Edge on RF signal */
1809
#define SSC_RCMR_START_CMP0 (8 << 8) /* Compare 0 */
1810
#define SSC_RCMR_STOP (1 << 12) /* Receive Stop Selection */
1811
#define SSC_RCMR_STDDLY (0xFF << 16) /* Receive Start Delay */
1812
#define SSC_RCMR_STDDLY_SHFT 16 /* bit position of field STDDLY */
1813
#define SSC_RCMR_PERIOD (0xFFu << 24) /* Receive Period Divider Selection */
1814
#define SSC_RCMR_PERIOD_SHFT 24 /* bit position of field PERIOD */
1816
/* SSC_RFMR: SSC Receive Frame Mode Register */
1817
#define SSC_RFMR_DATLEN (0x1F << 0) /* Data Length */
1818
#define SSC_RFMR_LOOP (1 << 5) /* Loop Mode (0=normal) */
1819
#define SSC_RFMR_MSBF (1 << 7) /* Most Significant Bit First */
1820
#define SSC_RFMR_DATNB (0x0F << 8) /* Data Number per Frame */
1821
#define SSC_RFMR_FSLEN (0x0F << 16) /* Receive Frame Sync Length */
1822
#define SSC_RFMR_FSOS (0x07 << 20) /* Receive Frame Sync Output Selection */
1823
#define SSC_RFMR_FSEDGE (1 << 24) /* Frame Sync Edge Detection */
1825
/* SSC_TCMR: SSC Transmit Clock Mode Register */
1826
#define SSC_TCMR_CKS (0x03 << 0) /* Transmit Clock Selection */
1827
#define SSC_TCMR_CKS_DIVC (0 << 0) /* Divided Clock */
1828
#define SSC_TCMR_CKS_RK (1 << 0) /* RK Clock signal */
1829
#define SSC_TCMR_CKS_TK (2 << 0) /* TK pin */
1830
#define SSC_TCMR_CKO (0x07 << 2) /* Transmit Clock Output Mode Selection */
1831
#define SSC_TCMR_CKO_NONE (0 << 2) /* None (TK pin input-only) */
1832
#define SSC_TCMR_CKO_CONT (1 << 2) /* Continuous Transmit Clock */
1833
#define SSC_TCMR_CKO_TRAN (2 << 2) /* Transmit Clock only during data transfers */
1834
#define SSC_TCMR_CKI (1 << 5) /* Transmit Clock Inversion */
1835
#define SSC_TCMR_CKG (0x03 << 6) /* Transmit Clock Gating */
1836
#define SSC_TCMR_CKG_NONE (0 << 6) /* None, continuous clock */
1837
#define SSC_TCMR_CKG_TFL (1 << 6) /* Transmit Clock enabled only if TF Low */
1838
#define SSC_TCMR_CKG_TFH (2 << 6) /* Transmit Clock enabled only if TF High */
1839
#define SSC_TCMR_START (0x0F << 8) /* Transmit Start Selection */
1840
#define SSC_TCMR_START_CONT (0 << 8) /* Continuous, as soon as SSC_THR is written */
1841
#define SSC_TCMR_START_RS (1 << 8) /* Receive start */
1842
#define SSC_TCMR_START_LL (2 << 8) /* Low Level on TF signal */
1843
#define SSC_TCMR_START_HL (3 << 8) /* High Level on TF signal */
1844
#define SSC_TCMR_START_FE (4 << 8) /* Falling Edge on TF signal */
1845
#define SSC_TCMR_START_RE (5 << 8) /* Rising Edge on TF signal */
1846
#define SSC_TCMR_START_AL (6 << 8) /* Any Level change on TF signal */
1847
#define SSC_TCMR_START_AE (7 << 8) /* Any Edge on TF signal */
1848
#define SSC_TCMR_STDDLY (0xFF << 16) /* Transmit Start Delay */
1849
#define SSC_TCMR_STDDLY_SHFT 16 /* bit position of field STDDLY */
1850
#define SSC_TCMR_PERIOD (0xFFu << 24) /* Transmit Period Divider Selection */
1851
#define SSC_TCMR_PERIOD_SHFT 24 /* bit position of field PERIOD */
1853
/* SSC_TFMR: SSC Transmit Frame Mode Register */
1854
#define SSC_TFMR_DATLEN (0x1F << 0) /* Data Length */
1855
#define SSC_TFMR_DATDEF (1 << 5) /* Data Default Value */
1856
#define SSC_TFMR_MSBF (1 << 7) /* Most Significant Bit First */
1857
#define SSC_TFMR_DATNB (0x0F << 8) /* Data Number per Frame */
1858
#define SSC_TFMR_FSLEN (0x0F << 16) /* Transmit Frame Sync Length */
1859
#define SSC_TFMR_FSOS (0x07 << 20) /* Transmit Frame Sync Output Selection */
1860
#define SSC_TFMR_FSDEN (1 << 23) /* Frame Sync Data Enable */
1861
#define SSC_TFMR_FSEDGE (1 << 24) /* Frame Sync Edge Detection */
1863
/* SSC_SR: SSC Status Register */
1864
#define SSC_SR_TXRDY (1 << 0) /* Transmit Ready */
1865
#define SSC_SR_TXEMPTY (1 << 1) /* Transmit Empty */
1866
#define SSC_SR_ENDTX (1 << 2) /* End of Transmission */
1867
#define SSC_SR_TXBUFE (1 << 3) /* Transmit Buffer Empty */
1868
#define SSC_SR_RXRDY (1 << 4) /* Receive Ready */
1869
#define SSC_SR_OVRUN (1 << 5) /* Receive Overrun */
1870
#define SSC_SR_ENDRX (1 << 6) /* End of Reception */
1871
#define SSC_SR_RXBUFF (1 << 7) /* Receive Buffer Full */
1872
#define SSC_SR_CP0 (1 << 8) /* Compare 0 */
1873
#define SSC_SR_CP1 (1 << 9) /* Compare 1 */
1874
#define SSC_SR_TXSYN (1 << 10) /* Transmit Sync */
1875
#define SSC_SR_RXSYN (1 << 11) /* Receive Sync */
1876
#define SSC_SR_TXEN (1 << 16) /* Transmit Enable */
1877
#define SSC_SR_RXEN (1 << 17) /* Receive Enable */
1879
/* SSC_IR: SSC Interrupt Register (IER,IDR,IMR) */
1880
#define SSC_IR_TXRDY (1 << 0) /* Transmit Ready */
1881
#define SSC_IR_TXEMPTY (1 << 1) /* Transmit Empty */
1882
#define SSC_IR_ENDTX (1 << 2) /* End of Transmission */
1883
#define SSC_IR_TXBUFE (1 << 3) /* Transmit Buffer Empty */
1884
#define SSC_IR_RXRDY (1 << 4) /* Receive Ready */
1885
#define SSC_IR_OVRUN (1 << 5) /* Receive Overrun */
1886
#define SSC_IR_ENDRX (1 << 6) /* End of Reception */
1887
#define SSC_IR_RXBUFF (1 << 7) /* Receive Buffer Full */
1888
#define SSC_IR_CP0 (1 << 8) /* Compare 0 */
1889
#define SSC_IR_CP1 (1 << 9) /* Compare 1 */
1890
#define SSC_IR_TXSYN (1 << 10) /* Transmit Sync */
1891
#define SSC_IR_RXSYN (1 << 11) /* Receive Sync */
1894
/*--------------------*/
1895
/* Two-Wire Interface */
1896
/*--------------------*/
1897
#define TWI_BASE 0xFFFB8000
1898
#define TWI_CR __REG32(TWI_BASE + 0x00) /* Control Register */
1899
#define TWI_MMR __REG32(TWI_BASE + 0x04) /* Master Mode Register */
1900
#define TWI_IADR __REG32(TWI_BASE + 0x0C) /* Internal Address Register */
1901
#define TWI_CWGR __REG32(TWI_BASE + 0x10) /* Clock Waveform Generator Register */
1902
#define TWI_SR __REG32(TWI_BASE + 0x20) /* Status Register */
1903
#define TWI_IER __REG32(TWI_BASE + 0x24) /* Interrupt Enable Register */
1904
#define TWI_IDR __REG32(TWI_BASE + 0x28) /* Interrupt Disable Register */
1905
#define TWI_IMR __REG32(TWI_BASE + 0x2C) /* Interrupt Mask Register */
1906
#define TWI_RHR __REG32(TWI_BASE + 0x30) /* Receive Holding Register */
1907
#define TWI_THR __REG32(TWI_BASE + 0x34) /* Transmit Holding Register */
1909
/* TWI_CR: TWI Control Register */
1910
#define TWI_CR_START (1 << 0) /* Send a START Condition */
1911
#define TWI_CR_STOP (1 << 1) /* Send a STOP Condition */
1912
#define TWI_CR_MSEN (1 << 2) /* TWI Master Transfer Enabled */
1913
#define TWI_CR_MSDIS (1 << 3) /* TWI Master Transfer Disabled */
1914
#define TWI_CR_SWRST (1 << 7) /* Software Reset */
1916
/* TWI_MMR: TWI Master Mode Register */
1917
#define TWI_MMR_IADRSZ (0x03 << 8) /* Internal Device Address Size */
1918
#define TWI_MMR_IADRSZ_0 (0 << 8) /* No internal device address (byte command) */
1919
#define TWI_MMR_IADRSZ_1 (1 << 8) /* One-byte internal device address */
1920
#define TWI_MMR_IADRSZ_2 (2 << 8) /* Two-byte internal device address */
1921
#define TWI_MMR_IADRSZ_3 (3 << 8) /* Three-byte internal device address */
1922
#define TWI_MMR_MREAD (1 << 12) /* Master Read Direction (0=Write,1=Read) */
1923
#define TWI_MMR_DADR (0x7F << 16) /* Device Address */
1924
#define TWI_MMR_DADR_SHFT 16 /* bit position of DADR field */
1926
/* TWI_CWGR: TWI Clock Waveform Generator Register */
1927
#define TWI_CWGR_CLDIV (0xFF << 0) /* Clock Low Divider (SCL low period) */
1928
#define TWI_CWGR_CHDIV (0xFF << 8) /* Clock High Divider (SCL high period) */
1929
#define TWI_CWGR_CHDIV_SHFT 8
1930
#define TWI_CWGR_CKDIV (0x07 << 16) /* Clock Divider */
1931
#define TWI_CWGR_CKDIV_SHFT 16
1933
/* TWI_SR: TWI Status Register (also: TWI_IER,TWI_IDR,TWI_IMR) */
1934
#define TWI_SR_TXCOMP (1 << 0) /* Transmission Completed */
1935
#define TWI_SR_RXRDY (1 << 1) /* Receive Holding Register Ready */
1936
#define TWI_SR_TXRDY (1 << 2) /* Transmit Holding Register Ready */
1937
#define TWI_SR_OVRE (1 << 6) /* Overrun Error */
1938
#define TWI_SR_UNRE (1 << 7) /* Underrun Error */
1939
#define TWI_SR_NACK (1 << 8) /* Not Acknowledged */
1942
/*-----------------*/
1943
/* USB Device Port */
1944
/*-----------------*/
1945
#define UDP_BASE 0xFFFB0000
1946
#define UDP_FRM_NUM __REG32(UDP_BASE + 0x000) /* Frame Number Register */
1947
#define UDP_GLB_STAT __REG32(UDP_BASE + 0x004) /* Global State Register */
1948
#define UDP_FADDR __REG32(UDP_BASE + 0x008) /* Function Address Register */
1949
#define UDP_IER __REG32(UDP_BASE + 0x010) /* Interrupt Enable Register */
1950
#define UDP_IDR __REG32(UDP_BASE + 0x014) /* Interrupt Disable Register */
1951
#define UDP_IMR __REG32(UDP_BASE + 0x018) /* Interrupt Mask Register */
1952
#define UDP_ISR __REG32(UDP_BASE + 0x01C) /* Interrupt Status Register */
1953
#define UDP_ICR __REG32(UDP_BASE + 0x020) /* Interrupt Clear Register */
1954
#define UDP_RST_EP __REG32(UDP_BASE + 0x028) /* Reset Endpoint Register */
1955
#define UDP_CSR0 __REG32(UDP_BASE + 0x030) /* EP0 Control and Status Register */
1956
#define UDP_CSR1 __REG32(UDP_BASE + 0x034) /* EP1 Control and Status Register */
1957
#define UDP_CSR2 __REG32(UDP_BASE + 0x038) /* EP2 Control and Status Register */
1958
#define UDP_CSR3 __REG32(UDP_BASE + 0x03C) /* EP3 Control and Status Register */
1959
#define UDP_CSR4 __REG32(UDP_BASE + 0x040) /* EP4 Control and Status Register */
1960
#define UDP_CSR5 __REG32(UDP_BASE + 0x044) /* EP5 Control and Status Register */
1961
#define UDP_FDR0 __REG32(UDP_BASE + 0x050) /* EP0 FIFO Data Register */
1962
#define UDP_FDR1 __REG32(UDP_BASE + 0x054) /* EP1 FIFO Data Register */
1963
#define UDP_FDR2 __REG32(UDP_BASE + 0x058) /* EP2 FIFO Data Register */
1964
#define UDP_FDR3 __REG32(UDP_BASE + 0x05C) /* EP3 FIFO Data Register */
1965
#define UDP_FDR4 __REG32(UDP_BASE + 0x060) /* EP4 FIFO Data Register */
1966
#define UDP_FDR5 __REG32(UDP_BASE + 0x064) /* EP5 FIFO Data Register */
1967
#define UDP_TXVC __REG32(UDP_BASE + 0x074) /* Transceiver Control Register */
1969
/* UDP_FRM_NUM: Frame Number Register */
1970
#define UDP_FRM_NUM_FRM_NUM (0x7FF << 0) /* Frame Number */
1971
#define UDP_FRM_NUM_FRM_ERR (1 << 16) /* Frame Error */
1972
#define UDP_FRM_NUM_FRM_OK (1 << 17) /* Frame OK */
1974
/* UDP_GLB_STAT: Global State Register */
1975
#define UDP_GLB_STAT_FADDEN (1 << 0) /* Function Address Enable */
1976
#define UDP_GLB_STAT_CONFG (1 << 1) /* Configured */
1977
#define UDP_GLB_STAT_ESR (1 << 2) /* Enable Send Resume */
1978
#define UDP_GLB_STAT_RSMINPR (1 << 3) /* Resume in process */
1979
#define UDP_GLB_STAT_RMWUPE (1 << 4) /* Remote Wake Up Enable */
1981
/* UDP_FADDR: Function Address Register */
1982
#define UDP_FADDR_FADD (0x7F << 0) /* Function Address Value */
1983
#define UDP_FADDR_FEN (1 << 8) /* Function Enable */
1985
/* UDP_IER,IDR,IMR,ISR,ICR: Interrupt Register */
1986
/* ENDBUSRES only in ISR and ICR */
1987
/* EPxINT not in ICR */
1988
#define UDP_EP0INT (1 << 0) /* EP0 interrupt */
1989
#define UDP_EP1INT (1 << 1) /* EP1 interrupt */
1990
#define UDP_EP2INT (1 << 2) /* EP2 interrupt */
1991
#define UDP_EP3INT (1 << 3) /* EP3 interrupt */
1992
#define UDP_EP4INT (1 << 4) /* EP4 interrupt */
1993
#define UDP_EP5INT (1 << 5) /* EP5 interrupt */
1994
#define UDP_RXSUSP (1 << 8) /* UDP Suspend interrupt */
1995
#define UDP_RXRSM (1 << 9) /* UDP Resume interrupt */
1996
#define UDP_EXTRSM (1 << 10) /* UDP External Resume interrupt */
1997
#define UDP_SOFINT (1 << 11) /* UDP Start of Frame interrupt */
1998
#define UDP_ENDBUSRES (1 << 12) /* UDP End of BUS Reset interrupt */
1999
#define UDP_WAKEUP (1 << 13) /* UDP Wakeup interrupt */
2001
/* UDP_RST_EP: UDP Reset Endpoint Register */
2002
#define UDP_RST_EP_EP0 (1 << 0)
2003
#define UDP_RST_EP_EP1 (1 << 1)
2004
#define UDP_RST_EP_EP2 (1 << 2)
2005
#define UDP_RST_EP_EP3 (1 << 3)
2006
#define UDP_RST_EP_EP4 (1 << 4)
2007
#define UDP_RST_EP_EP5 (1 << 5)
2009
/* UDP_CSRx: UDP Endpoint Control and Status Register */
2010
#define UDP_CSR_TXCOMP (1 << 0) /* Transmit Complete */
2011
#define UDP_CSR_RX_DATA_BK0 (1 << 1) /* Receive Data Bank 0 */
2012
#define UDP_CSR_RXSETUP (1 << 2) /* SETUP packet (only Control EPs) */
2013
#define UDP_CSR_STALLSENT (1 << 3) /* Stall Sent */
2014
#define UDP_CSR_TXPKTRDY (1 << 4) /* Transmit Packet Ready */
2015
#define UDP_CSR_FORCESTALL (1 << 5) /* Force Stall */
2016
#define UDP_CSR_RX_DATA_BK1 (1 << 6) /* Receive Data Bank 1 */
2017
#define UDP_CSR_DIR (1 << 7) /* Transfer Direction (only Control EPs) */
2018
#define UDP_CSR_EPTYPE (0x07 << 8) /* Endpoint Type */
2019
#define UDP_CSR_EPTYPE_CONTROL (0 << 8) /* Control Endpoint */
2020
#define UDP_CSR_EPTYPE_ISO_OUT (1 << 8) /* Isochronous OUT Endpoint */
2021
#define UDP_CSR_EPTYPE_ISO_IN (5 << 8) /* Isochronous IN Endpoint */
2022
#define UDP_CSR_EPTYPE_BULK_OUT (2 << 8) /* Bulk OUT Endpoint */
2023
#define UDP_CSR_EPTYPE_BULK_IN (6 << 8) /* Bulk IN Endpoint */
2024
#define UDP_CSR_EPTYPE_INT_OUT (3 << 8) /* Interrupt OUT Endpoint */
2025
#define UDP_CSR_EPTYPE_INT_IN (7 << 8) /* Interrupt IN Endpoint */
2026
#define UDP_CSR_DTGLE (1 << 11) /* Data Toggle */
2027
#define UDP_CSR_EPEDS (1 << 15) /* Endpoint Enable Disable */
2028
#define UDP_CSR_RXBYTECNT (0x7FF << 16) /* Number of Bytes Available in FIFO */
2030
/* UDP_FDRx: UDP FIFO Data Register */
2031
#define UDP_FDR_FIFO_DATA (0xFF << 0) /* FIFO Data Value */
2033
/* UDP_TXVC: UDP Transceiver Control Register */
2034
#define UDP_TXVC_TXVDIS (1 << 8) /* Transceiver Disable */
2037
/*---------------------------*/
2038
/* Multimedia Card Interface */
2039
/*---------------------------*/
2040
#define MCI_BASE 0xFFFAC000
2041
#define MCI_CR __REG32(MCI_BASE + 0x000) /* Control Register */
2042
#define MCI_MR __REG32(MCI_BASE + 0x004) /* Mode Register */
2043
#define MCI_DTOR __REG32(MCI_BASE + 0x008) /* Data Timeout Register */
2044
#define MCI_SDCR __REG32(MCI_BASE + 0x00C) /* SD Card Register */
2045
#define MCI_ARGR __REG32(MCI_BASE + 0x010) /* Argument Register */
2046
#define MCI_CMDR __REG32(MCI_BASE + 0x014) /* Command Register */
2047
#define MCI_RSPR __REG32(MCI_BASE + 0x020) /* Response Register */
2048
#define MCI_RSPR1 __REG32(MCI_BASE + 0x024) /* Response Register */
2049
#define MCI_RSPR2 __REG32(MCI_BASE + 0x028) /* Response Register */
2050
#define MCI_RSPR3 __REG32(MCI_BASE + 0x02C) /* Response Register */
2051
#define MCI_RDR __REG32(MCI_BASE + 0x030) /* Receive Data Register */
2052
#define MCI_TDR __REG32(MCI_BASE + 0x034) /* Transmit Data Register */
2053
#define MCI_SR __REG32(MCI_BASE + 0x040) /* Status Register */
2054
#define MCI_IER __REG32(MCI_BASE + 0x044) /* Interrupt Enable Register */
2055
#define MCI_IDR __REG32(MCI_BASE + 0x048) /* Interrupt Disable Register */
2056
#define MCI_IMR __REG32(MCI_BASE + 0x048) /* Interrupt Mask Register */
2057
#define MCI_RPR __REG32(MCI_BASE + 0x100) /* Receive Pointer Register */
2058
#define MCI_RCR __REG32(MCI_BASE + 0x104) /* Receive Counter Register */
2059
#define MCI_TPR __REG32(MCI_BASE + 0x108) /* Transmit Pointer Register */
2060
#define MCI_TCR __REG32(MCI_BASE + 0x10C) /* Transmit Counter Register */
2061
#define MCI_RNPR __REG32(MCI_BASE + 0x110) /* Receive Next Pointer Register */
2062
#define MCI_RNCR __REG32(MCI_BASE + 0x114) /* Receive Next Counter Register */
2063
#define MCI_TNPR __REG32(MCI_BASE + 0x118) /* Transmit Next Pointer Register */
2064
#define MCI_TNCR __REG32(MCI_BASE + 0x11C) /* Transmit Next Counter Register */
2065
#define MCI_PTCR __REG32(MCI_BASE + 0x120) /* PDC Transfer Control Register */
2066
#define MCI_PTSR __REG32(MCI_BASE + 0x124) /* PDC Transfer Status Register */
2068
/* MCI_CR: MCI Control Register */
2069
#define MCI_CR_MCIEN (1 << 0) /* Multi-Media Interface Enable */
2070
#define MCI_CR_MCIDIS (1 << 1) /* Multi-Media Interface Disable */
2071
#define MCI_CR_PWSEN (1 << 2) /* Power Save Mode Enable */
2072
#define MCI_CR_PWSDIS (1 << 3) /* Power Save Mode Disable */
2073
#define MCI_CR_SWRST (1 << 7) /* Software Reset */
2075
/* MCI_MR: MCI Mode Register */
2076
#define MCI_MR_CLKDIV (0x0FF << 0) /* Clock Divider */
2077
#define MCI_MR_PWSDIV (0x007 << 8) /* Power Saving Divider */
2078
#define MCI_MR_PDCPADV (1 << 14) /* PDC Padding Value (0=0x00,1=0xFF) */
2079
#define MCI_MR_PDCMODE (1 << 15) /* PDC-oriented Mode */
2080
#define MCI_MR_BLKLEN (0xFFF << 18) /* Data Block Length */
2081
#define MCI_MR_BLKLEN_SHFT 18 /* bit position of BLKLEN field */
2083
/* MCI_DTOR: Data Timeout Register */
2084
#define MCI_DTOR_DTOCYC (0x0F << 0) /* Data Timeout Cycle Number */
2085
#define MCI_DTOR_DTOMUL (0x07 << 4) /* Data Timeout Multiplier */
2086
#define MCI_DTOR_DTOMUL_SHFT 4 /* bit position of DTOMUL field */
2088
/* MCI_SDCR: MCI SD Card Register */
2089
#define MCI_SDCR_SDCSEL (0x0F << 0) /* SD Card Selector */
2090
#define MCI_SDCR_SDCBUS (1 << 7) /* SD Card Bus Width (0=1-bit,1=4-bit) */
2092
/* MCI_CMDR: MCI Command Register */
2093
#define MCI_CMDR_CMDNB (0x3F << 0) /* Command Number */
2094
#define MCI_CMDR_RSPTYP (0x03 << 6) /* Response Type */
2095
#define MCI_CMDR_RSPTYP_NONE (0 << 6) /* No response */
2096
#define MCI_CMDR_RSPTYP_48 (1 << 6) /* 48-bit response */
2097
#define MCI_CMDR_RSPTYP_136 (2 << 6) /* 136-bit response */
2098
#define MCI_CMDR_SPCMD (0x07 << 8) /* Special Command */
2099
#define MCI_CMDR_SPCMD_NONE (0 << 8) /* Not a special CMD */
2100
#define MCI_CMDR_SPCMD_INIT (1 << 8) /* Initialization CMD */
2101
#define MCI_CMDR_SPCMD_SYNC (2 << 8) /* Synchronized CMD */
2102
#define MCI_CMDR_SPCMD_INTCMD (4 << 8) /* Interrupt command */
2103
#define MCI_CMDR_SPCMD_INTRSP (5 << 8) /* Interrupt response */
2104
#define MCI_CMDR_OPDCMD (1 << 11) /* Open Drain Command */
2105
#define MCI_CMDR_MAXLAT (1 << 12) /* Max Latency for Command to Response */
2106
#define MCI_CMDR_MAXLAT_5C (0 << 12) /* 5-cycle max latency */
2107
#define MCI_CMDR_MAXLAT_64C (1 << 12) /* 64-cycle max latency */
2108
#define MCI_CMDR_TRCMD (0x03 << 16) /* Transfer Command */
2109
#define MCI_CMDR_TRCMD_NODATA (0 << 16) /* No data transfer */
2110
#define MCI_CMDR_TRCMD_START (1 << 16) /* Start data transfer */
2111
#define MCI_CMDR_TRCMD_STOP (2 << 16) /* Stop data transfer */
2112
#define MCI_CMDR_TRDIR (1 << 18) /* Transfer Direction (0=Write,1=Read) */
2113
#define MCI_CMDR_TRDIR_WRITE (0 << 18)
2114
#define MCI_CMDR_TRDIR_READ (1 << 18)
2115
#define MCI_CMDR_TRTYP (0x03 << 19) /* Transfer Type */
2116
#define MCI_CMDR_TRTYP_BLOCK (0 << 19) /* Block */
2117
#define MCI_CMDR_TRTYP_MULBLK (1 << 19) /* Multiple Block */
2118
#define MCI_CMDR_TRTYP_STREAM (2 << 19) /* Stream */
2120
/* MCI_SR: MCI Status Register (also: MCI_IER,MCI_IDR,MCI_IMR,MCI_ISR) */
2121
#define MCI_SR_CMDRDY (1 << 0) /* Command Ready */
2122
#define MCI_SR_RXRDY (1 << 1) /* Receiver Ready */
2123
#define MCI_SR_TXRDY (1 << 2) /* Transmit Ready */
2124
#define MCI_SR_BLKE (1 << 3) /* Data Block Ended */
2125
#define MCI_SR_DTIP (1 << 4) /* Data Transfer In Progress */
2126
#define MCI_SR_NOTBUSY (1 << 5) /* Data Not Busy */
2127
#define MCI_SR_ENDRX (1 << 6) /* End of RX Buffer */
2128
#define MCI_SR_ENDTX (1 << 7) /* End of TX Buffer */
2129
#define MCI_SR_RXBUFF (1 << 14) /* RX Buffer Full */
2130
#define MCI_SR_TXBUFE (1 << 15) /* TX Buffer Empty */
2131
#define MCI_SR_RINDE (1 << 16) /* Response Index Error */
2132
#define MCI_SR_RDIRE (1 << 17) /* Response Direction Error */
2133
#define MCI_SR_RCRCE (1 << 18) /* Response CRC Error */
2134
#define MCI_SR_RENDE (1 << 19) /* Response End Bit Error */
2135
#define MCI_SR_RTOE (1 << 20) /* Response Time-out Error */
2136
#define MCI_SR_DCRCE (1 << 21) /* Data CRC Error */
2137
#define MCI_SR_DTOE (1 << 22) /* Data Time-out Error */
2138
#define MCI_SR_OVRE (1 << 30) /* Overrun */
2139
#define MCI_SR_UNRE (1u << 31) /* Underrun */
2142
/*----------------*/
2143
/* PWM Controller */
2144
/*----------------*/
2145
#define PWMC_BASE 0xFFFCC000
2146
#define PWM_MR __REG32(PWMC_BASE + 0x000) /* PWM Mode Register */
2147
#define PWM_ENA __REG32(PWMC_BASE + 0x004) /* PWM Enable Register */
2148
#define PWM_DIS __REG32(PWMC_BASE + 0x008) /* PWM Disable Register */
2149
#define PWM_SR __REG32(PWMC_BASE + 0x00C) /* PWM Status Register */
2150
#define PWM_IER __REG32(PWMC_BASE + 0x010) /* PWM Interrupt Enable Register */
2151
#define PWM_IDR __REG32(PWMC_BASE + 0x014) /* PWM Interrupt Disable Register */
2152
#define PWM_IMR __REG32(PWMC_BASE + 0x018) /* PWM Interrupt Mask Register */
2153
#define PWM_ISR __REG32(PWMC_BASE + 0x01C) /* PWM Interrupt Status Register */
2154
#define PWM_CMR0 __REG32(PWMC_BASE + 0x200) /* Channel 0 Mode Register */
2155
#define PWM_CDTY0 __REG32(PWMC_BASE + 0x204) /* Channel 0 Duty Cycle Register */
2156
#define PWM_CPRD0 __REG32(PWMC_BASE + 0x208) /* Channel 0 Period Register */
2157
#define PWM_CCNT0 __REG32(PWMC_BASE + 0x20C) /* Channel 0 Counter Register */
2158
#define PWM_CUPD0 __REG32(PWMC_BASE + 0x210) /* Channel 0 Update Register */
2159
#define PWM_CMR1 __REG32(PWMC_BASE + 0x220) /* Channel 1 Mode Register */
2160
#define PWM_CDTY1 __REG32(PWMC_BASE + 0x224) /* Channel 1 Duty Cycle Register */
2161
#define PWM_CPRD1 __REG32(PWMC_BASE + 0x228) /* Channel 1 Period Register */
2162
#define PWM_CCNT1 __REG32(PWMC_BASE + 0x22C) /* Channel 1 Counter Register */
2163
#define PWM_CUPD1 __REG32(PWMC_BASE + 0x230) /* Channel 1 Update Register */
2164
#define PWM_CMR2 __REG32(PWMC_BASE + 0x240) /* Channel 2 Mode Register */
2165
#define PWM_CDTY2 __REG32(PWMC_BASE + 0x244) /* Channel 2 Duty Cycle Register */
2166
#define PWM_CPRD2 __REG32(PWMC_BASE + 0x248) /* Channel 2 Period Register */
2167
#define PWM_CCNT2 __REG32(PWMC_BASE + 0x24C) /* Channel 2 Counter Register */
2168
#define PWM_CUPD2 __REG32(PWMC_BASE + 0x250) /* Channel 2 Update Register */
2169
#define PWM_CMR3 __REG32(PWMC_BASE + 0x260) /* Channel 3 Mode Register */
2170
#define PWM_CDTY3 __REG32(PWMC_BASE + 0x264) /* Channel 3 Duty Cycle Register */
2171
#define PWM_CPRD3 __REG32(PWMC_BASE + 0x268) /* Channel 3 Period Register */
2172
#define PWM_CCNT3 __REG32(PWMC_BASE + 0x26C) /* Channel 3 Counter Register */
2173
#define PWM_CUPD3 __REG32(PWMC_BASE + 0x270) /* Channel 3 Update Register */
2174
#define PWM_CMR4 __REG32(PWMC_BASE + 0x280) /* Channel 4 Mode Register */
2175
#define PWM_CDTY4 __REG32(PWMC_BASE + 0x284) /* Channel 4 Duty Cycle Register */
2176
#define PWM_CPRD4 __REG32(PWMC_BASE + 0x288) /* Channel 4 Period Register */
2177
#define PWM_CCNT4 __REG32(PWMC_BASE + 0x28C) /* Channel 4 Counter Register */
2178
#define PWM_CUPD4 __REG32(PWMC_BASE + 0x290) /* Channel 4 Update Register */
2179
#define PWM_CMR5 __REG32(PWMC_BASE + 0x2A0) /* Channel 5 Mode Register */
2180
#define PWM_CDTY5 __REG32(PWMC_BASE + 0x2A4) /* Channel 5 Duty Cycle Register */
2181
#define PWM_CPRD5 __REG32(PWMC_BASE + 0x2A8) /* Channel 5 Period Register */
2182
#define PWM_CCNT5 __REG32(PWMC_BASE + 0x2AC) /* Channel 5 Counter Register */
2183
#define PWM_CUPD5 __REG32(PWMC_BASE + 0x2B0) /* Channel 5 Update Register */
2184
#define PWM_CMR6 __REG32(PWMC_BASE + 0x2C0) /* Channel 6 Mode Register */
2185
#define PWM_CDTY6 __REG32(PWMC_BASE + 0x2C4) /* Channel 6 Duty Cycle Register */
2186
#define PWM_CPRD6 __REG32(PWMC_BASE + 0x2C8) /* Channel 6 Period Register */
2187
#define PWM_CCNT6 __REG32(PWMC_BASE + 0x2CC) /* Channel 6 Counter Register */
2188
#define PWM_CUPD6 __REG32(PWMC_BASE + 0x2D0) /* Channel 6 Update Register */
2189
#define PWM_CMR7 __REG32(PWMC_BASE + 0x2E0) /* Channel 7 Mode Register */
2190
#define PWM_CDTY7 __REG32(PWMC_BASE + 0x2E4) /* Channel 7 Duty Cycle Register */
2191
#define PWM_CPRD7 __REG32(PWMC_BASE + 0x2E8) /* Channel 7 Period Register */
2192
#define PWM_CCNT7 __REG32(PWMC_BASE + 0x2EC) /* Channel 7 Counter Register */
2193
#define PWM_CUPD7 __REG32(PWMC_BASE + 0x2F0) /* Channel 7 Update Register */
2195
/* PWM_MR: PWM Mode Register */
2196
#define PWM_MR_DIVA (0xFF << 0) /* CLKA Divide Factor */
2197
#define PWM_MR_PREA (0x0F << 8) /* CLKA Divider Input Clock */
2198
#define PWM_MR_DIVA_SHFT 0
2199
#define PWM_MR_PREA_SHFT 8
2200
#define PWM_MR_DIVB (0xFF << 16) /* CLKB Divide Factor */
2201
#define PWM_MR_PREB (0x0F << 24) /* CLKB Divider Input Clock */
2202
#define PWM_MR_DIVB_SHFT 16
2203
#define PWM_MR_PREB_SHFT 24
2204
/* Divider Input Clock values */
2205
#define PWM_MR_PRE_MCK (0x00) /* MCK */
2206
#define PWM_MR_PRE_MCK2 (0x01) /* MCK/2 */
2207
#define PWM_MR_PRE_MCK4 (0x02) /* MCK/4 */
2208
#define PWM_MR_PRE_MCK8 (0x03) /* MCK/8 */
2209
#define PWM_MR_PRE_MCK16 (0x04) /* MCK/16 */
2210
#define PWM_MR_PRE_MCK32 (0x05) /* MCK/32 */
2211
#define PWM_MR_PRE_MCK64 (0x06) /* MCK/64 */
2212
#define PWM_MR_PRE_MCK128 (0x07) /* MCK/128 */
2213
#define PWM_MR_PRE_MCK256 (0x08) /* MCK/256 */
2214
#define PWM_MR_PRE_MCK512 (0x09) /* MCK/512 */
2215
#define PWM_MR_PRE_MCK1024 (0x0A) /* MCK/1024 */
2217
/* Channel IDs (PWM_ENA, PWM_DIS, PWM_SR, PWM_IER, PWM_IDR, PWM_IMR, PWM_ISR) */
2218
#define PWM_CHID0 (1 << 0) /* PWM channel 0 */
2219
#define PWM_CHID1 (1 << 1) /* PWM channel 1 */
2220
#define PWM_CHID2 (1 << 2) /* PWM channel 2 */
2221
#define PWM_CHID3 (1 << 3) /* PWM channel 3 */
2222
#define PWM_CHID4 (1 << 4) /* PWM channel 4 */
2223
#define PWM_CHID5 (1 << 5) /* PWM channel 5 */
2224
#define PWM_CHID6 (1 << 6) /* PWM channel 6 */
2225
#define PWM_CHID7 (1 << 7) /* PWM channel 7 */
2227
/* PWM Channel Mode Registers (PWM_CMRx) */
2228
#define PWM_CMR_CPRE (0x0F << 0) /* Channel Pre-scaler */
2229
#define PWM_CMR_CPRE_MCK (0x00) /* MCK */
2230
#define PWM_CMR_CPRE_MCK2 (0x01) /* MCK/2 */
2231
#define PWM_CMR_CPRE_MCK4 (0x02) /* MCK/4 */
2232
#define PWM_CMR_CPRE_MCK8 (0x03) /* MCK/8 */
2233
#define PWM_CMR_CPRE_MCK16 (0x04) /* MCK/16 */
2234
#define PWM_CMR_CPRE_MCK32 (0x05) /* MCK/32 */
2235
#define PWM_CMR_CPRE_MCK64 (0x06) /* MCK/64 */
2236
#define PWM_CMR_CPRE_MCK128 (0x07) /* MCK/128 */
2237
#define PWM_CMR_CPRE_MCK256 (0x08) /* MCK/256 */
2238
#define PWM_CMR_CPRE_MCK512 (0x09) /* MCK/512 */
2239
#define PWM_CMR_CPRE_MCK1024 (0x0A) /* MCK/1024 */
2240
#define PWM_CMR_CPRE_CLKA (0x0B) /* CLKA */
2241
#define PWM_CMR_CPRE_CLKB (0x0C) /* CLKB */
2242
#define PWM_CMR_CALG (1 << 8) /* Channel Alignment (1=Center,0=Left) */
2243
#define PWM_CMR_CPOL (1 << 9) /* Channel Polarity (1=High,0=Low) */
2244
#define PWM_CMR_CPD (1 << 10) /* Channel Update Period (0=update Duty Cycle) */
2247
/*----------------*/
2248
/* CAN Controller */
2249
/*----------------*/
2250
#define CAN0_BASE 0xFFF80000
2252
#define CAN1_BASE 0xFFF84000
2255
#endif /* __AT91SAM7A3_H__ */
added
removed
src/plugins/scriptedwizard/resources/arm/files/ek-at91sam7a3/h/at91sam7a3.h
