1
/*====================================================================
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* Project: Board Support Package (BSP)
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* Function: Standard definitions for PHILIPS ARM7TDMI-S controller LPC213x
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* Copyright HighTec EDV-Systeme GmbH 1982-2007
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*====================================================================*/
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/* general register definition macro */
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#define __REG32(x) ((volatile unsigned int *)(x))
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#define __REG16(x) ((volatile unsigned short *)(x))
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#define __REG8(x) ((volatile unsigned char *)(x))
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/*-----------------------------*/
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/* Interrupt Source Identifier */
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/*-----------------------------*/
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#define WDT_ID 0 /* Watchdog Interrupt */
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#define SW_ID 1 /* Reserved for software interrupts only */
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#define COMMRX_ID 2 /* RX Debug Communication Channel Interrupt */
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#define COMMTX_ID 3 /* TX Debug Communication Channel Interrupt */
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#define TIMER0_ID 4 /* Timer 0 Interrupts */
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#define TIMER1_ID 5 /* Timer 1 Interrupts */
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#define UART0_ID 6 /* UART0 Interrupts */
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#define UART1_ID 7 /* UART1 Interrupts */
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#define PWM0_ID 8 /* PWM Interrupts */
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#define I2C0_ID 9 /* I2C0 Interrupt */
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#define SPI0_ID 10 /* SPI0 Interrupts */
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#define SPI1_ID 11 /* SPI1 Interrupts */
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#define PLL_ID 12 /* PLL Interrupt (PLOCK) */
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#define RTC_ID 13 /* Real Time Clock Interrupts */
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#define EINT0_ID 14 /* External Interrupt 0 */
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#define EINT1_ID 15 /* External Interrupt 1 */
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#define EINT2_ID 16 /* External Interrupt 2 */
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#define EINT3_ID 17 /* External Interrupt 3 */
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#define ADC0_ID 18 /* Analog to Digital Converter 0 Interrupt */
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#define I2C1_ID 19 /* I2C1 Interrupt */
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#define BOD_ID 20 /* Brown Out Detect Interrupt */
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#define ADC1_ID 21 /* Analog to Digital Converter 1 Interrupt */
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#define ISR_VALID_MASK 0x003FFFFF
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#define MAXIRQNUM (ISR_MAX)
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#define MAXFIQNUM (MAXIRQNUM)
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#define NR_IRQS (MAXIRQNUM + 1)
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/*------------------------------*/
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/* System Control Block */
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/*------------------------------*/
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#define SCB_BASE 0xE01FC000
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#define MAMCR __REG32(SCB_BASE + 0x000) /* MAM Control Register */
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#define MAMTIM __REG32(SCB_BASE + 0x004) /* MAM Timing Control */
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#define MEMMAP __REG32(SCB_BASE + 0x040) /* Memory Mapping Control */
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#define PLLCON __REG32(SCB_BASE + 0x080) /* PLL Control Register */
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#define PLLCFG __REG32(SCB_BASE + 0x084) /* PLL Configuration Register */
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#define PLLSTAT __REG32(SCB_BASE + 0x088) /* PLL Status Register (RO) */
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#define PLLFEED __REG32(SCB_BASE + 0x08C) /* PLL Feed Register (WO) */
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#define PCON __REG32(SCB_BASE + 0x0C0) /* Power Control Register */
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#define PCONP __REG32(SCB_BASE + 0x0C4) /* Power Control Peripherals */
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#define APBDIV __REG32(SCB_BASE + 0x100) /* APB Divider Control */
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#define EXTINT __REG32(SCB_BASE + 0x140) /* Ext. Interrupt Flag */
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#define INTWAKE __REG32(SCB_BASE + 0x144) /* Ext. Interrupt Wakeup */
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#define EXTMODE __REG32(SCB_BASE + 0x148) /* Ext. Interrupt Mode */
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#define EXTPOLAR __REG32(SCB_BASE + 0x14C) /* Ext. Interrupt Polarity */
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#define RSID __REG32(SCB_BASE + 0x180) /* Reset Source Identification Register */
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#define CSPR __REG32(SCB_BASE + 0x184) /* Code Security Protection Register */
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#define SCS __REG32(SCB_BASE + 0x1A0) /* System Controls and Status */
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/* Memory Mapping Control Register Bits Definition */
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#define MEMMAP_BOOT 0x00 /* vectors mapped to Boot Block */
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#define MEMMAP_FLASH 0x01 /* vectors at 0 (internal Flash) */
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#define MEMMAP_ISRAM 0x02 /* vectors mapped to internal SRAM */
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#define ISRAM_START 0x40000000 /* start of internal SRAM */
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/* PLL Control Register Bits Definition */
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#define PLLCON_PLLE (1 << 0) /* PLL Enable */
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#define PLLCON_PLLC (1 << 1) /* PLL Connect */
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/* PLL Configuration Register Bits Definition */
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#define PLLCFG_MSEL (0x1F << 0) /* PLL Multiplier value "M" */
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#define PLLCFG_PSEL (0x03 << 5) /* PLL Divider value "P" */
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/* PLL Status Register Bits Definition */
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#define PLLSTAT_MSEL (0x1F << 0) /* PLL Multiplier value "M" */
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#define PLLSTAT_PSEL (0x03 << 5) /* PLL Divider value "P" */
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#define PLLSTAT_PLLE (1 << 8) /* Status of PLL Enable */
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#define PLLSTAT_PLLC (1 << 9) /* Status of PLL Connect */
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#define PLLSTAT_PLOCK (1 << 10) /* PLL Lock Status */
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#define PLLFEED_PW0 0xAA
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#define PLLFEED_PW1 0x55
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/* Power Control Register Bits Definition */
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#define PCON_IDL (1 << 0) /* Idle mode control */
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#define PCON_PD (1 << 1) /* Power-Down mode control */
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#define PCON_BODPDM (1 << 2) /* Brown-Out Power-Down mode control */
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#define PCON_BOGD (1 << 3) /* Brown-Out Global Disable */
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#define PCON_BORD (1 << 4) /* Brown-Out Reset Disable */
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/* Power Control Peripherals Bits Definition */
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#define PCTIM0 (1U << 1) /* Timer 0 */
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#define PCTIM1 (1U << 2) /* Timer 1 */
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#define PCURT0 (1U << 3) /* UART 0 */
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#define PCURT1 (1U << 4) /* UART 1 */
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#define PCPWM0 (1U << 5) /* PWM unit */
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#define PCI2C0 (1U << 7) /* I2C interface 0 */
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#define PCSPI0 (1U << 8) /* SPI 0 */
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#define PCRTC (1U << 9) /* RTC */
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#define PCSPI1 (1U << 10) /* SPI 1 */
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#define PCAD0 (1U << 12) /* Analog to Digital Converter 0 */
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#define PCI2C1 (1U << 19) /* I2C interface 1 */
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#define PCAD1 (1U << 20) /* Analog to Digital Converter 1 */
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/* Reset Source Identification Register Bits Definition */
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#define RSID_POR (1 << 0) /* Power On Reset */
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#define RSID_EXTR (1 << 1) /* External /RESET */
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#define RSID_WDTR (1 << 2) /* Watchdog Timer Reset */
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#define RSID_BODR (1 << 3) /* Brown-Out Detect Reset */
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/* APB Divider values */
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#define APBDIV_MSK 0x03
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#define APBDIV_4 0 /* peripherals clock == CPU/4 clock */
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#define APBDIV_2 2 /* peripherals clock == CPU/2 clock */
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#define APBDIV_1 1 /* peripherals clock == CPU clock */
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/*-------------------------------------------------------*/
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/* Vector Interrupt Controller Module Bits Definitions */
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/*-------------------------------------------------------*/
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/*------------------------------------------*/
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/* Vector Interrupt Controller Register */
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/*------------------------------------------*/
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#define VIC_BASE 0xFFFFF000
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#define VICIRQSTAT __REG32(VIC_BASE + 0x000) /* IRQ Status Register */
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#define VICFIQSTAT __REG32(VIC_BASE + 0x004) /* FIQ Status Register */
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#define VICRIR __REG32(VIC_BASE + 0x008) /* Raw Interrupt Status */
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#define VICISR __REG32(VIC_BASE + 0x00C) /* Interrupt Select Reg */
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#define VICIEN __REG32(VIC_BASE + 0x010) /* Interrupt Enable Reg */
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#define VICIEC __REG32(VIC_BASE + 0x014) /* Interrupt Enable Clear */
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#define VICSIR __REG32(VIC_BASE + 0x018) /* Software Interrupt Reg */
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#define VICSIC __REG32(VIC_BASE + 0x01C) /* SW Interrupt Clear Reg */
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#define VICPRO __REG32(VIC_BASE + 0x020) /* Protection Enable Reg */
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#define VICVADDR __REG32(VIC_BASE + 0x030) /* Vector Address Reg */
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#define VICDEFVADDR __REG32(VIC_BASE + 0x034) /* Default Vector Address */
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/* Vector Address Register 0 - 15 */
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#define VICVADDR0 __REG32(VIC_BASE + 0x100)
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#define VICVADDR1 __REG32(VIC_BASE + 0x104)
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#define VICVADDR2 __REG32(VIC_BASE + 0x108)
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#define VICVADDR3 __REG32(VIC_BASE + 0x10C)
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#define VICVADDR4 __REG32(VIC_BASE + 0x110)
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#define VICVADDR5 __REG32(VIC_BASE + 0x114)
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#define VICVADDR6 __REG32(VIC_BASE + 0x118)
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#define VICVADDR7 __REG32(VIC_BASE + 0x11C)
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#define VICVADDR8 __REG32(VIC_BASE + 0x120)
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#define VICVADDR9 __REG32(VIC_BASE + 0x124)
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#define VICVADDR10 __REG32(VIC_BASE + 0x128)
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#define VICVADDR11 __REG32(VIC_BASE + 0x12C)
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#define VICVADDR12 __REG32(VIC_BASE + 0x130)
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#define VICVADDR13 __REG32(VIC_BASE + 0x134)
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#define VICVADDR14 __REG32(VIC_BASE + 0x138)
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#define VICVADDR15 __REG32(VIC_BASE + 0x13C)
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/* Vector Control Register 0 - 15: 0 = highest, 15 lowest prio */
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#define VICVCR0 __REG32(VIC_BASE + 0x200)
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#define VICVCR1 __REG32(VIC_BASE + 0x204)
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#define VICVCR2 __REG32(VIC_BASE + 0x208)
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#define VICVCR3 __REG32(VIC_BASE + 0x20C)
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#define VICVCR4 __REG32(VIC_BASE + 0x210)
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#define VICVCR5 __REG32(VIC_BASE + 0x214)
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#define VICVCR6 __REG32(VIC_BASE + 0x218)
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#define VICVCR7 __REG32(VIC_BASE + 0x21C)
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#define VICVCR8 __REG32(VIC_BASE + 0x220)
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#define VICVCR9 __REG32(VIC_BASE + 0x224)
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#define VICVCR10 __REG32(VIC_BASE + 0x228)
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#define VICVCR11 __REG32(VIC_BASE + 0x22C)
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#define VICVCR12 __REG32(VIC_BASE + 0x230)
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#define VICVCR13 __REG32(VIC_BASE + 0x234)
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#define VICVCR14 __REG32(VIC_BASE + 0x238)
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#define VICVCR15 __REG32(VIC_BASE + 0x23C)
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/*---------------------------------------------*/
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/* Pin Connect Block Bits Definitions */
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/*---------------------------------------------*/
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/*----------------------------*/
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/* Pin Connect Block Register */
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/*----------------------------*/
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#define PCB_BASE 0xE002C000
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#define PINSEL0 __REG32(PCB_BASE + 0x00) /* Pin function select register 0 */
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#define PINSEL1 __REG32(PCB_BASE + 0x04) /* Pin function select register 1 */
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#define PINSEL2 __REG32(PCB_BASE + 0x14) /* Pin function select register 2 */
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/*----------- PINSEL0 Bit Definitions ---------*/
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#define GPIO00 (0 << 0)
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#define GPIO00TXD0 (1 << 0)
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#define GPIO00PWM1 (2 << 0)
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#define GPIO01 (0 << 2)
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#define GPIO01RXD0 (1 << 2)
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#define GPIO01PWM3 (2 << 2)
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#define GPIO01EINT0 (3 << 2)
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#define GPIO02 (0 << 4)
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#define GPIO02SCL0 (1 << 4) /* I2C0 */
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#define GPIO02CR00 (2 << 4) /* Capture 0.0 (Timer 0) */
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#define GPIO03 (0 << 6)
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#define GPIO03SDA0 (1 << 6) /* I2C0 */
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#define GPIO03MR00 (2 << 6) /* Match 0.0 (Timer 0) */
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#define GPIO03EINT1 (3 << 6)
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#define GPIO04 (0 << 8)
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#define GPIO04SCK0 (1 << 8) /* SPI0 */
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#define GPIO04CR01 (2 << 8) /* Capture 0.1 (Timer 0) */
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#define GPIO04AD06 (3 << 8) /* AD0.6 */
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#define GPIO05 (0 << 10)
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#define GPIO05MISO0 (1 << 10) /* SPI0 */
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#define GPIO05MR01 (2 << 10) /* Match 0.1 (Timer 0) */
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#define GPIO05AD07 (3 << 10) /* AD0.7 */
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#define GPIO06 (0 << 12)
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#define GPIO06MOSI0 (1 << 12) /* SPI0 */
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#define GPIO06CR02 (2 << 12) /* Capture 0.2 (Timer 0) */
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#define GPIO06AD10 (3 << 12) /* AD1.0 */
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#define GPIO07 (0 << 14)
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#define GPIO07SSEL0 (1 << 14) /* SPI0 */
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#define GPIO07PWM2 (2 << 14)
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#define GPIO07EINT2 (3 << 14)
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#define GPIO08 (0 << 16)
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#define GPIO08TXD1 (1 << 16)
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#define GPIO08PWM4 (2 << 16)
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#define GPIO08AD11 (3 << 16) /* AD1.1 */
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#define GPIO09 (0 << 18)
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#define GPIO09RXD1 (1 << 18)
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#define GPIO09PWM6 (2 << 18)
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#define GPIO09EINT3 (3 << 18)
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#define GPIO010 (0 << 20)
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#define GPIO010RTS1 (1 << 20)
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#define GPIO010CR10 (2 << 20) /* Capture 1.0 (Timer 1) */
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#define GPIO010AD12 (3 << 20) /* AD1.2 */
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#define GPIO011 (0 << 22)
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#define GPIO011CTS1 (1 << 22)
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#define GPIO011CR11 (2 << 22) /* Capture 1.1 (Timer 1) */
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#define GPIO011SCL1 (3 << 22) /* I2C1 */
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#define GPIO012 (0 << 24)
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#define GPIO012DSR1 (1 << 24)
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#define GPIO012MR10 (2 << 24) /* Match 1.0 (Timer 1) */
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#define GPIO012AD13 (3 << 24) /* AD1.3 */
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#define GPIO013 (0 << 26)
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#define GPIO013DTR1 (1 << 26)
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#define GPIO013MR11 (2 << 26) /* Match 1.1 (Timer 1) */
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#define GPIO013AD14 (3 << 26) /* AD1.4 */
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#define GPIO014 (0 << 28)
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#define GPIO014DCD1 (1 << 28)
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#define GPIO014EINT1 (2 << 28)
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#define GPIO014SDA1 (3 << 28) /* I2C1 */
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#define GPIO015 (0u << 30)
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#define GPIO015RI1 (1u << 30)
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#define GPIO015EINT2 (2u << 30)
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#define GPIO015AD15 (3u << 30) /* AD1.5 */
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/*----------- PINSEL1 Bit Definitions ---------*/
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#define GPIO016 (0 << 0)
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#define GPIO016EINT0 (1 << 0)
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#define GPIO016MR02 (2 << 0) /* Match 0.2 (Timer 0) */
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#define GPIO016CR02 (3 << 0) /* Capture 0.2 (Timer 0) */
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#define GPIO017 (0 << 2)
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#define GPIO017CR12 (1 << 2) /* Capture 1.2 (Timer 1) */
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#define GPIO017SCK1 (2 << 2) /* SPI1 (SSP) */
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#define GPIO017MR12 (3 << 2) /* Match 1.2 (Timer 1) */
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#define GPIO018 (0 << 4)
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#define GPIO018CR13 (1 << 4) /* Capture 1.3 (Timer 1) */
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#define GPIO018MISO1 (2 << 4) /* SPI1 (SSP) */
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#define GPIO018MR13 (3 << 4) /* Match 1.3 (Timer 1) */
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#define GPIO019 (0 << 6)
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#define GPIO019MR12 (1 << 6) /* Match 1.2 (Timer 1) */
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#define GPIO019MOSI1 (2 << 6) /* SPI1 (SSP) */
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#define GPIO019CR12 (3 << 6) /* Capture 1.2 (Timer 1) */
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#define GPIO020 (0 << 8)
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#define GPIO020MR13 (1 << 8) /* Match 1.3 (Timer 1) */
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#define GPIO020SSEL1 (2 << 8) /* SPI1 (SSP) */
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#define GPIO020EINT3 (3 << 8)
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#define GPIO021 (0 << 10)
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#define GPIO021PWM5 (1 << 10)
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#define GPIO021AD16 (2 << 10) /* AD1.6 */
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#define GPIO021CR13 (3 << 10) /* Capture 1.3 (Timer 1) */
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#define GPIO022 (0 << 12)
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#define GPIO022AD17 (1 << 12) /* AD1.7 */
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#define GPIO022CR00 (2 << 12) /* Capture 0.0 (Timer 0) */
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#define GPIO022MR00 (3 << 12) /* Match 0.0 (Timer 0) */
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#define GPIO023 (0 << 14)
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#define GPIO024 (0 << 16)
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#define GPIO025 (0 << 18)
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#define GPIO025AD04 (1 << 18) /* AD0.4 */
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#define GPIO025DAC (2 << 18) /* Aout DAC */
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#define GPIO026 (0 << 20)
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#define GPIO026AD04 (1 << 20) /* AD0.5 */
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#define GPIO027 (0 << 22)
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#define GPIO027AD00 (1 << 22) /* AD0.0 */
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#define GPIO027CR01 (2 << 22) /* Capture 0.1 (Timer 0) */
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#define GPIO027MR01 (3 << 22) /* Match 0.1 (Timer 0) */
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#define GPIO028 (0 << 24)
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#define GPIO028AD01 (1 << 24) /* AD0.1 */
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#define GPIO028CR02 (2 << 24) /* Capture 0.2 (Timer 0) */
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#define GPIO028MR02 (3 << 24) /* Match 0.2 (Timer 0) */
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#define GPIO029 (0 << 26)
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#define GPIO029AD02 (1 << 26) /* AD0.2 */
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#define GPIO029CR03 (2 << 26) /* Capture 0.3 (Timer 0) */
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#define GPIO029MR03 (3 << 26) /* Match 0.3 (Timer 0) */
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#define GPIO030 (0 << 28)
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#define GPIO030AD03 (1 << 28) /* AD0.3 */
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#define GPIO030EINT3 (2 << 28)
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#define GPIO030CR00 (3 << 28) /* Capture 0.0 (Timer 0) */
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#define GPIO031 (0 << 30)
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/*----------- PINSEL2 Bit Definitions ---------*/
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#define GPIO_DEBUG (1 << 2) /* P1.31-26 used for Debug */
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#define GPIO_TRACE (1 << 3) /* P1.25-16 used for Trace */
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/*---------------------------*/
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/* GPIO Register Definitions */
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/*---------------------------*/
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#define GPIO_BASE 0xE0028000
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#define IO0PIN __REG32(GPIO_BASE + 0x00) /* Pin Value Register */
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#define IO0SET __REG32(GPIO_BASE + 0x04) /* Output Set Register */
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#define IO0DIR __REG32(GPIO_BASE + 0x08) /* Direction Control Register */
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#define IO0CLR __REG32(GPIO_BASE + 0x0C) /* Output Clear Register */
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#define IO1PIN __REG32(GPIO_BASE + 0x10) /* Pin Value Register */
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#define IO1SET __REG32(GPIO_BASE + 0x14) /* Output Set Register */
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#define IO1DIR __REG32(GPIO_BASE + 0x18) /* Direction Control Register */
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#define IO1CLR __REG32(GPIO_BASE + 0x1C) /* Output Clear Register */
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/*-----------------------*/
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/* UART Bits Definitions */
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/*-----------------------*/
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#define UIER_RBR (1 << 0) /* Receive Buffer Ready */
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#define UIER_THRE (1 << 1) /* Transmit Hold Register Empty */
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#define UIER_RLS (1 << 2) /* Rx Line Status */
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#define UIIR_NOPEND 0x01 /* No Pending Interrupts */
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#define UIIR_THRE 0x02 /* Tx Hold Register Empty */
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#define UIIR_RDA 0x04 /* Receive Data Available */
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#define UIIR_RLS 0x06 /* Receive Line Status */
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#define UIIR_CTI 0x0C /* Character Timeout Indicator */
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#define UIIR_IMSK 0x0F /* Mask for Interrupt cause */
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#define ULCR_CHRL (0x00 << 0) /* Byte Length */
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#define ULCR_CHRL_5 (0x00 << 0) /* 5 bits */
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#define ULCR_CHRL_6 (0x01 << 0) /* 6 bits */
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#define ULCR_CHRL_7 (0x02 << 0) /* 7 bits */
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#define ULCR_CHRL_8 (0x03 << 0) /* 8 bits */
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#define ULCR_NBSTOP (1 << 2) /* Stop Bit Number */
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#define ULCR_NBSTOP_1 (0 << 2) /* 1 Stop Bit */
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#define ULCR_NBSTOP_1_5 (1 << 2) /* 1.5 Stop Bits at 5 bits */
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#define ULCR_NBSTOP_2 (1 << 2) /* 2 Stop Bits */
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#define ULCR_PAREN (1 << 3) /* Parity Enable */
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#define ULCR_PODD (0x00 << 4) /* Odd parity */
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#define ULCR_PEVEN (0x01 << 4) /* Even parity */
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#define ULCR_FORC1 (0x02 << 4) /* Forced "1" stick parity */
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#define ULCR_FORC0 (0x03 << 4) /* Forced "0" stick parity */
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#define ULCR_BREAK (1 << 6) /* Enable break transmission */
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#define ULCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
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#define DATA8BIT ULCR_CHRL_8
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#define ULSR_RDR (1 << 0) /* Receiver Data Ready */
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#define ULSR_OE (1 << 1) /* Overrun Error */
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#define ULSR_PE (1 << 2) /* Parity Error */
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#define ULSR_FE (1 << 3) /* Framing Error */
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#define ULSR_BI (1 << 4) /* Break Interrupt */
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#define ULSR_THRE (1 << 5) /* Transmitter Holding Register Empty */
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#define ULSR_TEMT (1 << 6) /* Transmitter Empty */
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#define ULSR_RXFE (1 << 7) /* Error in Rx FIFO */
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#define ULSR_MASK_ERROR (ULSR_OE | ULSR_PE | ULSR_FE)
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#define FIFOEN (1 << 0) /* FIFO Enable */
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#define RXFIFOR (1 << 1) /* Rx FIFO Reset */
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#define TXFIFOR (1 << 2) /* Tx FIFO Reset */
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#define TRLVL0 (0x00 << 6)
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#define TRLVL1 (0x01 << 6)
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#define TRLVL2 (0x02 << 6)
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#define TRLVL3 (0x03 << 6)
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/*---------------------------*/
497
/* UART Register Definitions */
498
/*---------------------------*/
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#define UART0_BASE 0xE000C000
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#define U0RBR __REG32(UART0_BASE + 0x00) /* Receiver Buffer Register */
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#define U0THR __REG32(UART0_BASE + 0x00) /* Transmit Holding Register */
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#define U0DLL __REG32(UART0_BASE + 0x00) /* Divisor Latch LSB */
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#define U0IER __REG32(UART0_BASE + 0x04) /* Interrupt Enable Register */
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#define U0DLM __REG32(UART0_BASE + 0x04) /* Divisor Latch MSB */
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#define U0IIR __REG32(UART0_BASE + 0x08) /* Interrupt ID Register */
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#define U0FCR __REG32(UART0_BASE + 0x08) /* FIFO Control Register */
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#define U0LCR __REG32(UART0_BASE + 0x0C) /* Line Control Register */
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#define U0LSR __REG32(UART0_BASE + 0x14) /* Line Status Register */
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#define U0SCR __REG32(UART0_BASE + 0x1C) /* Scratch Pad Register */
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#define UART1_BASE 0xE0010000
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#define U1RBR __REG32(UART1_BASE + 0x00) /* Receiver Buffer Register */
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#define U1THR __REG32(UART1_BASE + 0x00) /* Transmit Holding Register */
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#define U1DLL __REG32(UART1_BASE + 0x00) /* Divisor Latch LSB */
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#define U1IER __REG32(UART1_BASE + 0x04) /* Interrupt Enable Register */
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#define U1DLM __REG32(UART1_BASE + 0x04) /* Divisor Latch MSB */
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#define U1IIR __REG32(UART1_BASE + 0x08) /* Interrupt ID Register */
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#define U1FCR __REG32(UART1_BASE + 0x08) /* FIFO Control Register */
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#define U1LCR __REG32(UART1_BASE + 0x0C) /* Line Control Register */
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#define U1MCR __REG32(UART1_BASE + 0x10) /* Modem Control Register */
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#define U1LSR __REG32(UART1_BASE + 0x14) /* Line Status Register */
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#define U1MSR __REG32(UART1_BASE + 0x18) /* Modem Status Register */
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#define U1SCR __REG32(UART1_BASE + 0x1C) /* Scratch Pad Register */
532
/*--------------------------*/
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/* I2C Register Definitions */
534
/*--------------------------*/
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#define I2C0_BASE 0xE001C000
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#define I2C0CONSET __REG32(I2C0_BASE + 0x00) /* Control Set Register */
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#define I2C0STAT __REG32(I2C0_BASE + 0x04) /* Status Register */
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#define I2C0DAT __REG32(I2C0_BASE + 0x08) /* Data Register */
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#define I2C0ADR __REG32(I2C0_BASE + 0x0C) /* Slave Address Register */
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#define I2C0SCLH __REG32(I2C0_BASE + 0x10) /* SCL Duty Cycle High Word */
542
#define I2C0SCLL __REG32(I2C0_BASE + 0x14) /* SCL Duty Cycle Low Word */
543
#define I2C0CONCLR __REG32(I2C0_BASE + 0x18) /* Control Clear Register */
545
#define I2C1_BASE 0xE005C000
547
#define I2C1CONSET __REG32(I2C1_BASE + 0x00) /* Control Set Register */
548
#define I2C1STAT __REG32(I2C1_BASE + 0x04) /* Status Register */
549
#define I2C1DAT __REG32(I2C1_BASE + 0x08) /* Data Register */
550
#define I2C1ADR __REG32(I2C1_BASE + 0x0C) /* Slave Address Register */
551
#define I2C1SCLH __REG32(I2C1_BASE + 0x10) /* SCL Duty Cycle High Word */
552
#define I2C1SCLL __REG32(I2C1_BASE + 0x14) /* SCL Duty Cycle Low Word */
553
#define I2C1CONCLR __REG32(I2C1_BASE + 0x18) /* Control Clear Register */
555
/*---------------------------------------*/
556
/* Serial Peripheral Interface Registers */
557
/*---------------------------------------*/
558
#define SPI0_BASE 0xE0020000 /* SPI 0 */
560
#define S0SPCR __REG32(SPI0_BASE + 0x00) /* Control Register */
561
#define S0SPSR __REG32(SPI0_BASE + 0x04) /* Status Register */
562
#define S0SPDR __REG32(SPI0_BASE + 0x08) /* Data Register */
563
#define S0SPCCR __REG32(SPI0_BASE + 0x0C) /* Clock Count Register */
564
#define S0SPINT __REG32(SPI0_BASE + 0x1C) /* Interrupt Flag */
566
#define SSP_BASE 0xE0068000 /* SSP (SPI 1) */
568
#define SSPCR0 __REG32(SSP_BASE + 0x00) /* Control Register 0 */
569
#define SSPCR1 __REG32(SSP_BASE + 0x04) /* Control Register 1 */
570
#define SSPDR __REG32(SSP_BASE + 0x08) /* Data Register */
571
#define SSPSR __REG32(SSP_BASE + 0x0C) /* Status Register */
572
#define SSPCPSR __REG32(SSP_BASE + 0x10) /* Clock Prescale Register */
573
#define SSPIMSC __REG32(SSP_BASE + 0x14) /* Interrupt Mask Set and Clear Register */
574
#define SSPRIS __REG32(SSP_BASE + 0x18) /* Raw Interrupt Status Register */
575
#define SSPMIS __REG32(SSP_BASE + 0x1C) /* Masked Interrupt Status Register (RO) */
576
#define SSPICR __REG32(SSP_BASE + 0x20) /* Interrupt Clear Register (WO) */
579
/*----------------------------*/
580
/* Timer Register Definitions */
581
/*----------------------------*/
584
#define TIMER0_BASE 0xE0004000
585
#define T0_BASE TIMER0_BASE
587
#define T0IR __REG32(TIMER0_BASE + 0x00) /* Interrupt Register */
588
#define T0TCR __REG32(TIMER0_BASE + 0x04) /* Control Register */
589
#define T0TC __REG32(TIMER0_BASE + 0x08) /* Counter value */
590
#define T0PR __REG32(TIMER0_BASE + 0x0C) /* Prescale Register */
591
#define T0PC __REG32(TIMER0_BASE + 0x10) /* Prescale Counter */
592
#define T0MCR __REG32(TIMER0_BASE + 0x14) /* Match Control Register */
593
#define T0MR0 __REG32(TIMER0_BASE + 0x18) /* Match Register 0 */
594
#define T0MR1 __REG32(TIMER0_BASE + 0x1C) /* Match Register 1 */
595
#define T0MR2 __REG32(TIMER0_BASE + 0x20) /* Match Register 2 */
596
#define T0MR3 __REG32(TIMER0_BASE + 0x24) /* Match Register 3 */
597
#define T0CCR __REG32(TIMER0_BASE + 0x28) /* Capture Control Register */
598
#define T0CR0 __REG32(TIMER0_BASE + 0x2C) /* Capture Register 0 */
599
#define T0CR1 __REG32(TIMER0_BASE + 0x30) /* Capture Register 1 */
600
#define T0CR2 __REG32(TIMER0_BASE + 0x34) /* Capture Register 2 */
601
#define T0CR3 __REG32(TIMER0_BASE + 0x38) /* Capture Register 3 */
602
#define T0EMR __REG32(TIMER0_BASE + 0x3C) /* External Match Register */
604
#define T0CTCR __REG32(TIMER0_BASE + 0x70) /* Count Control Register */
607
#define TIMER1_BASE 0xE0008000
608
#define T1_BASE TIMER1_BASE
610
#define T1IR __REG32(TIMER1_BASE + 0x00) /* Interrupt Register */
611
#define T1TCR __REG32(TIMER1_BASE + 0x04) /* Control Register */
612
#define T1TC __REG32(TIMER1_BASE + 0x08) /* Counter value */
613
#define T1PR __REG32(TIMER1_BASE + 0x0C) /* Prescale Register */
614
#define T1PC __REG32(TIMER1_BASE + 0x10) /* Prescale Counter */
615
#define T1MCR __REG32(TIMER1_BASE + 0x14) /* Match Control Register */
616
#define T1MR0 __REG32(TIMER1_BASE + 0x18) /* Match Register 0 */
617
#define T1MR1 __REG32(TIMER1_BASE + 0x1C) /* Match Register 1 */
618
#define T1MR2 __REG32(TIMER1_BASE + 0x20) /* Match Register 2 */
619
#define T1MR3 __REG32(TIMER1_BASE + 0x24) /* Match Register 3 */
620
#define T1CCR __REG32(TIMER1_BASE + 0x28) /* Capture Control Register */
621
#define T1CR0 __REG32(TIMER1_BASE + 0x2C) /* Capture Register 0 */
622
#define T1CR1 __REG32(TIMER1_BASE + 0x30) /* Capture Register 1 */
623
#define T1CR2 __REG32(TIMER1_BASE + 0x34) /* Capture Register 2 */
624
#define T1CR3 __REG32(TIMER1_BASE + 0x38) /* Capture Register 3 */
625
#define T1EMR __REG32(TIMER1_BASE + 0x3C) /* External Match Register */
627
#define T1CTCR __REG32(TIMER1_BASE + 0x70) /* Count Control Register */
629
/* Timer Interrupt Register bits */
630
#define TIR_MR0 (1 << 0) /* Match Channel 0 */
631
#define TIR_MR1 (1 << 1) /* Match Channel 1 */
632
#define TIR_MR2 (1 << 2) /* Match Channel 2 */
633
#define TIR_MR3 (1 << 3) /* Match Channel 3 */
634
#define TIR_CR0 (1 << 4) /* Capture Channel 0 */
635
#define TIR_CR1 (1 << 5) /* Capture Channel 1 */
636
#define TIR_CR2 (1 << 6) /* Capture Channel 2 */
637
#define TIR_CR3 (1 << 7) /* Capture Channel 3 */
639
/* Timer Control Register bits */
640
#define TCR_CTEN (1 << 0) /* Counter Enable */
641
#define TCR_CTRST (1 << 1) /* Counter Reset */
643
/* Timer Match Control Register bits */
644
#define TMCR_MR0I (1 << 0) /* Interrupt on MR0 */
645
#define TMCR_MR0R (1 << 1) /* Reset on MR0 */
646
#define TMCR_MR0S (1 << 2) /* Stop on MR0 */
647
#define TMCR_MR1I (1 << 3) /* Interrupt on MR1 */
648
#define TMCR_MR1R (1 << 4) /* Reset on MR1 */
649
#define TMCR_MR1S (1 << 5) /* Stop on MR1 */
650
#define TMCR_MR2I (1 << 6) /* Interrupt on MR2 */
651
#define TMCR_MR2R (1 << 7) /* Reset on MR2 */
652
#define TMCR_MR2S (1 << 8) /* Stop on MR2 */
653
#define TMCR_MR3I (1 << 9) /* Interrupt on MR3 */
654
#define TMCR_MR3R (1 << 10) /* Reset on MR3 */
655
#define TMCR_MR3S (1 << 11) /* Stop on MR3 */
657
/* Timer Capture Control Register bits */
658
#define TCCR_CAP0RE (1 << 0) /* CR0 Rising Edge */
659
#define TCCR_CAP0FE (1 << 1) /* CR0 Falling Edge */
660
#define TCCR_CAP0I (1 << 2) /* Interrupt on CR0 */
661
#define TCCR_CAP1RE (1 << 3) /* CR1 Rising Edge */
662
#define TCCR_CAP1FE (1 << 4) /* CR1 Falling Edge */
663
#define TCCR_CAP1I (1 << 5) /* Interrupt on CR1 */
664
#define TCCR_CAP2RE (1 << 6) /* CR2 Rising Edge */
665
#define TCCR_CAP2FE (1 << 7) /* CR2 Falling Edge */
666
#define TCCR_CAP2I (1 << 8) /* Interrupt on CR2 */
667
#define TCCR_CAP3RE (1 << 9) /* CR3 Rising Edge */
668
#define TCCR_CAP3FE (1 << 10) /* CR3 Falling Edge */
669
#define TCCR_CAP3I (1 << 11) /* Interrupt on CR3 */
672
/*--------------------------*/
673
/* PWM Register Definitions */
674
/*--------------------------*/
676
#define PWM_BASE 0xE0014000
678
#define PWMIR __REG32(PWM_BASE + 0x00) /* Interrupt Register */
679
#define PWMTCR __REG32(PWM_BASE + 0x04) /* Timer Control Register */
680
#define PWMTC __REG32(PWM_BASE + 0x08) /* Timer Counter */
681
#define PWMPR __REG32(PWM_BASE + 0x0C) /* Prescale Register */
682
#define PWMPC __REG32(PWM_BASE + 0x10) /* Prescale Counter */
683
#define PWMMCR __REG32(PWM_BASE + 0x14) /* Match Control Register */
684
#define PWMMR0 __REG32(PWM_BASE + 0x18) /* Match Register 0 */
685
#define PWMMR1 __REG32(PWM_BASE + 0x1C) /* Match Register 1 */
686
#define PWMMR2 __REG32(PWM_BASE + 0x20) /* Match Register 2 */
687
#define PWMMR3 __REG32(PWM_BASE + 0x24) /* Match Register 3 */
688
#define PWMMR4 __REG32(PWM_BASE + 0x40) /* Match Register 4 */
689
#define PWMMR5 __REG32(PWM_BASE + 0x44) /* Match Register 5 */
690
#define PWMMR6 __REG32(PWM_BASE + 0x48) /* Match Register 6 */
691
#define PWMPCR __REG32(PWM_BASE + 0x4C) /* Control Register */
692
#define PWMLER __REG32(PWM_BASE + 0x50) /* Latch Enable Register */
695
/*--------------------------*/
696
/* ADC Register Definitions */
697
/*--------------------------*/
698
#define ADC0_BASE 0xE0034000 /* Analog to Digital Converter 0 */
700
#define AD0CR __REG32(ADC0_BASE + 0x00) /* Control Register */
701
#define AD0GDR __REG32(ADC0_BASE + 0x04) /* Global Data Register */
702
#define AD0GSR __REG32(ADC0_BASE + 0x08) /* Global Start Register */
703
#define AD0INTEN __REG32(ADC0_BASE + 0x0C) /* Interrupt Enable Register */
704
#define AD0DR0 __REG32(ADC0_BASE + 0x10) /* Channel 0 Data Register */
705
#define AD0DR1 __REG32(ADC0_BASE + 0x14) /* Channel 1 Data Register */
706
#define AD0DR2 __REG32(ADC0_BASE + 0x18) /* Channel 2 Data Register */
707
#define AD0DR3 __REG32(ADC0_BASE + 0x1C) /* Channel 3 Data Register */
708
#define AD0DR4 __REG32(ADC0_BASE + 0x20) /* Channel 4 Data Register */
709
#define AD0DR5 __REG32(ADC0_BASE + 0x24) /* Channel 5 Data Register */
710
#define AD0DR6 __REG32(ADC0_BASE + 0x28) /* Channel 6 Data Register */
711
#define AD0DR7 __REG32(ADC0_BASE + 0x2C) /* Channel 7 Data Register */
712
#define AD0STAT __REG32(ADC0_BASE + 0x30) /* Status Register */
714
#define ADC1_BASE 0xE0060000 /* Analog to Digital Converter 1 */
716
#define AD1CR __REG32(ADC1_BASE + 0x00) /* Control Register */
717
#define AD1GDR __REG32(ADC1_BASE + 0x04) /* Global Data Register */
718
#define AD1INTEN __REG32(ADC1_BASE + 0x0C) /* Interrupt Enable Register */
719
#define AD1DR0 __REG32(ADC1_BASE + 0x10) /* Channel 0 Data Register */
720
#define AD1DR1 __REG32(ADC1_BASE + 0x14) /* Channel 1 Data Register */
721
#define AD1DR2 __REG32(ADC1_BASE + 0x18) /* Channel 2 Data Register */
722
#define AD1DR3 __REG32(ADC1_BASE + 0x1C) /* Channel 3 Data Register */
723
#define AD1DR4 __REG32(ADC1_BASE + 0x20) /* Channel 4 Data Register */
724
#define AD1DR5 __REG32(ADC1_BASE + 0x24) /* Channel 5 Data Register */
725
#define AD1DR6 __REG32(ADC1_BASE + 0x28) /* Channel 6 Data Register */
726
#define AD1DR7 __REG32(ADC1_BASE + 0x2C) /* Channel 7 Data Register */
727
#define AD1STAT __REG32(ADC1_BASE + 0x30) /* Status Register */
730
/*--------------------------*/
731
/* DAC Register Definitions */
732
/*--------------------------*/
733
#define DAC_BASE 0xE006C000 /* Digital to Analog Converter */
735
#define DAC_DACR __REG32(DAC_BASE + 0x00) /* DAC Register */
738
/*----------------------------*/
739
/* Real Time Clock Registers */
740
/*----------------------------*/
741
#define RTC_BASE 0xE0024000
743
#define RTC_ILR __REG32(RTC_BASE + 0x00) /* Interrupt Location Reg */
744
#define RTC_CTC __REG32(RTC_BASE + 0x04) /* Clock Tick Counter */
745
#define RTC_CCR __REG32(RTC_BASE + 0x08) /* Clock Control Register */
746
#define RTC_CIIR __REG32(RTC_BASE + 0x0C) /* Counter Incr. Interrpt Reg */
747
#define RTC_AMR __REG32(RTC_BASE + 0x10) /* Alarm Mask Register */
748
#define RTC_CTIME0 __REG32(RTC_BASE + 0x14) /* Time Register 0 */
749
#define RTC_CTIME1 __REG32(RTC_BASE + 0x18) /* Time Register 1 */
750
#define RTC_CTIME2 __REG32(RTC_BASE + 0x1C) /* Time Register 2 */
751
#define RTC_SEC __REG32(RTC_BASE + 0x20) /* Seconds Register */
752
#define RTC_MIN __REG32(RTC_BASE + 0x24) /* Minutes Register */
753
#define RTC_HOUR __REG32(RTC_BASE + 0x28) /* Hours Register */
754
#define RTC_DOM __REG32(RTC_BASE + 0x2C) /* Day Of Month Register */
755
#define RTC_DOW __REG32(RTC_BASE + 0x30) /* Day Of Week Register */
756
#define RTC_DOY __REG32(RTC_BASE + 0x34) /* Day Of Year Register */
757
#define RTC_MONTH __REG32(RTC_BASE + 0x38) /* Months Register */
758
#define RTC_YEAR __REG32(RTC_BASE + 0x3C) /* Year Register */
759
#define RTC_ALSEC __REG32(RTC_BASE + 0x60) /* Alarm Seconds Register */
760
#define RTC_ALMIN __REG32(RTC_BASE + 0x64) /* Alarm Minutes Register */
761
#define RTC_ALHOUR __REG32(RTC_BASE + 0x68) /* Alarm Hours Register */
762
#define RTC_ALDOM __REG32(RTC_BASE + 0x6C) /* Alarm Day Of Month Reg */
763
#define RTC_ALDOW __REG32(RTC_BASE + 0x70) /* Alarm Day Of Week Register */
764
#define RTC_ALDOY __REG32(RTC_BASE + 0x74) /* Alarm Day Of Year Register */
765
#define RTC_ALMONTH __REG32(RTC_BASE + 0x78) /* Alarm Months Register */
766
#define RTC_ALYEAR __REG32(RTC_BASE + 0x7C) /* Alarm Year Register */
767
#define RTC_PREINT __REG32(RTC_BASE + 0x80) /* Prescale Value, Integer */
768
#define RTC_PREFRAC __REG32(RTC_BASE + 0x84) /* Prescale Value, Fraction */
771
/*--------------------------*/
772
/* WDT Register Definitions */
773
/*--------------------------*/
775
#define WDT_BASE 0xE0000000
777
#define WDMOD __REG32(WD_BASE + 0x00) /* Mode Register */
778
#define WDTC __REG32(WD_BASE + 0x04) /* Timer Constant Register */
779
#define WDFEED __REG32(WD_BASE + 0x08) /* Feed Sequence Register */
780
#define WDTV __REG32(WD_BASE + 0x0C) /* Timer Value Register */
782
#endif /* __LPC213X_H__ */
added
removed
src/plugins/scriptedwizard/resources/arm/files/olimex-lpc213x/h/lpc213x.h
