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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity shiftregister is
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left : boolean := false -- so shift right
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q : out std_logic_vector
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architecture behavioral of shiftregister is
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constant crcpoly : std_logic_vector(7 downto 0) := x"8D";
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type utxstates is (idle, data, parity, stop);
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signal utxstate : utxstates;
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shift: process ( rst, clk ) begin
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elsif clk'event and clk = '1' then
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q <= q(q'left - 1 downto q'right) & d;
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q <= d & q(q'left downto q'right + 1);