1
/* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
3
* Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
4
* Copyright (C) 2002, 2006 David S. Miller (davem@davemloft.net)
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* Rewrote buffer handling to use CIRC(Circular Buffer) macros.
7
* Maxim Krasnyanskiy <maxk@qualcomm.com>
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* Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
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* rates to be programmed into the UART. Also eliminated a lot of
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* duplicated code in the console setup.
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* Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
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* Ported to new 2.5.x UART layer.
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* David S. Miller <davem@davemloft.net>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/major.h>
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#include <linux/string.h>
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#include <linux/ptrace.h>
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#include <linux/ioport.h>
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#include <linux/circ_buf.h>
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#include <linux/serial.h>
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#include <linux/sysrq.h>
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#include <linux/console.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/of_device.h>
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#if defined(CONFIG_SERIAL_SUNSAB_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
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#include <linux/serial_core.h>
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struct uart_sunsab_port {
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struct uart_port port; /* Generic UART port */
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union sab82532_async_regs __iomem *regs; /* Chip registers */
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unsigned long irqflags; /* IRQ state flags */
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int dsr; /* Current DSR state */
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unsigned int cec_timeout; /* Chip poll timeout... */
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unsigned int tec_timeout; /* likewise */
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unsigned char interrupt_mask0;/* ISR0 masking */
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unsigned char interrupt_mask1;/* ISR1 masking */
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unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */
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unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */
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unsigned int gis_shift;
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int type; /* SAB82532 version */
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/* Setting configuration bits while the transmitter is active
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* can cause garbage characters to get emitted by the chip.
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* Therefore, we cache such writes here and do the real register
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* write the next time the transmitter becomes idle.
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unsigned int cached_ebrg;
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unsigned char cached_mode;
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unsigned char cached_pvr;
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unsigned char cached_dafo;
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* This assumes you have a 29.4912 MHz clock for your UART.
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#define SAB_BASE_BAUD ( 29491200 / 16 )
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static char *sab82532_version[16] = {
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"V1.0", "V2.0", "V3.2", "V(0x03)",
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"V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
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"V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
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"V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
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#define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
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#define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */
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#define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */
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#define SAB82532_XMIT_FIFO_SIZE 32
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static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
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int timeout = up->tec_timeout;
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while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
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static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
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int timeout = up->cec_timeout;
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while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
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static struct tty_struct *
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receive_chars(struct uart_sunsab_port *up,
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union sab82532_irq_status *stat)
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struct tty_struct *tty = NULL;
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unsigned char buf[32];
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int saw_console_brk = 0;
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if (up->port.state != NULL) /* Unopened serial console */
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tty = up->port.state->port.tty;
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/* Read number of BYTES (Character + Status) available. */
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if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
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count = SAB82532_RECV_FIFO_SIZE;
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if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
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count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
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/* Issue a FIFO read command in case we where idle. */
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if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
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writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
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if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
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for (i = 0; i < count; i++)
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buf[i] = readb(&up->regs->r.rfifo[i]);
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/* Issue Receive Message Complete command. */
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writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
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/* Count may be zero for BRK, so we check for it here */
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if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
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(up->port.line == up->port.cons->index))
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for (i = 0; i < count; i++) {
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unsigned char ch = buf[i], flag;
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uart_handle_sysrq_char(&up->port, ch);
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up->port.icount.rx++;
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if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
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SAB82532_ISR0_RFO)) ||
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unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
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* For statistics only
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if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
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stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
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up->port.icount.brk++;
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* We do the SysRQ and SAK checking
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* here because otherwise the break
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* may get masked by ignore_status_mask
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* or read_status_mask.
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if (uart_handle_break(&up->port))
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} else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
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up->port.icount.parity++;
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else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
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up->port.icount.frame++;
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if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
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up->port.icount.overrun++;
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* Mask off conditions which should be ingored.
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stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
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stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
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if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
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} else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
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else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
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if (uart_handle_sysrq_char(&up->port, ch))
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if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
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(stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
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tty_insert_flip_char(tty, ch, flag);
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if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
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tty_insert_flip_char(tty, 0, TTY_OVERRUN);
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static void sunsab_stop_tx(struct uart_port *);
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static void sunsab_tx_idle(struct uart_sunsab_port *);
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static void transmit_chars(struct uart_sunsab_port *up,
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union sab82532_irq_status *stat)
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struct circ_buf *xmit = &up->port.state->xmit;
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if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
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up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
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writeb(up->interrupt_mask1, &up->regs->w.imr1);
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set_bit(SAB82532_ALLS, &up->irqflags);
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#if 0 /* bde@nwlink.com says this check causes problems */
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if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
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if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
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set_bit(SAB82532_XPR, &up->irqflags);
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if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
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up->interrupt_mask1 |= SAB82532_IMR1_XPR;
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writeb(up->interrupt_mask1, &up->regs->w.imr1);
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up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
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writeb(up->interrupt_mask1, &up->regs->w.imr1);
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clear_bit(SAB82532_ALLS, &up->irqflags);
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/* Stuff 32 bytes into Transmit FIFO. */
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clear_bit(SAB82532_XPR, &up->irqflags);
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for (i = 0; i < up->port.fifosize; i++) {
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writeb(xmit->buf[xmit->tail],
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&up->regs->w.xfifo[i]);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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up->port.icount.tx++;
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if (uart_circ_empty(xmit))
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/* Issue a Transmit Frame command. */
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writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(&up->port);
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if (uart_circ_empty(xmit))
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sunsab_stop_tx(&up->port);
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static void check_status(struct uart_sunsab_port *up,
285
union sab82532_irq_status *stat)
287
if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
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uart_handle_dcd_change(&up->port,
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!(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
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if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
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uart_handle_cts_change(&up->port,
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(readb(&up->regs->r.star) & SAB82532_STAR_CTS));
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if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
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up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
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up->port.icount.dsr++;
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wake_up_interruptible(&up->port.state->port.delta_msr_wait);
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static irqreturn_t sunsab_interrupt(int irq, void *dev_id)
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struct uart_sunsab_port *up = dev_id;
306
struct tty_struct *tty;
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union sab82532_irq_status status;
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spin_lock_irqsave(&up->port.lock, flags);
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gis = readb(&up->regs->r.gis) >> up->gis_shift;
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status.sreg.isr0 = readb(&up->regs->r.isr0);
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status.sreg.isr1 = readb(&up->regs->r.isr1);
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if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
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SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
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(status.sreg.isr1 & SAB82532_ISR1_BRK))
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tty = receive_chars(up, &status);
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if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
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(status.sreg.isr1 & SAB82532_ISR1_CSC))
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check_status(up, &status);
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if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
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transmit_chars(up, &status);
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spin_unlock_irqrestore(&up->port.lock, flags);
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tty_flip_buffer_push(tty);
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/* port->lock is not held. */
342
static unsigned int sunsab_tx_empty(struct uart_port *port)
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struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
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/* Do not need a lock for a state test like this. */
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if (test_bit(SAB82532_ALLS, &up->irqflags))
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/* port->lock held by caller. */
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static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
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struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
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if (mctrl & TIOCM_RTS) {
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up->cached_mode &= ~SAB82532_MODE_FRTS;
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up->cached_mode |= SAB82532_MODE_RTS;
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up->cached_mode |= (SAB82532_MODE_FRTS |
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if (mctrl & TIOCM_DTR) {
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up->cached_pvr &= ~(up->pvr_dtr_bit);
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up->cached_pvr |= up->pvr_dtr_bit;
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set_bit(SAB82532_REGS_PENDING, &up->irqflags);
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if (test_bit(SAB82532_XPR, &up->irqflags))
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/* port->lock is held by caller and interrupts are disabled. */
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static unsigned int sunsab_get_mctrl(struct uart_port *port)
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struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
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val = readb(&up->regs->r.pvr);
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result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
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val = readb(&up->regs->r.vstr);
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result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
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val = readb(&up->regs->r.star);
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result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
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/* port->lock held by caller. */
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static void sunsab_stop_tx(struct uart_port *port)
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struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
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up->interrupt_mask1 |= SAB82532_IMR1_XPR;
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writeb(up->interrupt_mask1, &up->regs->w.imr1);
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/* port->lock held by caller. */
410
static void sunsab_tx_idle(struct uart_sunsab_port *up)
412
if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
415
clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
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writeb(up->cached_mode, &up->regs->rw.mode);
417
writeb(up->cached_pvr, &up->regs->rw.pvr);
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writeb(up->cached_dafo, &up->regs->w.dafo);
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writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
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tmp = readb(&up->regs->rw.ccr2);
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tmp |= (up->cached_ebrg >> 2) & 0xc0;
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writeb(tmp, &up->regs->rw.ccr2);
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/* port->lock held by caller. */
429
static void sunsab_start_tx(struct uart_port *port)
431
struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
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struct circ_buf *xmit = &up->port.state->xmit;
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up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
436
writeb(up->interrupt_mask1, &up->regs->w.imr1);
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if (!test_bit(SAB82532_XPR, &up->irqflags))
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clear_bit(SAB82532_ALLS, &up->irqflags);
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clear_bit(SAB82532_XPR, &up->irqflags);
444
for (i = 0; i < up->port.fifosize; i++) {
445
writeb(xmit->buf[xmit->tail],
446
&up->regs->w.xfifo[i]);
447
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
448
up->port.icount.tx++;
449
if (uart_circ_empty(xmit))
453
/* Issue a Transmit Frame command. */
455
writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
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/* port->lock is not held. */
459
static void sunsab_send_xchar(struct uart_port *port, char ch)
461
struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
464
spin_lock_irqsave(&up->port.lock, flags);
467
writeb(ch, &up->regs->w.tic);
469
spin_unlock_irqrestore(&up->port.lock, flags);
472
/* port->lock held by caller. */
473
static void sunsab_stop_rx(struct uart_port *port)
475
struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
477
up->interrupt_mask0 |= SAB82532_ISR0_TCD;
478
writeb(up->interrupt_mask1, &up->regs->w.imr0);
481
/* port->lock held by caller. */
482
static void sunsab_enable_ms(struct uart_port *port)
484
/* For now we always receive these interrupts. */
487
/* port->lock is not held. */
488
static void sunsab_break_ctl(struct uart_port *port, int break_state)
490
struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
494
spin_lock_irqsave(&up->port.lock, flags);
496
val = up->cached_dafo;
498
val |= SAB82532_DAFO_XBRK;
500
val &= ~SAB82532_DAFO_XBRK;
501
up->cached_dafo = val;
503
set_bit(SAB82532_REGS_PENDING, &up->irqflags);
504
if (test_bit(SAB82532_XPR, &up->irqflags))
507
spin_unlock_irqrestore(&up->port.lock, flags);
510
/* port->lock is not held. */
511
static int sunsab_startup(struct uart_port *port)
513
struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
516
int err = request_irq(up->port.irq, sunsab_interrupt,
517
IRQF_SHARED, "sab", up);
521
spin_lock_irqsave(&up->port.lock, flags);
524
* Wait for any commands or immediate characters
530
* Clear the FIFO buffers.
532
writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
534
writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
537
* Clear the interrupt registers.
539
(void) readb(&up->regs->r.isr0);
540
(void) readb(&up->regs->r.isr1);
543
* Now, initialize the UART
545
writeb(0, &up->regs->w.ccr0); /* power-down */
546
writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
547
SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
548
writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
549
writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
550
SAB82532_CCR2_TOE, &up->regs->w.ccr2);
551
writeb(0, &up->regs->w.ccr3);
552
writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
553
up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
555
writeb(up->cached_mode, &up->regs->w.mode);
556
writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
558
tmp = readb(&up->regs->rw.ccr0);
559
tmp |= SAB82532_CCR0_PU; /* power-up */
560
writeb(tmp, &up->regs->rw.ccr0);
563
* Finally, enable interrupts
565
up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
567
writeb(up->interrupt_mask0, &up->regs->w.imr0);
568
up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
569
SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
570
SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
572
writeb(up->interrupt_mask1, &up->regs->w.imr1);
573
set_bit(SAB82532_ALLS, &up->irqflags);
574
set_bit(SAB82532_XPR, &up->irqflags);
576
spin_unlock_irqrestore(&up->port.lock, flags);
581
/* port->lock is not held. */
582
static void sunsab_shutdown(struct uart_port *port)
584
struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
587
spin_lock_irqsave(&up->port.lock, flags);
589
/* Disable Interrupts */
590
up->interrupt_mask0 = 0xff;
591
writeb(up->interrupt_mask0, &up->regs->w.imr0);
592
up->interrupt_mask1 = 0xff;
593
writeb(up->interrupt_mask1, &up->regs->w.imr1);
595
/* Disable break condition */
596
up->cached_dafo = readb(&up->regs->rw.dafo);
597
up->cached_dafo &= ~SAB82532_DAFO_XBRK;
598
writeb(up->cached_dafo, &up->regs->rw.dafo);
600
/* Disable Receiver */
601
up->cached_mode &= ~SAB82532_MODE_RAC;
602
writeb(up->cached_mode, &up->regs->rw.mode);
607
* If the chip is powered down here the system hangs/crashes during
608
* reboot or shutdown. This needs to be investigated further,
609
* similar behaviour occurs in 2.4 when the driver is configured
610
* as a module only. One hint may be that data is sometimes
611
* transmitted at 9600 baud during shutdown (regardless of the
612
* speed the chip was configured for when the port was open).
616
tmp = readb(&up->regs->rw.ccr0);
617
tmp &= ~SAB82532_CCR0_PU;
618
writeb(tmp, &up->regs->rw.ccr0);
621
spin_unlock_irqrestore(&up->port.lock, flags);
622
free_irq(up->port.irq, up);
626
* This is used to figure out the divisor speeds.
628
* The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
630
* with 0 <= N < 64 and 0 <= M < 16
633
static void calc_ebrg(int baud, int *n_ret, int *m_ret)
644
* We scale numbers by 10 so that we get better accuracy
645
* without having to use floating point. Here we increment m
646
* until n is within the valid range.
648
n = (SAB_BASE_BAUD * 10) / baud;
656
* We try very hard to avoid speeds with M == 0 since they may
657
* not work correctly for XTAL frequences above 10 MHz.
659
if ((m == 0) && ((n & 1) == 0)) {
667
/* Internal routine, port->lock is held and local interrupts are disabled. */
668
static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
669
unsigned int iflag, unsigned int baud,
675
/* Byte size and parity */
676
switch (cflag & CSIZE) {
677
case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
678
case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
679
case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
680
case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
681
/* Never happens, but GCC is too dumb to figure it out */
682
default: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
685
if (cflag & CSTOPB) {
686
dafo |= SAB82532_DAFO_STOP;
690
if (cflag & PARENB) {
691
dafo |= SAB82532_DAFO_PARE;
695
if (cflag & PARODD) {
696
dafo |= SAB82532_DAFO_PAR_ODD;
698
dafo |= SAB82532_DAFO_PAR_EVEN;
700
up->cached_dafo = dafo;
702
calc_ebrg(baud, &n, &m);
704
up->cached_ebrg = n | (m << 6);
706
up->tec_timeout = (10 * 1000000) / baud;
707
up->cec_timeout = up->tec_timeout >> 2;
709
/* CTS flow control flags */
710
/* We encode read_status_mask and ignore_status_mask like so:
712
* ---------------------
713
* | ... | ISR1 | ISR0 |
714
* ---------------------
718
up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
719
SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
721
up->port.read_status_mask |= (SAB82532_ISR1_CSC |
723
SAB82532_ISR1_XPR) << 8;
725
up->port.read_status_mask |= (SAB82532_ISR0_PERR |
727
if (iflag & (BRKINT | PARMRK))
728
up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
731
* Characteres to ignore
733
up->port.ignore_status_mask = 0;
735
up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
737
if (iflag & IGNBRK) {
738
up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
740
* If we're ignoring parity and break indicators,
741
* ignore overruns too (for real raw support).
744
up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
748
* ignore all characters if CREAD is not set
750
if ((cflag & CREAD) == 0)
751
up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
754
uart_update_timeout(&up->port, cflag,
755
(up->port.uartclk / (16 * quot)));
757
/* Now schedule a register update when the chip's
758
* transmitter is idle.
760
up->cached_mode |= SAB82532_MODE_RAC;
761
set_bit(SAB82532_REGS_PENDING, &up->irqflags);
762
if (test_bit(SAB82532_XPR, &up->irqflags))
766
/* port->lock is not held. */
767
static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios,
768
struct ktermios *old)
770
struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
772
unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
773
unsigned int quot = uart_get_divisor(port, baud);
775
spin_lock_irqsave(&up->port.lock, flags);
776
sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
777
spin_unlock_irqrestore(&up->port.lock, flags);
780
static const char *sunsab_type(struct uart_port *port)
782
struct uart_sunsab_port *up = (void *)port;
785
sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
789
static void sunsab_release_port(struct uart_port *port)
793
static int sunsab_request_port(struct uart_port *port)
798
static void sunsab_config_port(struct uart_port *port, int flags)
802
static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
807
static struct uart_ops sunsab_pops = {
808
.tx_empty = sunsab_tx_empty,
809
.set_mctrl = sunsab_set_mctrl,
810
.get_mctrl = sunsab_get_mctrl,
811
.stop_tx = sunsab_stop_tx,
812
.start_tx = sunsab_start_tx,
813
.send_xchar = sunsab_send_xchar,
814
.stop_rx = sunsab_stop_rx,
815
.enable_ms = sunsab_enable_ms,
816
.break_ctl = sunsab_break_ctl,
817
.startup = sunsab_startup,
818
.shutdown = sunsab_shutdown,
819
.set_termios = sunsab_set_termios,
821
.release_port = sunsab_release_port,
822
.request_port = sunsab_request_port,
823
.config_port = sunsab_config_port,
824
.verify_port = sunsab_verify_port,
827
static struct uart_driver sunsab_reg = {
828
.owner = THIS_MODULE,
829
.driver_name = "sunsab",
834
static struct uart_sunsab_port *sunsab_ports;
836
#ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
838
static void sunsab_console_putchar(struct uart_port *port, int c)
840
struct uart_sunsab_port *up = (struct uart_sunsab_port *)port;
843
writeb(c, &up->regs->w.tic);
846
static void sunsab_console_write(struct console *con, const char *s, unsigned n)
848
struct uart_sunsab_port *up = &sunsab_ports[con->index];
852
local_irq_save(flags);
853
if (up->port.sysrq) {
855
} else if (oops_in_progress) {
856
locked = spin_trylock(&up->port.lock);
858
spin_lock(&up->port.lock);
860
uart_console_write(&up->port, s, n, sunsab_console_putchar);
864
spin_unlock(&up->port.lock);
865
local_irq_restore(flags);
868
static int sunsab_console_setup(struct console *con, char *options)
870
struct uart_sunsab_port *up = &sunsab_ports[con->index];
872
unsigned int baud, quot;
875
* The console framework calls us for each and every port
876
* registered. Defer the console setup until the requested
877
* port has been properly discovered. A bit of a hack,
880
if (up->port.type != PORT_SUNSAB)
883
printk("Console: ttyS%d (SAB82532)\n",
884
(sunsab_reg.minor - 64) + con->index);
886
sunserial_console_termios(con, to_of_device(up->port.dev)->node);
888
switch (con->cflag & CBAUD) {
889
case B150: baud = 150; break;
890
case B300: baud = 300; break;
891
case B600: baud = 600; break;
892
case B1200: baud = 1200; break;
893
case B2400: baud = 2400; break;
894
case B4800: baud = 4800; break;
895
default: case B9600: baud = 9600; break;
896
case B19200: baud = 19200; break;
897
case B38400: baud = 38400; break;
898
case B57600: baud = 57600; break;
899
case B115200: baud = 115200; break;
900
case B230400: baud = 230400; break;
901
case B460800: baud = 460800; break;
907
spin_lock_init(&up->port.lock);
910
* Initialize the hardware
912
sunsab_startup(&up->port);
914
spin_lock_irqsave(&up->port.lock, flags);
917
* Finally, enable interrupts
919
up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
920
SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
921
writeb(up->interrupt_mask0, &up->regs->w.imr0);
922
up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
923
SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
924
SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
926
writeb(up->interrupt_mask1, &up->regs->w.imr1);
928
quot = uart_get_divisor(&up->port, baud);
929
sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
930
sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
932
spin_unlock_irqrestore(&up->port.lock, flags);
937
static struct console sunsab_console = {
939
.write = sunsab_console_write,
940
.device = uart_console_device,
941
.setup = sunsab_console_setup,
942
.flags = CON_PRINTBUFFER,
947
static inline struct console *SUNSAB_CONSOLE(void)
949
return &sunsab_console;
952
#define SUNSAB_CONSOLE() (NULL)
953
#define sunsab_console_init() do { } while (0)
956
static int __devinit sunsab_init_one(struct uart_sunsab_port *up,
957
struct of_device *op,
958
unsigned long offset,
961
up->port.line = line;
962
up->port.dev = &op->dev;
964
up->port.mapbase = op->resource[0].start + offset;
965
up->port.membase = of_ioremap(&op->resource[0], offset,
966
sizeof(union sab82532_async_regs),
968
if (!up->port.membase)
970
up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
972
up->port.irq = op->irqs[0];
974
up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
975
up->port.iotype = UPIO_MEM;
977
writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
979
up->port.ops = &sunsab_pops;
980
up->port.type = PORT_SUNSAB;
981
up->port.uartclk = SAB_BASE_BAUD;
983
up->type = readb(&up->regs->r.vstr) & 0x0f;
984
writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
985
writeb(0xff, &up->regs->w.pim);
986
if ((up->port.line & 0x1) == 0) {
987
up->pvr_dsr_bit = (1 << 0);
988
up->pvr_dtr_bit = (1 << 1);
991
up->pvr_dsr_bit = (1 << 3);
992
up->pvr_dtr_bit = (1 << 2);
995
up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
996
writeb(up->cached_pvr, &up->regs->w.pvr);
997
up->cached_mode = readb(&up->regs->rw.mode);
998
up->cached_mode |= SAB82532_MODE_FRTS;
999
writeb(up->cached_mode, &up->regs->rw.mode);
1000
up->cached_mode |= SAB82532_MODE_RTS;
1001
writeb(up->cached_mode, &up->regs->rw.mode);
1003
up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1004
up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1009
static int __devinit sab_probe(struct of_device *op, const struct of_device_id *match)
1012
struct uart_sunsab_port *up;
1015
up = &sunsab_ports[inst * 2];
1017
err = sunsab_init_one(&up[0], op,
1023
err = sunsab_init_one(&up[1], op,
1024
sizeof(union sab82532_async_regs),
1029
sunserial_console_match(SUNSAB_CONSOLE(), op->node,
1030
&sunsab_reg, up[0].port.line,
1033
sunserial_console_match(SUNSAB_CONSOLE(), op->node,
1034
&sunsab_reg, up[1].port.line,
1037
err = uart_add_one_port(&sunsab_reg, &up[0].port);
1041
err = uart_add_one_port(&sunsab_reg, &up[1].port);
1045
dev_set_drvdata(&op->dev, &up[0]);
1052
uart_remove_one_port(&sunsab_reg, &up[0].port);
1054
of_iounmap(&op->resource[0],
1056
sizeof(union sab82532_async_regs));
1058
of_iounmap(&op->resource[0],
1060
sizeof(union sab82532_async_regs));
1065
static int __devexit sab_remove(struct of_device *op)
1067
struct uart_sunsab_port *up = dev_get_drvdata(&op->dev);
1069
uart_remove_one_port(&sunsab_reg, &up[1].port);
1070
uart_remove_one_port(&sunsab_reg, &up[0].port);
1071
of_iounmap(&op->resource[0],
1073
sizeof(union sab82532_async_regs));
1074
of_iounmap(&op->resource[0],
1076
sizeof(union sab82532_async_regs));
1078
dev_set_drvdata(&op->dev, NULL);
1083
static const struct of_device_id sab_match[] = {
1089
.compatible = "sab82532",
1093
MODULE_DEVICE_TABLE(of, sab_match);
1095
static struct of_platform_driver sab_driver = {
1097
.match_table = sab_match,
1099
.remove = __devexit_p(sab_remove),
1102
static int __init sunsab_init(void)
1104
struct device_node *dp;
1106
int num_channels = 0;
1108
for_each_node_by_name(dp, "se")
1110
for_each_node_by_name(dp, "serial") {
1111
if (of_device_is_compatible(dp, "sab82532"))
1116
sunsab_ports = kzalloc(sizeof(struct uart_sunsab_port) *
1117
num_channels, GFP_KERNEL);
1121
err = sunserial_register_minors(&sunsab_reg, num_channels);
1123
kfree(sunsab_ports);
1124
sunsab_ports = NULL;
1130
return of_register_driver(&sab_driver, &of_bus_type);
1133
static void __exit sunsab_exit(void)
1135
of_unregister_driver(&sab_driver);
1136
if (sunsab_reg.nr) {
1137
sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr);
1140
kfree(sunsab_ports);
1141
sunsab_ports = NULL;
1144
module_init(sunsab_init);
1145
module_exit(sunsab_exit);
1147
MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1148
MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1149
MODULE_LICENSE("GPL");