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* linux/drivers/video/omap2/dss/dispc.c
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* Copyright (C) 2009 Nokia Corporation
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* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
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* Some code and ideas taken from drivers/video/omap/ driver
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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#define DSS_SUBSYS_NAME "DISPC"
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#include <linux/kernel.h>
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#include <linux/dma-mapping.h>
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#include <linux/vmalloc.h>
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#include <linux/clk.h>
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#include <linux/jiffies.h>
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#include <linux/seq_file.h>
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#include <linux/delay.h>
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#include <linux/workqueue.h>
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#include <plat/sram.h>
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#include <plat/clock.h>
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#include <plat/display.h>
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#define DISPC_BASE 0x48050400
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#define DISPC_SZ_REGS SZ_1K
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struct dispc_reg { u16 idx; };
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#define DISPC_REG(idx) ((const struct dispc_reg) { idx })
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#define DISPC_REVISION DISPC_REG(0x0000)
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#define DISPC_SYSCONFIG DISPC_REG(0x0010)
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#define DISPC_SYSSTATUS DISPC_REG(0x0014)
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#define DISPC_IRQSTATUS DISPC_REG(0x0018)
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#define DISPC_IRQENABLE DISPC_REG(0x001C)
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#define DISPC_CONTROL DISPC_REG(0x0040)
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#define DISPC_CONFIG DISPC_REG(0x0044)
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#define DISPC_CAPABLE DISPC_REG(0x0048)
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#define DISPC_DEFAULT_COLOR0 DISPC_REG(0x004C)
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#define DISPC_DEFAULT_COLOR1 DISPC_REG(0x0050)
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#define DISPC_TRANS_COLOR0 DISPC_REG(0x0054)
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#define DISPC_TRANS_COLOR1 DISPC_REG(0x0058)
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#define DISPC_LINE_STATUS DISPC_REG(0x005C)
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#define DISPC_LINE_NUMBER DISPC_REG(0x0060)
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#define DISPC_TIMING_H DISPC_REG(0x0064)
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#define DISPC_TIMING_V DISPC_REG(0x0068)
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#define DISPC_POL_FREQ DISPC_REG(0x006C)
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#define DISPC_DIVISOR DISPC_REG(0x0070)
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#define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
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#define DISPC_SIZE_DIG DISPC_REG(0x0078)
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#define DISPC_SIZE_LCD DISPC_REG(0x007C)
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#define DISPC_GFX_BA0 DISPC_REG(0x0080)
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#define DISPC_GFX_BA1 DISPC_REG(0x0084)
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#define DISPC_GFX_POSITION DISPC_REG(0x0088)
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#define DISPC_GFX_SIZE DISPC_REG(0x008C)
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#define DISPC_GFX_ATTRIBUTES DISPC_REG(0x00A0)
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#define DISPC_GFX_FIFO_THRESHOLD DISPC_REG(0x00A4)
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#define DISPC_GFX_FIFO_SIZE_STATUS DISPC_REG(0x00A8)
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#define DISPC_GFX_ROW_INC DISPC_REG(0x00AC)
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#define DISPC_GFX_PIXEL_INC DISPC_REG(0x00B0)
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#define DISPC_GFX_WINDOW_SKIP DISPC_REG(0x00B4)
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#define DISPC_GFX_TABLE_BA DISPC_REG(0x00B8)
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#define DISPC_DATA_CYCLE1 DISPC_REG(0x01D4)
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#define DISPC_DATA_CYCLE2 DISPC_REG(0x01D8)
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#define DISPC_DATA_CYCLE3 DISPC_REG(0x01DC)
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#define DISPC_CPR_COEF_R DISPC_REG(0x0220)
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#define DISPC_CPR_COEF_G DISPC_REG(0x0224)
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#define DISPC_CPR_COEF_B DISPC_REG(0x0228)
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#define DISPC_GFX_PRELOAD DISPC_REG(0x022C)
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/* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
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#define DISPC_VID_REG(n, idx) DISPC_REG(0x00BC + (n)*0x90 + idx)
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#define DISPC_VID_BA0(n) DISPC_VID_REG(n, 0x0000)
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#define DISPC_VID_BA1(n) DISPC_VID_REG(n, 0x0004)
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#define DISPC_VID_POSITION(n) DISPC_VID_REG(n, 0x0008)
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#define DISPC_VID_SIZE(n) DISPC_VID_REG(n, 0x000C)
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#define DISPC_VID_ATTRIBUTES(n) DISPC_VID_REG(n, 0x0010)
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#define DISPC_VID_FIFO_THRESHOLD(n) DISPC_VID_REG(n, 0x0014)
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#define DISPC_VID_FIFO_SIZE_STATUS(n) DISPC_VID_REG(n, 0x0018)
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#define DISPC_VID_ROW_INC(n) DISPC_VID_REG(n, 0x001C)
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#define DISPC_VID_PIXEL_INC(n) DISPC_VID_REG(n, 0x0020)
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#define DISPC_VID_FIR(n) DISPC_VID_REG(n, 0x0024)
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#define DISPC_VID_PICTURE_SIZE(n) DISPC_VID_REG(n, 0x0028)
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#define DISPC_VID_ACCU0(n) DISPC_VID_REG(n, 0x002C)
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#define DISPC_VID_ACCU1(n) DISPC_VID_REG(n, 0x0030)
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/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
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#define DISPC_VID_FIR_COEF_H(n, i) DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
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/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
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#define DISPC_VID_FIR_COEF_HV(n, i) DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
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/* coef index i = {0, 1, 2, 3, 4} */
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#define DISPC_VID_CONV_COEF(n, i) DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
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/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
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#define DISPC_VID_FIR_COEF_V(n, i) DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
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#define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04)
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#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
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DISPC_IRQ_OCP_ERR | \
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DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
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DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
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DISPC_IRQ_SYNC_LOST | \
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DISPC_IRQ_SYNC_LOST_DIGIT)
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#define DISPC_MAX_NR_ISRS 8
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struct omap_dispc_isr_data {
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omap_dispc_isr_t isr;
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#define REG_GET(idx, start, end) \
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FLD_GET(dispc_read_reg(idx), start, end)
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#define REG_FLD_MOD(idx, val, start, end) \
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dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
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static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
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DISPC_VID_ATTRIBUTES(0),
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DISPC_VID_ATTRIBUTES(1) };
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struct dispc_irq_stats {
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unsigned long last_reset;
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struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
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struct work_struct error_work;
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u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
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#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
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spinlock_t irq_stats_lock;
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struct dispc_irq_stats irq_stats;
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static void _omap_dispc_set_irqs(void);
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static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
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__raw_writel(val, dispc.base + idx.idx);
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static inline u32 dispc_read_reg(const struct dispc_reg idx)
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return __raw_readl(dispc.base + idx.idx);
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dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
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dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
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void dispc_save_context(void)
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if (cpu_is_omap24xx())
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SR(GFX_FIFO_THRESHOLD);
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SR(VID_ATTRIBUTES(0));
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SR(VID_FIFO_THRESHOLD(0));
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SR(VID_PIXEL_INC(0));
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SR(VID_PICTURE_SIZE(0));
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SR(VID_FIR_COEF_H(0, 0));
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SR(VID_FIR_COEF_H(0, 1));
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SR(VID_FIR_COEF_H(0, 2));
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SR(VID_FIR_COEF_H(0, 3));
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SR(VID_FIR_COEF_H(0, 4));
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SR(VID_FIR_COEF_H(0, 5));
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SR(VID_FIR_COEF_H(0, 6));
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SR(VID_FIR_COEF_H(0, 7));
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SR(VID_FIR_COEF_HV(0, 0));
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SR(VID_FIR_COEF_HV(0, 1));
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SR(VID_FIR_COEF_HV(0, 2));
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SR(VID_FIR_COEF_HV(0, 3));
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SR(VID_FIR_COEF_HV(0, 4));
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SR(VID_FIR_COEF_HV(0, 5));
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SR(VID_FIR_COEF_HV(0, 6));
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SR(VID_FIR_COEF_HV(0, 7));
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SR(VID_CONV_COEF(0, 0));
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SR(VID_CONV_COEF(0, 1));
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SR(VID_CONV_COEF(0, 2));
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SR(VID_CONV_COEF(0, 3));
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SR(VID_CONV_COEF(0, 4));
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SR(VID_FIR_COEF_V(0, 0));
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SR(VID_FIR_COEF_V(0, 1));
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SR(VID_FIR_COEF_V(0, 2));
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SR(VID_FIR_COEF_V(0, 3));
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SR(VID_FIR_COEF_V(0, 4));
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SR(VID_FIR_COEF_V(0, 5));
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SR(VID_FIR_COEF_V(0, 6));
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SR(VID_FIR_COEF_V(0, 7));
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SR(VID_ATTRIBUTES(1));
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SR(VID_FIFO_THRESHOLD(1));
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SR(VID_PIXEL_INC(1));
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SR(VID_PICTURE_SIZE(1));
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SR(VID_FIR_COEF_H(1, 0));
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SR(VID_FIR_COEF_H(1, 1));
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SR(VID_FIR_COEF_H(1, 2));
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SR(VID_FIR_COEF_H(1, 3));
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SR(VID_FIR_COEF_H(1, 4));
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SR(VID_FIR_COEF_H(1, 5));
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SR(VID_FIR_COEF_H(1, 6));
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SR(VID_FIR_COEF_H(1, 7));
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SR(VID_FIR_COEF_HV(1, 0));
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SR(VID_FIR_COEF_HV(1, 1));
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SR(VID_FIR_COEF_HV(1, 2));
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SR(VID_FIR_COEF_HV(1, 3));
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SR(VID_FIR_COEF_HV(1, 4));
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SR(VID_FIR_COEF_HV(1, 5));
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SR(VID_FIR_COEF_HV(1, 6));
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SR(VID_FIR_COEF_HV(1, 7));
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SR(VID_CONV_COEF(1, 0));
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SR(VID_CONV_COEF(1, 1));
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SR(VID_CONV_COEF(1, 2));
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SR(VID_CONV_COEF(1, 3));
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SR(VID_CONV_COEF(1, 4));
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SR(VID_FIR_COEF_V(1, 0));
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SR(VID_FIR_COEF_V(1, 1));
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SR(VID_FIR_COEF_V(1, 2));
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SR(VID_FIR_COEF_V(1, 3));
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SR(VID_FIR_COEF_V(1, 4));
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SR(VID_FIR_COEF_V(1, 5));
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SR(VID_FIR_COEF_V(1, 6));
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SR(VID_FIR_COEF_V(1, 7));
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void dispc_restore_context(void)
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RR(GFX_FIFO_THRESHOLD);
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RR(VID_ATTRIBUTES(0));
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RR(VID_FIFO_THRESHOLD(0));
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RR(VID_PIXEL_INC(0));
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RR(VID_PICTURE_SIZE(0));
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RR(VID_FIR_COEF_H(0, 0));
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RR(VID_FIR_COEF_H(0, 1));
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RR(VID_FIR_COEF_H(0, 2));
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RR(VID_FIR_COEF_H(0, 3));
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RR(VID_FIR_COEF_H(0, 4));
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RR(VID_FIR_COEF_H(0, 5));
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RR(VID_FIR_COEF_H(0, 6));
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RR(VID_FIR_COEF_H(0, 7));
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RR(VID_FIR_COEF_HV(0, 0));
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RR(VID_FIR_COEF_HV(0, 1));
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RR(VID_FIR_COEF_HV(0, 2));
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RR(VID_FIR_COEF_HV(0, 3));
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RR(VID_FIR_COEF_HV(0, 4));
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RR(VID_FIR_COEF_HV(0, 5));
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RR(VID_FIR_COEF_HV(0, 6));
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RR(VID_FIR_COEF_HV(0, 7));
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RR(VID_CONV_COEF(0, 0));
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RR(VID_CONV_COEF(0, 1));
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RR(VID_CONV_COEF(0, 2));
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RR(VID_CONV_COEF(0, 3));
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RR(VID_CONV_COEF(0, 4));
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RR(VID_FIR_COEF_V(0, 0));
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RR(VID_FIR_COEF_V(0, 1));
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RR(VID_FIR_COEF_V(0, 2));
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RR(VID_FIR_COEF_V(0, 3));
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RR(VID_FIR_COEF_V(0, 4));
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RR(VID_FIR_COEF_V(0, 5));
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RR(VID_FIR_COEF_V(0, 6));
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RR(VID_FIR_COEF_V(0, 7));
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RR(VID_ATTRIBUTES(1));
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RR(VID_FIFO_THRESHOLD(1));
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RR(VID_PIXEL_INC(1));
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RR(VID_PICTURE_SIZE(1));
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RR(VID_FIR_COEF_H(1, 0));
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RR(VID_FIR_COEF_H(1, 1));
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RR(VID_FIR_COEF_H(1, 2));
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RR(VID_FIR_COEF_H(1, 3));
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RR(VID_FIR_COEF_H(1, 4));
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RR(VID_FIR_COEF_H(1, 5));
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RR(VID_FIR_COEF_H(1, 6));
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RR(VID_FIR_COEF_H(1, 7));
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RR(VID_FIR_COEF_HV(1, 0));
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RR(VID_FIR_COEF_HV(1, 1));
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RR(VID_FIR_COEF_HV(1, 2));
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RR(VID_FIR_COEF_HV(1, 3));
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RR(VID_FIR_COEF_HV(1, 4));
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RR(VID_FIR_COEF_HV(1, 5));
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RR(VID_FIR_COEF_HV(1, 6));
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RR(VID_FIR_COEF_HV(1, 7));
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RR(VID_CONV_COEF(1, 0));
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RR(VID_CONV_COEF(1, 1));
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RR(VID_CONV_COEF(1, 2));
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RR(VID_CONV_COEF(1, 3));
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RR(VID_CONV_COEF(1, 4));
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RR(VID_FIR_COEF_V(1, 0));
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RR(VID_FIR_COEF_V(1, 1));
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RR(VID_FIR_COEF_V(1, 2));
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RR(VID_FIR_COEF_V(1, 3));
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RR(VID_FIR_COEF_V(1, 4));
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RR(VID_FIR_COEF_V(1, 5));
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RR(VID_FIR_COEF_V(1, 6));
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RR(VID_FIR_COEF_V(1, 7));
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/* enable last, because LCD & DIGIT enable are here */
480
static inline void enable_clocks(bool enable)
483
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
485
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
488
bool dispc_go_busy(enum omap_channel channel)
492
if (channel == OMAP_DSS_CHANNEL_LCD)
495
bit = 6; /* GODIGIT */
497
return REG_GET(DISPC_CONTROL, bit, bit) == 1;
500
void dispc_go(enum omap_channel channel)
506
if (channel == OMAP_DSS_CHANNEL_LCD)
507
bit = 0; /* LCDENABLE */
509
bit = 1; /* DIGITALENABLE */
511
/* if the channel is not enabled, we don't need GO */
512
if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
515
if (channel == OMAP_DSS_CHANNEL_LCD)
518
bit = 6; /* GODIGIT */
520
if (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
521
DSSERR("GO bit not down for channel %d\n", channel);
525
DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
527
REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
532
static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
534
BUG_ON(plane == OMAP_DSS_GFX);
536
dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
539
static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
541
BUG_ON(plane == OMAP_DSS_GFX);
543
dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
546
static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
548
BUG_ON(plane == OMAP_DSS_GFX);
550
dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
553
static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
554
int vscaleup, int five_taps)
556
/* Coefficients for horizontal up-sampling */
557
static const u32 coef_hup[8] = {
568
/* Coefficients for horizontal down-sampling */
569
static const u32 coef_hdown[8] = {
580
/* Coefficients for horizontal and vertical up-sampling */
581
static const u32 coef_hvup[2][8] = {
604
/* Coefficients for horizontal and vertical down-sampling */
605
static const u32 coef_hvdown[2][8] = {
628
/* Coefficients for vertical up-sampling */
629
static const u32 coef_vup[8] = {
641
/* Coefficients for vertical down-sampling */
642
static const u32 coef_vdown[8] = {
655
const u32 *hv_coef_mod;
665
hv_coef = coef_hvup[five_taps];
671
hv_coef_mod = coef_hvdown[five_taps];
673
hv_coef = coef_hvdown[five_taps];
677
hv_coef_mod = coef_hvup[five_taps];
682
for (i = 0; i < 8; i++) {
691
hv |= (hv_coef_mod[i] & 0xff);
694
_dispc_write_firh_reg(plane, i, h);
695
_dispc_write_firhv_reg(plane, i, hv);
701
for (i = 0; i < 8; i++) {
704
_dispc_write_firv_reg(plane, i, v);
708
static void _dispc_setup_color_conv_coef(void)
710
const struct color_conv_coef {
711
int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
714
298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
717
const struct color_conv_coef *ct;
719
#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
723
dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
724
dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy, ct->rcb));
725
dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
726
dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
727
dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0, ct->bcb));
729
dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
730
dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy, ct->rcb));
731
dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
732
dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
733
dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0, ct->bcb));
737
REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
738
REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
742
static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
744
const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
748
dispc_write_reg(ba0_reg[plane], paddr);
751
static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
753
const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
757
dispc_write_reg(ba1_reg[plane], paddr);
760
static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
762
const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
763
DISPC_VID_POSITION(0),
764
DISPC_VID_POSITION(1) };
766
u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
767
dispc_write_reg(pos_reg[plane], val);
770
static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
772
const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
773
DISPC_VID_PICTURE_SIZE(0),
774
DISPC_VID_PICTURE_SIZE(1) };
775
u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
776
dispc_write_reg(siz_reg[plane], val);
779
static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
782
const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
785
BUG_ON(plane == OMAP_DSS_GFX);
787
val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
788
dispc_write_reg(vsi_reg[plane-1], val);
791
static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
794
BUG_ON(plane == OMAP_DSS_VIDEO1);
796
if (cpu_is_omap24xx())
799
if (plane == OMAP_DSS_GFX)
800
REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
801
else if (plane == OMAP_DSS_VIDEO2)
802
REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
805
static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
807
const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
808
DISPC_VID_PIXEL_INC(0),
809
DISPC_VID_PIXEL_INC(1) };
811
dispc_write_reg(ri_reg[plane], inc);
814
static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
816
const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
817
DISPC_VID_ROW_INC(0),
818
DISPC_VID_ROW_INC(1) };
820
dispc_write_reg(ri_reg[plane], inc);
823
static void _dispc_set_color_mode(enum omap_plane plane,
824
enum omap_color_mode color_mode)
828
switch (color_mode) {
829
case OMAP_DSS_COLOR_CLUT1:
831
case OMAP_DSS_COLOR_CLUT2:
833
case OMAP_DSS_COLOR_CLUT4:
835
case OMAP_DSS_COLOR_CLUT8:
837
case OMAP_DSS_COLOR_RGB12U:
839
case OMAP_DSS_COLOR_ARGB16:
841
case OMAP_DSS_COLOR_RGB16:
843
case OMAP_DSS_COLOR_RGB24U:
845
case OMAP_DSS_COLOR_RGB24P:
847
case OMAP_DSS_COLOR_YUV2:
849
case OMAP_DSS_COLOR_UYVY:
851
case OMAP_DSS_COLOR_ARGB32:
853
case OMAP_DSS_COLOR_RGBA32:
855
case OMAP_DSS_COLOR_RGBX32:
861
REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
864
static void _dispc_set_channel_out(enum omap_plane plane,
865
enum omap_channel channel)
874
case OMAP_DSS_VIDEO1:
875
case OMAP_DSS_VIDEO2:
883
val = dispc_read_reg(dispc_reg_att[plane]);
884
val = FLD_MOD(val, channel, shift, shift);
885
dispc_write_reg(dispc_reg_att[plane], val);
888
void dispc_set_burst_size(enum omap_plane plane,
889
enum omap_burst_size burst_size)
900
case OMAP_DSS_VIDEO1:
901
case OMAP_DSS_VIDEO2:
909
val = dispc_read_reg(dispc_reg_att[plane]);
910
val = FLD_MOD(val, burst_size, shift+1, shift);
911
dispc_write_reg(dispc_reg_att[plane], val);
916
static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
920
BUG_ON(plane == OMAP_DSS_GFX);
922
val = dispc_read_reg(dispc_reg_att[plane]);
923
val = FLD_MOD(val, enable, 9, 9);
924
dispc_write_reg(dispc_reg_att[plane], val);
927
void dispc_enable_replication(enum omap_plane plane, bool enable)
931
if (plane == OMAP_DSS_GFX)
937
REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit);
941
void dispc_set_lcd_size(u16 width, u16 height)
944
BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
945
val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
947
dispc_write_reg(DISPC_SIZE_LCD, val);
951
void dispc_set_digit_size(u16 width, u16 height)
954
BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
955
val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
957
dispc_write_reg(DISPC_SIZE_DIG, val);
961
static void dispc_read_plane_fifo_sizes(void)
963
const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
964
DISPC_VID_FIFO_SIZE_STATUS(0),
965
DISPC_VID_FIFO_SIZE_STATUS(1) };
971
for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
972
if (cpu_is_omap24xx())
973
size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
974
else if (cpu_is_omap34xx())
975
size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
979
dispc.fifo_size[plane] = size;
985
u32 dispc_get_plane_fifo_size(enum omap_plane plane)
987
return dispc.fifo_size[plane];
990
void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
992
const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
993
DISPC_VID_FIFO_THRESHOLD(0),
994
DISPC_VID_FIFO_THRESHOLD(1) };
997
DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
999
REG_GET(ftrs_reg[plane], 11, 0),
1000
REG_GET(ftrs_reg[plane], 27, 16),
1003
if (cpu_is_omap24xx())
1004
dispc_write_reg(ftrs_reg[plane],
1005
FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0));
1007
dispc_write_reg(ftrs_reg[plane],
1008
FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0));
1013
void dispc_enable_fifomerge(bool enable)
1017
DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1018
REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1023
static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
1026
const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
1029
BUG_ON(plane == OMAP_DSS_GFX);
1031
if (cpu_is_omap24xx())
1032
val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
1034
val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1035
dispc_write_reg(fir_reg[plane-1], val);
1038
static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1041
const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1042
DISPC_VID_ACCU0(1) };
1044
BUG_ON(plane == OMAP_DSS_GFX);
1046
val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1047
dispc_write_reg(ac0_reg[plane-1], val);
1050
static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1053
const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1054
DISPC_VID_ACCU1(1) };
1056
BUG_ON(plane == OMAP_DSS_GFX);
1058
val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1059
dispc_write_reg(ac1_reg[plane-1], val);
1063
static void _dispc_set_scaling(enum omap_plane plane,
1064
u16 orig_width, u16 orig_height,
1065
u16 out_width, u16 out_height,
1066
bool ilace, bool five_taps,
1071
int hscaleup, vscaleup;
1076
BUG_ON(plane == OMAP_DSS_GFX);
1078
hscaleup = orig_width <= out_width;
1079
vscaleup = orig_height <= out_height;
1081
_dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1083
if (!orig_width || orig_width == out_width)
1086
fir_hinc = 1024 * orig_width / out_width;
1088
if (!orig_height || orig_height == out_height)
1091
fir_vinc = 1024 * orig_height / out_height;
1093
_dispc_set_fir(plane, fir_hinc, fir_vinc);
1095
l = dispc_read_reg(dispc_reg_att[plane]);
1096
l &= ~((0x0f << 5) | (0x3 << 21));
1098
l |= fir_hinc ? (1 << 5) : 0;
1099
l |= fir_vinc ? (1 << 6) : 0;
1101
l |= hscaleup ? 0 : (1 << 7);
1102
l |= vscaleup ? 0 : (1 << 8);
1104
l |= five_taps ? (1 << 21) : 0;
1105
l |= five_taps ? (1 << 22) : 0;
1107
dispc_write_reg(dispc_reg_att[plane], l);
1110
* field 0 = even field = bottom field
1111
* field 1 = odd field = top field
1113
if (ilace && !fieldmode) {
1115
accu0 = (fir_vinc / 2) & 0x3ff;
1116
if (accu0 >= 1024/2) {
1122
_dispc_set_vid_accu0(plane, 0, accu0);
1123
_dispc_set_vid_accu1(plane, 0, accu1);
1126
static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1127
bool mirroring, enum omap_color_mode color_mode)
1129
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1130
color_mode == OMAP_DSS_COLOR_UYVY) {
1135
case OMAP_DSS_ROT_0:
1138
case OMAP_DSS_ROT_90:
1141
case OMAP_DSS_ROT_180:
1144
case OMAP_DSS_ROT_270:
1150
case OMAP_DSS_ROT_0:
1153
case OMAP_DSS_ROT_90:
1156
case OMAP_DSS_ROT_180:
1159
case OMAP_DSS_ROT_270:
1165
REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1167
if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1168
REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
1170
REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
1172
REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
1173
REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
1177
static int color_mode_to_bpp(enum omap_color_mode color_mode)
1179
switch (color_mode) {
1180
case OMAP_DSS_COLOR_CLUT1:
1182
case OMAP_DSS_COLOR_CLUT2:
1184
case OMAP_DSS_COLOR_CLUT4:
1186
case OMAP_DSS_COLOR_CLUT8:
1188
case OMAP_DSS_COLOR_RGB12U:
1189
case OMAP_DSS_COLOR_RGB16:
1190
case OMAP_DSS_COLOR_ARGB16:
1191
case OMAP_DSS_COLOR_YUV2:
1192
case OMAP_DSS_COLOR_UYVY:
1194
case OMAP_DSS_COLOR_RGB24P:
1196
case OMAP_DSS_COLOR_RGB24U:
1197
case OMAP_DSS_COLOR_ARGB32:
1198
case OMAP_DSS_COLOR_RGBA32:
1199
case OMAP_DSS_COLOR_RGBX32:
1206
static s32 pixinc(int pixels, u8 ps)
1210
else if (pixels > 1)
1211
return 1 + (pixels - 1) * ps;
1212
else if (pixels < 0)
1213
return 1 - (-pixels + 1) * ps;
1218
static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1220
u16 width, u16 height,
1221
enum omap_color_mode color_mode, bool fieldmode,
1222
unsigned int field_offset,
1223
unsigned *offset0, unsigned *offset1,
1224
s32 *row_inc, s32 *pix_inc)
1228
/* FIXME CLUT formats */
1229
switch (color_mode) {
1230
case OMAP_DSS_COLOR_CLUT1:
1231
case OMAP_DSS_COLOR_CLUT2:
1232
case OMAP_DSS_COLOR_CLUT4:
1233
case OMAP_DSS_COLOR_CLUT8:
1236
case OMAP_DSS_COLOR_YUV2:
1237
case OMAP_DSS_COLOR_UYVY:
1241
ps = color_mode_to_bpp(color_mode) / 8;
1245
DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1249
* field 0 = even field = bottom field
1250
* field 1 = odd field = top field
1252
switch (rotation + mirror * 4) {
1253
case OMAP_DSS_ROT_0:
1254
case OMAP_DSS_ROT_180:
1256
* If the pixel format is YUV or UYVY divide the width
1257
* of the image by 2 for 0 and 180 degree rotation.
1259
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1260
color_mode == OMAP_DSS_COLOR_UYVY)
1262
case OMAP_DSS_ROT_90:
1263
case OMAP_DSS_ROT_270:
1266
*offset0 = field_offset * screen_width * ps;
1270
*row_inc = pixinc(1 + (screen_width - width) +
1271
(fieldmode ? screen_width : 0),
1273
*pix_inc = pixinc(1, ps);
1276
case OMAP_DSS_ROT_0 + 4:
1277
case OMAP_DSS_ROT_180 + 4:
1278
/* If the pixel format is YUV or UYVY divide the width
1279
* of the image by 2 for 0 degree and 180 degree
1281
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1282
color_mode == OMAP_DSS_COLOR_UYVY)
1284
case OMAP_DSS_ROT_90 + 4:
1285
case OMAP_DSS_ROT_270 + 4:
1288
*offset0 = field_offset * screen_width * ps;
1291
*row_inc = pixinc(1 - (screen_width + width) -
1292
(fieldmode ? screen_width : 0),
1294
*pix_inc = pixinc(1, ps);
1302
static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1304
u16 width, u16 height,
1305
enum omap_color_mode color_mode, bool fieldmode,
1306
unsigned int field_offset,
1307
unsigned *offset0, unsigned *offset1,
1308
s32 *row_inc, s32 *pix_inc)
1313
/* FIXME CLUT formats */
1314
switch (color_mode) {
1315
case OMAP_DSS_COLOR_CLUT1:
1316
case OMAP_DSS_COLOR_CLUT2:
1317
case OMAP_DSS_COLOR_CLUT4:
1318
case OMAP_DSS_COLOR_CLUT8:
1322
ps = color_mode_to_bpp(color_mode) / 8;
1326
DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1329
/* width & height are overlay sizes, convert to fb sizes */
1331
if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1340
* field 0 = even field = bottom field
1341
* field 1 = odd field = top field
1343
switch (rotation + mirror * 4) {
1344
case OMAP_DSS_ROT_0:
1347
*offset0 = *offset1 + field_offset * screen_width * ps;
1349
*offset0 = *offset1;
1350
*row_inc = pixinc(1 + (screen_width - fbw) +
1351
(fieldmode ? screen_width : 0),
1353
*pix_inc = pixinc(1, ps);
1355
case OMAP_DSS_ROT_90:
1356
*offset1 = screen_width * (fbh - 1) * ps;
1358
*offset0 = *offset1 + field_offset * ps;
1360
*offset0 = *offset1;
1361
*row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1362
(fieldmode ? 1 : 0), ps);
1363
*pix_inc = pixinc(-screen_width, ps);
1365
case OMAP_DSS_ROT_180:
1366
*offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1368
*offset0 = *offset1 - field_offset * screen_width * ps;
1370
*offset0 = *offset1;
1371
*row_inc = pixinc(-1 -
1372
(screen_width - fbw) -
1373
(fieldmode ? screen_width : 0),
1375
*pix_inc = pixinc(-1, ps);
1377
case OMAP_DSS_ROT_270:
1378
*offset1 = (fbw - 1) * ps;
1380
*offset0 = *offset1 - field_offset * ps;
1382
*offset0 = *offset1;
1383
*row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1384
(fieldmode ? 1 : 0), ps);
1385
*pix_inc = pixinc(screen_width, ps);
1389
case OMAP_DSS_ROT_0 + 4:
1390
*offset1 = (fbw - 1) * ps;
1392
*offset0 = *offset1 + field_offset * screen_width * ps;
1394
*offset0 = *offset1;
1395
*row_inc = pixinc(screen_width * 2 - 1 +
1396
(fieldmode ? screen_width : 0),
1398
*pix_inc = pixinc(-1, ps);
1401
case OMAP_DSS_ROT_90 + 4:
1404
*offset0 = *offset1 + field_offset * ps;
1406
*offset0 = *offset1;
1407
*row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1408
(fieldmode ? 1 : 0),
1410
*pix_inc = pixinc(screen_width, ps);
1413
case OMAP_DSS_ROT_180 + 4:
1414
*offset1 = screen_width * (fbh - 1) * ps;
1416
*offset0 = *offset1 - field_offset * screen_width * ps;
1418
*offset0 = *offset1;
1419
*row_inc = pixinc(1 - screen_width * 2 -
1420
(fieldmode ? screen_width : 0),
1422
*pix_inc = pixinc(1, ps);
1425
case OMAP_DSS_ROT_270 + 4:
1426
*offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1428
*offset0 = *offset1 - field_offset * ps;
1430
*offset0 = *offset1;
1431
*row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1432
(fieldmode ? 1 : 0),
1434
*pix_inc = pixinc(-screen_width, ps);
1442
static unsigned long calc_fclk_five_taps(u16 width, u16 height,
1443
u16 out_width, u16 out_height, enum omap_color_mode color_mode)
1446
/* FIXME venc pclk? */
1447
u64 tmp, pclk = dispc_pclk_rate();
1449
if (height > out_height) {
1450
/* FIXME get real display PPL */
1451
unsigned int ppl = 800;
1453
tmp = pclk * height * out_width;
1454
do_div(tmp, 2 * out_height * ppl);
1457
if (height > 2 * out_height) {
1458
if (ppl == out_width)
1461
tmp = pclk * (height - 2 * out_height) * out_width;
1462
do_div(tmp, 2 * out_height * (ppl - out_width));
1463
fclk = max(fclk, (u32) tmp);
1467
if (width > out_width) {
1469
do_div(tmp, out_width);
1470
fclk = max(fclk, (u32) tmp);
1472
if (color_mode == OMAP_DSS_COLOR_RGB24U)
1479
static unsigned long calc_fclk(u16 width, u16 height,
1480
u16 out_width, u16 out_height)
1482
unsigned int hf, vf;
1485
* FIXME how to determine the 'A' factor
1486
* for the no downscaling case ?
1489
if (width > 3 * out_width)
1491
else if (width > 2 * out_width)
1493
else if (width > out_width)
1498
if (height > out_height)
1503
/* FIXME venc pclk? */
1504
return dispc_pclk_rate() * vf * hf;
1507
void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
1510
_dispc_set_channel_out(plane, channel_out);
1514
static int _dispc_setup_plane(enum omap_plane plane,
1515
u32 paddr, u16 screen_width,
1516
u16 pos_x, u16 pos_y,
1517
u16 width, u16 height,
1518
u16 out_width, u16 out_height,
1519
enum omap_color_mode color_mode,
1521
enum omap_dss_rotation_type rotation_type,
1522
u8 rotation, int mirror,
1525
const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1529
unsigned offset0, offset1;
1532
u16 frame_height = height;
1533
unsigned int field_offset = 0;
1538
if (ilace && height == out_height)
1547
DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1549
height, pos_y, out_height);
1552
if (plane == OMAP_DSS_GFX) {
1553
if (width != out_width || height != out_height)
1556
switch (color_mode) {
1557
case OMAP_DSS_COLOR_ARGB16:
1558
case OMAP_DSS_COLOR_ARGB32:
1559
case OMAP_DSS_COLOR_RGBA32:
1560
case OMAP_DSS_COLOR_RGBX32:
1561
if (cpu_is_omap24xx())
1564
case OMAP_DSS_COLOR_RGB12U:
1565
case OMAP_DSS_COLOR_RGB16:
1566
case OMAP_DSS_COLOR_RGB24P:
1567
case OMAP_DSS_COLOR_RGB24U:
1576
unsigned long fclk = 0;
1578
if (out_width < width / maxdownscale ||
1579
out_width > width * 8)
1582
if (out_height < height / maxdownscale ||
1583
out_height > height * 8)
1586
switch (color_mode) {
1587
case OMAP_DSS_COLOR_RGBX32:
1588
case OMAP_DSS_COLOR_RGB12U:
1589
if (cpu_is_omap24xx())
1592
case OMAP_DSS_COLOR_RGB16:
1593
case OMAP_DSS_COLOR_RGB24P:
1594
case OMAP_DSS_COLOR_RGB24U:
1597
case OMAP_DSS_COLOR_ARGB16:
1598
case OMAP_DSS_COLOR_ARGB32:
1599
case OMAP_DSS_COLOR_RGBA32:
1600
if (cpu_is_omap24xx())
1602
if (plane == OMAP_DSS_VIDEO1)
1606
case OMAP_DSS_COLOR_YUV2:
1607
case OMAP_DSS_COLOR_UYVY:
1615
/* Must use 5-tap filter? */
1616
five_taps = height > out_height * 2;
1619
fclk = calc_fclk(width, height,
1620
out_width, out_height);
1622
/* Try 5-tap filter if 3-tap fclk is too high */
1623
if (cpu_is_omap34xx() && height > out_height &&
1624
fclk > dispc_fclk_rate())
1628
if (width > (2048 >> five_taps)) {
1629
DSSERR("failed to set up scaling, fclk too low\n");
1634
fclk = calc_fclk_five_taps(width, height,
1635
out_width, out_height, color_mode);
1637
DSSDBG("required fclk rate = %lu Hz\n", fclk);
1638
DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1640
if (!fclk || fclk > dispc_fclk_rate()) {
1641
DSSERR("failed to set up scaling, "
1642
"required fclk rate = %lu Hz, "
1643
"current fclk rate = %lu Hz\n",
1644
fclk, dispc_fclk_rate());
1649
if (ilace && !fieldmode) {
1651
* when downscaling the bottom field may have to start several
1652
* source lines below the top field. Unfortunately ACCUI
1653
* registers will only hold the fractional part of the offset
1654
* so the integer part must be added to the base address of the
1657
if (!height || height == out_height)
1660
field_offset = height / out_height / 2;
1663
/* Fields are independent but interleaved in memory. */
1667
if (rotation_type == OMAP_DSS_ROT_DMA)
1668
calc_dma_rotation_offset(rotation, mirror,
1669
screen_width, width, frame_height, color_mode,
1670
fieldmode, field_offset,
1671
&offset0, &offset1, &row_inc, &pix_inc);
1673
calc_vrfb_rotation_offset(rotation, mirror,
1674
screen_width, width, frame_height, color_mode,
1675
fieldmode, field_offset,
1676
&offset0, &offset1, &row_inc, &pix_inc);
1678
DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1679
offset0, offset1, row_inc, pix_inc);
1681
_dispc_set_color_mode(plane, color_mode);
1683
_dispc_set_plane_ba0(plane, paddr + offset0);
1684
_dispc_set_plane_ba1(plane, paddr + offset1);
1686
_dispc_set_row_inc(plane, row_inc);
1687
_dispc_set_pix_inc(plane, pix_inc);
1689
DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1690
out_width, out_height);
1692
_dispc_set_plane_pos(plane, pos_x, pos_y);
1694
_dispc_set_pic_size(plane, width, height);
1696
if (plane != OMAP_DSS_GFX) {
1697
_dispc_set_scaling(plane, width, height,
1698
out_width, out_height,
1699
ilace, five_taps, fieldmode);
1700
_dispc_set_vid_size(plane, out_width, out_height);
1701
_dispc_set_vid_color_conv(plane, cconv);
1704
_dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1706
if (plane != OMAP_DSS_VIDEO1)
1707
_dispc_setup_global_alpha(plane, global_alpha);
1712
static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1714
REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1717
static void dispc_disable_isr(void *data, u32 mask)
1719
struct completion *compl = data;
1723
static void _enable_lcd_out(bool enable)
1725
REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1728
void dispc_enable_lcd_out(bool enable)
1730
struct completion frame_done_completion;
1736
/* When we disable LCD output, we need to wait until frame is done.
1737
* Otherwise the DSS is still working, and turning off the clocks
1738
* prevents DSS from going to OFF mode */
1739
is_on = REG_GET(DISPC_CONTROL, 0, 0);
1741
if (!enable && is_on) {
1742
init_completion(&frame_done_completion);
1744
r = omap_dispc_register_isr(dispc_disable_isr,
1745
&frame_done_completion,
1746
DISPC_IRQ_FRAMEDONE);
1749
DSSERR("failed to register FRAMEDONE isr\n");
1752
_enable_lcd_out(enable);
1754
if (!enable && is_on) {
1755
if (!wait_for_completion_timeout(&frame_done_completion,
1756
msecs_to_jiffies(100)))
1757
DSSERR("timeout waiting for FRAME DONE\n");
1759
r = omap_dispc_unregister_isr(dispc_disable_isr,
1760
&frame_done_completion,
1761
DISPC_IRQ_FRAMEDONE);
1764
DSSERR("failed to unregister FRAMEDONE isr\n");
1770
static void _enable_digit_out(bool enable)
1772
REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1775
void dispc_enable_digit_out(bool enable)
1777
struct completion frame_done_completion;
1782
if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1788
unsigned long flags;
1789
/* When we enable digit output, we'll get an extra digit
1790
* sync lost interrupt, that we need to ignore */
1791
spin_lock_irqsave(&dispc.irq_lock, flags);
1792
dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1793
_omap_dispc_set_irqs();
1794
spin_unlock_irqrestore(&dispc.irq_lock, flags);
1797
/* When we disable digit output, we need to wait until fields are done.
1798
* Otherwise the DSS is still working, and turning off the clocks
1799
* prevents DSS from going to OFF mode. And when enabling, we need to
1800
* wait for the extra sync losts */
1801
init_completion(&frame_done_completion);
1803
r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1804
DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1806
DSSERR("failed to register EVSYNC isr\n");
1808
_enable_digit_out(enable);
1810
/* XXX I understand from TRM that we should only wait for the
1811
* current field to complete. But it seems we have to wait
1812
* for both fields */
1813
if (!wait_for_completion_timeout(&frame_done_completion,
1814
msecs_to_jiffies(100)))
1815
DSSERR("timeout waiting for EVSYNC\n");
1817
if (!wait_for_completion_timeout(&frame_done_completion,
1818
msecs_to_jiffies(100)))
1819
DSSERR("timeout waiting for EVSYNC\n");
1821
r = omap_dispc_unregister_isr(dispc_disable_isr,
1822
&frame_done_completion,
1823
DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1825
DSSERR("failed to unregister EVSYNC isr\n");
1828
unsigned long flags;
1829
spin_lock_irqsave(&dispc.irq_lock, flags);
1830
dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
1831
dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1832
_omap_dispc_set_irqs();
1833
spin_unlock_irqrestore(&dispc.irq_lock, flags);
1839
void dispc_lcd_enable_signal_polarity(bool act_high)
1842
REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1846
void dispc_lcd_enable_signal(bool enable)
1849
REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1853
void dispc_pck_free_enable(bool enable)
1856
REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1860
void dispc_enable_fifohandcheck(bool enable)
1863
REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
1868
void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
1873
case OMAP_DSS_LCD_DISPLAY_STN:
1877
case OMAP_DSS_LCD_DISPLAY_TFT:
1887
REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
1891
void dispc_set_loadmode(enum omap_dss_load_mode mode)
1894
REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
1899
void dispc_set_default_color(enum omap_channel channel, u32 color)
1901
const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1902
DISPC_DEFAULT_COLOR1 };
1905
dispc_write_reg(def_reg[channel], color);
1909
u32 dispc_get_default_color(enum omap_channel channel)
1911
const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1912
DISPC_DEFAULT_COLOR1 };
1915
BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
1916
channel != OMAP_DSS_CHANNEL_LCD);
1919
l = dispc_read_reg(def_reg[channel]);
1925
void dispc_set_trans_key(enum omap_channel ch,
1926
enum omap_dss_trans_key_type type,
1929
const struct dispc_reg tr_reg[] = {
1930
DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1933
if (ch == OMAP_DSS_CHANNEL_LCD)
1934
REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
1935
else /* OMAP_DSS_CHANNEL_DIGIT */
1936
REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
1938
dispc_write_reg(tr_reg[ch], trans_key);
1942
void dispc_get_trans_key(enum omap_channel ch,
1943
enum omap_dss_trans_key_type *type,
1946
const struct dispc_reg tr_reg[] = {
1947
DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1951
if (ch == OMAP_DSS_CHANNEL_LCD)
1952
*type = REG_GET(DISPC_CONFIG, 11, 11);
1953
else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1954
*type = REG_GET(DISPC_CONFIG, 13, 13);
1960
*trans_key = dispc_read_reg(tr_reg[ch]);
1964
void dispc_enable_trans_key(enum omap_channel ch, bool enable)
1967
if (ch == OMAP_DSS_CHANNEL_LCD)
1968
REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
1969
else /* OMAP_DSS_CHANNEL_DIGIT */
1970
REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
1973
void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
1975
if (cpu_is_omap24xx())
1979
if (ch == OMAP_DSS_CHANNEL_LCD)
1980
REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
1981
else /* OMAP_DSS_CHANNEL_DIGIT */
1982
REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
1985
bool dispc_alpha_blending_enabled(enum omap_channel ch)
1989
if (cpu_is_omap24xx())
1993
if (ch == OMAP_DSS_CHANNEL_LCD)
1994
enabled = REG_GET(DISPC_CONFIG, 18, 18);
1995
else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1996
enabled = REG_GET(DISPC_CONFIG, 18, 18);
2006
bool dispc_trans_key_enabled(enum omap_channel ch)
2011
if (ch == OMAP_DSS_CHANNEL_LCD)
2012
enabled = REG_GET(DISPC_CONFIG, 10, 10);
2013
else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2014
enabled = REG_GET(DISPC_CONFIG, 12, 12);
2023
void dispc_set_tft_data_lines(u8 data_lines)
2027
switch (data_lines) {
2046
REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2050
void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
2058
case OMAP_DSS_PARALLELMODE_BYPASS:
2063
case OMAP_DSS_PARALLELMODE_RFBI:
2068
case OMAP_DSS_PARALLELMODE_DSI:
2080
l = dispc_read_reg(DISPC_CONTROL);
2082
l = FLD_MOD(l, stallmode, 11, 11);
2083
l = FLD_MOD(l, gpout0, 15, 15);
2084
l = FLD_MOD(l, gpout1, 16, 16);
2086
dispc_write_reg(DISPC_CONTROL, l);
2091
static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2092
int vsw, int vfp, int vbp)
2094
if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2095
if (hsw < 1 || hsw > 64 ||
2096
hfp < 1 || hfp > 256 ||
2097
hbp < 1 || hbp > 256 ||
2098
vsw < 1 || vsw > 64 ||
2099
vfp < 0 || vfp > 255 ||
2100
vbp < 0 || vbp > 255)
2103
if (hsw < 1 || hsw > 256 ||
2104
hfp < 1 || hfp > 4096 ||
2105
hbp < 1 || hbp > 4096 ||
2106
vsw < 1 || vsw > 256 ||
2107
vfp < 0 || vfp > 4095 ||
2108
vbp < 0 || vbp > 4095)
2115
bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2117
return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2118
timings->hbp, timings->vsw,
2119
timings->vfp, timings->vbp);
2122
static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
2123
int vsw, int vfp, int vbp)
2125
u32 timing_h, timing_v;
2127
if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2128
timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2129
FLD_VAL(hbp-1, 27, 20);
2131
timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2132
FLD_VAL(vbp, 27, 20);
2134
timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2135
FLD_VAL(hbp-1, 31, 20);
2137
timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2138
FLD_VAL(vbp, 31, 20);
2142
dispc_write_reg(DISPC_TIMING_H, timing_h);
2143
dispc_write_reg(DISPC_TIMING_V, timing_v);
2147
/* change name to mode? */
2148
void dispc_set_lcd_timings(struct omap_video_timings *timings)
2150
unsigned xtot, ytot;
2151
unsigned long ht, vt;
2153
if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2154
timings->hbp, timings->vsw,
2155
timings->vfp, timings->vbp))
2158
_dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
2159
timings->vsw, timings->vfp, timings->vbp);
2161
dispc_set_lcd_size(timings->x_res, timings->y_res);
2163
xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2164
ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2166
ht = (timings->pixel_clock * 1000) / xtot;
2167
vt = (timings->pixel_clock * 1000) / xtot / ytot;
2169
DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
2170
DSSDBG("pck %u\n", timings->pixel_clock);
2171
DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2172
timings->hsw, timings->hfp, timings->hbp,
2173
timings->vsw, timings->vfp, timings->vbp);
2175
DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2178
static void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
2180
BUG_ON(lck_div < 1);
2181
BUG_ON(pck_div < 2);
2184
dispc_write_reg(DISPC_DIVISOR,
2185
FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2189
static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
2192
l = dispc_read_reg(DISPC_DIVISOR);
2193
*lck_div = FLD_GET(l, 23, 16);
2194
*pck_div = FLD_GET(l, 7, 0);
2197
unsigned long dispc_fclk_rate(void)
2199
unsigned long r = 0;
2201
if (dss_get_dispc_clk_source() == 0)
2202
r = dss_clk_get_rate(DSS_CLK_FCK1);
2204
#ifdef CONFIG_OMAP2_DSS_DSI
2205
r = dsi_get_dsi1_pll_rate();
2212
unsigned long dispc_lclk_rate(void)
2218
l = dispc_read_reg(DISPC_DIVISOR);
2220
lcd = FLD_GET(l, 23, 16);
2222
r = dispc_fclk_rate();
2227
unsigned long dispc_pclk_rate(void)
2233
l = dispc_read_reg(DISPC_DIVISOR);
2235
lcd = FLD_GET(l, 23, 16);
2236
pcd = FLD_GET(l, 7, 0);
2238
r = dispc_fclk_rate();
2240
return r / lcd / pcd;
2243
void dispc_dump_clocks(struct seq_file *s)
2249
dispc_get_lcd_divisor(&lcd, &pcd);
2251
seq_printf(s, "- DISPC -\n");
2253
seq_printf(s, "dispc fclk source = %s\n",
2254
dss_get_dispc_clk_source() == 0 ?
2255
"dss1_alwon_fclk" : "dsi1_pll_fclk");
2257
seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2258
seq_printf(s, "lck\t\t%-16lulck div\t%u\n", dispc_lclk_rate(), lcd);
2259
seq_printf(s, "pck\t\t%-16lupck div\t%u\n", dispc_pclk_rate(), pcd);
2264
#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2265
void dispc_dump_irqs(struct seq_file *s)
2267
unsigned long flags;
2268
struct dispc_irq_stats stats;
2270
spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2272
stats = dispc.irq_stats;
2273
memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2274
dispc.irq_stats.last_reset = jiffies;
2276
spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2278
seq_printf(s, "period %u ms\n",
2279
jiffies_to_msecs(jiffies - stats.last_reset));
2281
seq_printf(s, "irqs %d\n", stats.irq_count);
2283
seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2289
PIS(ACBIAS_COUNT_STAT);
2291
PIS(GFX_FIFO_UNDERFLOW);
2293
PIS(PAL_GAMMA_MASK);
2295
PIS(VID1_FIFO_UNDERFLOW);
2297
PIS(VID2_FIFO_UNDERFLOW);
2300
PIS(SYNC_LOST_DIGIT);
2305
void dispc_dump_irqs(struct seq_file *s) { }
2308
void dispc_dump_regs(struct seq_file *s)
2310
#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
2312
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
2314
DUMPREG(DISPC_REVISION);
2315
DUMPREG(DISPC_SYSCONFIG);
2316
DUMPREG(DISPC_SYSSTATUS);
2317
DUMPREG(DISPC_IRQSTATUS);
2318
DUMPREG(DISPC_IRQENABLE);
2319
DUMPREG(DISPC_CONTROL);
2320
DUMPREG(DISPC_CONFIG);
2321
DUMPREG(DISPC_CAPABLE);
2322
DUMPREG(DISPC_DEFAULT_COLOR0);
2323
DUMPREG(DISPC_DEFAULT_COLOR1);
2324
DUMPREG(DISPC_TRANS_COLOR0);
2325
DUMPREG(DISPC_TRANS_COLOR1);
2326
DUMPREG(DISPC_LINE_STATUS);
2327
DUMPREG(DISPC_LINE_NUMBER);
2328
DUMPREG(DISPC_TIMING_H);
2329
DUMPREG(DISPC_TIMING_V);
2330
DUMPREG(DISPC_POL_FREQ);
2331
DUMPREG(DISPC_DIVISOR);
2332
DUMPREG(DISPC_GLOBAL_ALPHA);
2333
DUMPREG(DISPC_SIZE_DIG);
2334
DUMPREG(DISPC_SIZE_LCD);
2336
DUMPREG(DISPC_GFX_BA0);
2337
DUMPREG(DISPC_GFX_BA1);
2338
DUMPREG(DISPC_GFX_POSITION);
2339
DUMPREG(DISPC_GFX_SIZE);
2340
DUMPREG(DISPC_GFX_ATTRIBUTES);
2341
DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
2342
DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
2343
DUMPREG(DISPC_GFX_ROW_INC);
2344
DUMPREG(DISPC_GFX_PIXEL_INC);
2345
DUMPREG(DISPC_GFX_WINDOW_SKIP);
2346
DUMPREG(DISPC_GFX_TABLE_BA);
2348
DUMPREG(DISPC_DATA_CYCLE1);
2349
DUMPREG(DISPC_DATA_CYCLE2);
2350
DUMPREG(DISPC_DATA_CYCLE3);
2352
DUMPREG(DISPC_CPR_COEF_R);
2353
DUMPREG(DISPC_CPR_COEF_G);
2354
DUMPREG(DISPC_CPR_COEF_B);
2356
DUMPREG(DISPC_GFX_PRELOAD);
2358
DUMPREG(DISPC_VID_BA0(0));
2359
DUMPREG(DISPC_VID_BA1(0));
2360
DUMPREG(DISPC_VID_POSITION(0));
2361
DUMPREG(DISPC_VID_SIZE(0));
2362
DUMPREG(DISPC_VID_ATTRIBUTES(0));
2363
DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
2364
DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
2365
DUMPREG(DISPC_VID_ROW_INC(0));
2366
DUMPREG(DISPC_VID_PIXEL_INC(0));
2367
DUMPREG(DISPC_VID_FIR(0));
2368
DUMPREG(DISPC_VID_PICTURE_SIZE(0));
2369
DUMPREG(DISPC_VID_ACCU0(0));
2370
DUMPREG(DISPC_VID_ACCU1(0));
2372
DUMPREG(DISPC_VID_BA0(1));
2373
DUMPREG(DISPC_VID_BA1(1));
2374
DUMPREG(DISPC_VID_POSITION(1));
2375
DUMPREG(DISPC_VID_SIZE(1));
2376
DUMPREG(DISPC_VID_ATTRIBUTES(1));
2377
DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
2378
DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
2379
DUMPREG(DISPC_VID_ROW_INC(1));
2380
DUMPREG(DISPC_VID_PIXEL_INC(1));
2381
DUMPREG(DISPC_VID_FIR(1));
2382
DUMPREG(DISPC_VID_PICTURE_SIZE(1));
2383
DUMPREG(DISPC_VID_ACCU0(1));
2384
DUMPREG(DISPC_VID_ACCU1(1));
2386
DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
2387
DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
2388
DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
2389
DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
2390
DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
2391
DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
2392
DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
2393
DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
2394
DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
2395
DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
2396
DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
2397
DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
2398
DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
2399
DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
2400
DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
2401
DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
2402
DUMPREG(DISPC_VID_CONV_COEF(0, 0));
2403
DUMPREG(DISPC_VID_CONV_COEF(0, 1));
2404
DUMPREG(DISPC_VID_CONV_COEF(0, 2));
2405
DUMPREG(DISPC_VID_CONV_COEF(0, 3));
2406
DUMPREG(DISPC_VID_CONV_COEF(0, 4));
2407
DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
2408
DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
2409
DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
2410
DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
2411
DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
2412
DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
2413
DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
2414
DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
2416
DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
2417
DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
2418
DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
2419
DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
2420
DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
2421
DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
2422
DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
2423
DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
2424
DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
2425
DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
2426
DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
2427
DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
2428
DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
2429
DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
2430
DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
2431
DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
2432
DUMPREG(DISPC_VID_CONV_COEF(1, 0));
2433
DUMPREG(DISPC_VID_CONV_COEF(1, 1));
2434
DUMPREG(DISPC_VID_CONV_COEF(1, 2));
2435
DUMPREG(DISPC_VID_CONV_COEF(1, 3));
2436
DUMPREG(DISPC_VID_CONV_COEF(1, 4));
2437
DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
2438
DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
2439
DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
2440
DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
2441
DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
2442
DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
2443
DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
2444
DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
2446
DUMPREG(DISPC_VID_PRELOAD(0));
2447
DUMPREG(DISPC_VID_PRELOAD(1));
2449
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
2453
static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
2454
bool ihs, bool ivs, u8 acbi, u8 acb)
2458
DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2459
onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2461
l |= FLD_VAL(onoff, 17, 17);
2462
l |= FLD_VAL(rf, 16, 16);
2463
l |= FLD_VAL(ieo, 15, 15);
2464
l |= FLD_VAL(ipc, 14, 14);
2465
l |= FLD_VAL(ihs, 13, 13);
2466
l |= FLD_VAL(ivs, 12, 12);
2467
l |= FLD_VAL(acbi, 11, 8);
2468
l |= FLD_VAL(acb, 7, 0);
2471
dispc_write_reg(DISPC_POL_FREQ, l);
2475
void dispc_set_pol_freq(enum omap_panel_config config, u8 acbi, u8 acb)
2477
_dispc_set_pol_freq((config & OMAP_DSS_LCD_ONOFF) != 0,
2478
(config & OMAP_DSS_LCD_RF) != 0,
2479
(config & OMAP_DSS_LCD_IEO) != 0,
2480
(config & OMAP_DSS_LCD_IPC) != 0,
2481
(config & OMAP_DSS_LCD_IHS) != 0,
2482
(config & OMAP_DSS_LCD_IVS) != 0,
2486
/* with fck as input clock rate, find dispc dividers that produce req_pck */
2487
void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2488
struct dispc_clock_info *cinfo)
2490
u16 pcd_min = is_tft ? 2 : 3;
2491
unsigned long best_pck;
2492
u16 best_ld, cur_ld;
2493
u16 best_pd, cur_pd;
2499
for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2500
unsigned long lck = fck / cur_ld;
2502
for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2503
unsigned long pck = lck / cur_pd;
2504
long old_delta = abs(best_pck - req_pck);
2505
long new_delta = abs(pck - req_pck);
2507
if (best_pck == 0 || new_delta < old_delta) {
2520
if (lck / pcd_min < req_pck)
2525
cinfo->lck_div = best_ld;
2526
cinfo->pck_div = best_pd;
2527
cinfo->lck = fck / cinfo->lck_div;
2528
cinfo->pck = cinfo->lck / cinfo->pck_div;
2531
/* calculate clock rates using dividers in cinfo */
2532
int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2533
struct dispc_clock_info *cinfo)
2535
if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2537
if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
2540
cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2541
cinfo->pck = cinfo->lck / cinfo->pck_div;
2546
int dispc_set_clock_div(struct dispc_clock_info *cinfo)
2548
DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2549
DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2551
dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
2556
int dispc_get_clock_div(struct dispc_clock_info *cinfo)
2560
fck = dispc_fclk_rate();
2562
cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
2563
cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
2565
cinfo->lck = fck / cinfo->lck_div;
2566
cinfo->pck = cinfo->lck / cinfo->pck_div;
2571
/* dispc.irq_lock has to be locked by the caller */
2572
static void _omap_dispc_set_irqs(void)
2577
struct omap_dispc_isr_data *isr_data;
2579
mask = dispc.irq_error_mask;
2581
for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2582
isr_data = &dispc.registered_isr[i];
2584
if (isr_data->isr == NULL)
2587
mask |= isr_data->mask;
2592
old_mask = dispc_read_reg(DISPC_IRQENABLE);
2593
/* clear the irqstatus for newly enabled irqs */
2594
dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2596
dispc_write_reg(DISPC_IRQENABLE, mask);
2601
int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2605
unsigned long flags;
2606
struct omap_dispc_isr_data *isr_data;
2611
spin_lock_irqsave(&dispc.irq_lock, flags);
2613
/* check for duplicate entry */
2614
for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2615
isr_data = &dispc.registered_isr[i];
2616
if (isr_data->isr == isr && isr_data->arg == arg &&
2617
isr_data->mask == mask) {
2626
for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2627
isr_data = &dispc.registered_isr[i];
2629
if (isr_data->isr != NULL)
2632
isr_data->isr = isr;
2633
isr_data->arg = arg;
2634
isr_data->mask = mask;
2640
_omap_dispc_set_irqs();
2642
spin_unlock_irqrestore(&dispc.irq_lock, flags);
2646
spin_unlock_irqrestore(&dispc.irq_lock, flags);
2650
EXPORT_SYMBOL(omap_dispc_register_isr);
2652
int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2655
unsigned long flags;
2657
struct omap_dispc_isr_data *isr_data;
2659
spin_lock_irqsave(&dispc.irq_lock, flags);
2661
for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2662
isr_data = &dispc.registered_isr[i];
2663
if (isr_data->isr != isr || isr_data->arg != arg ||
2664
isr_data->mask != mask)
2667
/* found the correct isr */
2669
isr_data->isr = NULL;
2670
isr_data->arg = NULL;
2678
_omap_dispc_set_irqs();
2680
spin_unlock_irqrestore(&dispc.irq_lock, flags);
2684
EXPORT_SYMBOL(omap_dispc_unregister_isr);
2687
static void print_irq_status(u32 status)
2689
if ((status & dispc.irq_error_mask) == 0)
2692
printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2695
if (status & DISPC_IRQ_##x) \
2697
PIS(GFX_FIFO_UNDERFLOW);
2699
PIS(VID1_FIFO_UNDERFLOW);
2700
PIS(VID2_FIFO_UNDERFLOW);
2702
PIS(SYNC_LOST_DIGIT);
2709
/* Called from dss.c. Note that we don't touch clocks here,
2710
* but we presume they are on because we got an IRQ. However,
2711
* an irq handler may turn the clocks off, so we may not have
2712
* clock later in the function. */
2713
void dispc_irq_handler(void)
2717
u32 handledirqs = 0;
2718
u32 unhandled_errors;
2719
struct omap_dispc_isr_data *isr_data;
2720
struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2722
spin_lock(&dispc.irq_lock);
2724
irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2726
#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2727
spin_lock(&dispc.irq_stats_lock);
2728
dispc.irq_stats.irq_count++;
2729
dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2730
spin_unlock(&dispc.irq_stats_lock);
2735
print_irq_status(irqstatus);
2737
/* Ack the interrupt. Do it here before clocks are possibly turned
2739
dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2740
/* flush posted write */
2741
dispc_read_reg(DISPC_IRQSTATUS);
2743
/* make a copy and unlock, so that isrs can unregister
2745
memcpy(registered_isr, dispc.registered_isr,
2746
sizeof(registered_isr));
2748
spin_unlock(&dispc.irq_lock);
2750
for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2751
isr_data = ®istered_isr[i];
2756
if (isr_data->mask & irqstatus) {
2757
isr_data->isr(isr_data->arg, irqstatus);
2758
handledirqs |= isr_data->mask;
2762
spin_lock(&dispc.irq_lock);
2764
unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2766
if (unhandled_errors) {
2767
dispc.error_irqs |= unhandled_errors;
2769
dispc.irq_error_mask &= ~unhandled_errors;
2770
_omap_dispc_set_irqs();
2772
schedule_work(&dispc.error_work);
2775
spin_unlock(&dispc.irq_lock);
2778
static void dispc_error_worker(struct work_struct *work)
2782
unsigned long flags;
2784
spin_lock_irqsave(&dispc.irq_lock, flags);
2785
errors = dispc.error_irqs;
2786
dispc.error_irqs = 0;
2787
spin_unlock_irqrestore(&dispc.irq_lock, flags);
2789
if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2790
DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2791
for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2792
struct omap_overlay *ovl;
2793
ovl = omap_dss_get_overlay(i);
2795
if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2799
dispc_enable_plane(ovl->id, 0);
2800
dispc_go(ovl->manager->id);
2807
if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2808
DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2809
for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2810
struct omap_overlay *ovl;
2811
ovl = omap_dss_get_overlay(i);
2813
if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2817
dispc_enable_plane(ovl->id, 0);
2818
dispc_go(ovl->manager->id);
2825
if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
2826
DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
2827
for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2828
struct omap_overlay *ovl;
2829
ovl = omap_dss_get_overlay(i);
2831
if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2835
dispc_enable_plane(ovl->id, 0);
2836
dispc_go(ovl->manager->id);
2843
if (errors & DISPC_IRQ_SYNC_LOST) {
2844
struct omap_overlay_manager *manager = NULL;
2845
bool enable = false;
2847
DSSERR("SYNC_LOST, disabling LCD\n");
2849
for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2850
struct omap_overlay_manager *mgr;
2851
mgr = omap_dss_get_overlay_manager(i);
2853
if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
2855
enable = mgr->device->state ==
2856
OMAP_DSS_DISPLAY_ACTIVE;
2857
mgr->device->disable(mgr->device);
2863
for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2864
struct omap_overlay *ovl;
2865
ovl = omap_dss_get_overlay(i);
2867
if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2870
if (ovl->id != 0 && ovl->manager == manager)
2871
dispc_enable_plane(ovl->id, 0);
2874
dispc_go(manager->id);
2877
manager->device->enable(manager->device);
2881
if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
2882
struct omap_overlay_manager *manager = NULL;
2883
bool enable = false;
2885
DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
2887
for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2888
struct omap_overlay_manager *mgr;
2889
mgr = omap_dss_get_overlay_manager(i);
2891
if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
2893
enable = mgr->device->state ==
2894
OMAP_DSS_DISPLAY_ACTIVE;
2895
mgr->device->disable(mgr->device);
2901
for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2902
struct omap_overlay *ovl;
2903
ovl = omap_dss_get_overlay(i);
2905
if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2908
if (ovl->id != 0 && ovl->manager == manager)
2909
dispc_enable_plane(ovl->id, 0);
2912
dispc_go(manager->id);
2915
manager->device->enable(manager->device);
2919
if (errors & DISPC_IRQ_OCP_ERR) {
2920
DSSERR("OCP_ERR\n");
2921
for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2922
struct omap_overlay_manager *mgr;
2923
mgr = omap_dss_get_overlay_manager(i);
2925
if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
2926
mgr->device->disable(mgr->device);
2930
spin_lock_irqsave(&dispc.irq_lock, flags);
2931
dispc.irq_error_mask |= errors;
2932
_omap_dispc_set_irqs();
2933
spin_unlock_irqrestore(&dispc.irq_lock, flags);
2936
int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
2938
void dispc_irq_wait_handler(void *data, u32 mask)
2940
complete((struct completion *)data);
2944
DECLARE_COMPLETION_ONSTACK(completion);
2946
r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2952
timeout = wait_for_completion_timeout(&completion, timeout);
2954
omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2959
if (timeout == -ERESTARTSYS)
2960
return -ERESTARTSYS;
2965
int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
2966
unsigned long timeout)
2968
void dispc_irq_wait_handler(void *data, u32 mask)
2970
complete((struct completion *)data);
2974
DECLARE_COMPLETION_ONSTACK(completion);
2976
r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2982
timeout = wait_for_completion_interruptible_timeout(&completion,
2985
omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2990
if (timeout == -ERESTARTSYS)
2991
return -ERESTARTSYS;
2996
#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
2997
void dispc_fake_vsync_irq(void)
2999
u32 irqstatus = DISPC_IRQ_VSYNC;
3002
local_irq_disable();
3004
for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3005
struct omap_dispc_isr_data *isr_data;
3006
isr_data = &dispc.registered_isr[i];
3011
if (isr_data->mask & irqstatus)
3012
isr_data->isr(isr_data->arg, irqstatus);
3019
static void _omap_dispc_initialize_irq(void)
3021
unsigned long flags;
3023
spin_lock_irqsave(&dispc.irq_lock, flags);
3025
memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3027
dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3029
/* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3031
dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3033
_omap_dispc_set_irqs();
3035
spin_unlock_irqrestore(&dispc.irq_lock, flags);
3038
void dispc_enable_sidle(void)
3040
REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3043
void dispc_disable_sidle(void)
3045
REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3048
static void _omap_dispc_initial_config(void)
3052
l = dispc_read_reg(DISPC_SYSCONFIG);
3053
l = FLD_MOD(l, 2, 13, 12); /* MIDLEMODE: smart standby */
3054
l = FLD_MOD(l, 2, 4, 3); /* SIDLEMODE: smart idle */
3055
l = FLD_MOD(l, 1, 2, 2); /* ENWAKEUP */
3056
l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */
3057
dispc_write_reg(DISPC_SYSCONFIG, l);
3060
REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3062
/* L3 firewall setting: enable access to OCM RAM */
3063
/* XXX this should be somewhere in plat-omap */
3064
if (cpu_is_omap24xx())
3065
__raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3067
_dispc_setup_color_conv_coef();
3069
dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3071
dispc_read_plane_fifo_sizes();
3074
int dispc_init(void)
3078
spin_lock_init(&dispc.irq_lock);
3080
#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3081
spin_lock_init(&dispc.irq_stats_lock);
3082
dispc.irq_stats.last_reset = jiffies;
3085
INIT_WORK(&dispc.error_work, dispc_error_worker);
3087
dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
3089
DSSERR("can't ioremap DISPC\n");
3095
_omap_dispc_initial_config();
3097
_omap_dispc_initialize_irq();
3099
dispc_save_context();
3101
rev = dispc_read_reg(DISPC_REVISION);
3102
printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
3103
FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3110
void dispc_exit(void)
3112
iounmap(dispc.base);
3115
int dispc_enable_plane(enum omap_plane plane, bool enable)
3117
DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3120
_dispc_enable_plane(plane, enable);
3126
int dispc_setup_plane(enum omap_plane plane,
3127
u32 paddr, u16 screen_width,
3128
u16 pos_x, u16 pos_y,
3129
u16 width, u16 height,
3130
u16 out_width, u16 out_height,
3131
enum omap_color_mode color_mode,
3133
enum omap_dss_rotation_type rotation_type,
3134
u8 rotation, bool mirror, u8 global_alpha)
3138
DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
3139
"%dx%d, ilace %d, cmode %x, rot %d, mir %d\n",
3140
plane, paddr, screen_width, pos_x, pos_y,
3142
out_width, out_height,
3148
r = _dispc_setup_plane(plane,
3149
paddr, screen_width,
3152
out_width, out_height,