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* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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#ifndef __ARCH_ARM_MACH_MX3_SERIAL_H__
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#define __ARCH_ARM_MACH_MX3_SERIAL_H__
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* @file mach-mx3/serial.h
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#include <mach/mxc_uart.h>
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* UART Chip level Configuration that a user may not have to edit. These
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* configuration vary depending on how the UART module is integrated with
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* This option is used to set or clear the RXDMUXSEL bit in control reg 3.
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* Certain platforms need this bit to be set in order to receive Irda data.
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#define MXC_UART_IR_RXDMUX 0x0004
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* This option is used to set or clear the RXDMUXSEL bit in control reg 3.
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* Certain platforms need this bit to be set in order to receive UART data.
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#define MXC_UART_RXDMUX 0x0004
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/* UART 1 configuration */
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* This option allows to choose either an interrupt-driven software controlled
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* hardware flow control (set this option to 0) or hardware-driven hardware
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* flow control (set this option to 1).
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/* UART used as wakeup source */
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#define UART1_HW_FLOW 0
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* This specifies the threshold at which the CTS pin is deasserted by the
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* RXFIFO. Set this value in Decimal to anything from 0 to 32 for
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* hardware-driven hardware flow control. Read the HW spec while specifying
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* this value. When using interrupt-driven software controlled hardware
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* flow control set this option to -1.
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#define UART1_UCR4_CTSTL 16
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* This is option to enable (set this option to 1) or disable DMA data transfer
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#define UART1_DMA_ENABLE 0
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* Specify the size of the DMA receive buffer. The minimum buffer size is 512
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* bytes. The buffer size should be a multiple of 256.
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#define UART1_DMA_RXBUFSIZE 1024
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* Specify the MXC UART's Receive Trigger Level. This controls the threshold at
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* which a maskable interrupt is generated by the RxFIFO. Set this value in
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* Decimal to anything from 0 to 32. Read the HW spec while specifying this
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#define UART1_UFCR_RXTL 16
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* Specify the MXC UART's Transmit Trigger Level. This controls the threshold at
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* which a maskable interrupt is generated by the TxFIFO. Set this value in
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* Decimal to anything from 0 to 32. Read the HW spec while specifying this
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#define UART1_UFCR_TXTL 16
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/* UART 2 configuration */
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#define UART2_HW_FLOW 0
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#define UART2_UCR4_CTSTL -1
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#define UART2_DMA_ENABLE 0
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#define UART2_DMA_RXBUFSIZE 512
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#define UART2_UFCR_RXTL 16
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#define UART2_UFCR_TXTL 16
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/* UART 3 configuration */
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#define UART3_HW_FLOW 1
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#define UART3_UCR4_CTSTL 16
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#define UART3_DMA_ENABLE 1
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#define UART3_DMA_RXBUFSIZE 1024
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#define UART3_UFCR_RXTL 16
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#define UART3_UFCR_TXTL 16
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/* UART 4 configuration */
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#define UART4_HW_FLOW 1
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#define UART4_UCR4_CTSTL 16
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#define UART4_DMA_ENABLE 0
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#define UART4_DMA_RXBUFSIZE 512
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#define UART4_UFCR_RXTL 16
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#define UART4_UFCR_TXTL 16
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/* UART 5 configuration */
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#define UART5_HW_FLOW 1
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#define UART5_UCR4_CTSTL 16
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#define UART5_DMA_ENABLE 0
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#define UART5_DMA_RXBUFSIZE 512
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#define UART5_UFCR_RXTL 16
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#define UART5_UFCR_TXTL 16
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* UART Chip level Configuration that a user may not have to edit. These
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* configuration vary depending on how the UART module is integrated with
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* Is the MUXED interrupt output sent to the ARM core
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#define INTS_NOTMUXED 0
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/* UART 1 configuration */
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* This define specifies whether the muxed ANDed interrupt line or the
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* individual interrupts from the UART port is integrated with the ARM core.
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* There exists a define like this for each UART port. Valid values that can
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* be used are \b INTS_NOTMUXED or \b INTS_MUXED.
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#define UART1_MUX_INTS INTS_MUXED
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* This define specifies the transmitter interrupt number or the interrupt
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* number of the ANDed interrupt in case the interrupts are muxed. There exists
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* a define like this for each UART port.
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#define UART1_INT1 MXC_INT_UART1
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* This define specifies the receiver interrupt number. If the interrupts of
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* the UART are muxed, then we specify here a dummy value -1. There exists a
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* define like this for each UART port.
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#define UART1_INT2 -1
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* This specifies the master interrupt number. If the interrupts of the UART
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* are muxed, then we specify here a dummy value of -1. There exists a define
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* like this for each UART port.
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#define UART1_INT3 -1
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* This specifies if the UART is a shared peripheral. It holds the shared
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* peripheral number if it is shared or -1 if it is not shared. There exists
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* a define like this for each UART port.
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#define UART1_SHARED_PERI -1
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/* UART 2 configuration */
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#define UART2_MUX_INTS INTS_MUXED
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#define UART2_INT1 MXC_INT_UART2
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#define UART2_INT2 -1
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#define UART2_INT3 -1
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#define UART2_SHARED_PERI -1
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/* UART 3 configuration */
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#define UART3_MUX_INTS INTS_MUXED
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#define UART3_INT1 MXC_INT_UART3
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#define UART3_INT2 -1
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#define UART3_INT3 -1
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#define UART3_SHARED_PERI SPBA_UART3
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/* UART 4 configuration */
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#define UART4_MUX_INTS INTS_MUXED
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#define UART4_INT1 MXC_INT_UART4
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#define UART4_INT2 -1
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#define UART4_INT3 -1
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#define UART4_SHARED_PERI -1
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/* UART 5 configuration */
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#define UART5_MUX_INTS INTS_MUXED
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#define UART5_INT1 MXC_INT_UART5
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#define UART5_INT2 -1
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#define UART5_INT3 -1
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#define UART5_SHARED_PERI -1
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#endif /* __ARCH_ARM_MACH_MX3_SERIAL_H__ */
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arch/arm/mach-mx3/serial.h
