← Back to branch summary

~ubuntu-branches/ubuntu/vivid/linux-fsl-imx51/vivid

« back to all changes in this revision

Viewing changes to arch/arm/mach-mx35/dma.c

  • Committer: Bazaar Package Importer
  • Author(s): Andy Whitcroft, Amit Kucheria, Andy Whitcroft, Bryan Wu, Upstream Kernel Changes
  • Date: 2010-01-11 16:26:27 UTC
  • Revision ID: james.westby@ubuntu.com-20100111162627-1q2fl9tcuwcywt1e
Tags: 2.6.31-602.4
[ Amit Kucheria ]

* Update to official 2.6.31 BSP release from Freescale

[ Andy Whitcroft ]

* drop a number of modules no longer built

[ Bryan Wu ]

* [Config] Update configs after applying .31 patchset from Freescale
* [Config] Sync with imx51_defconfig from Freescale BSP

[ Upstream Kernel Changes ]

* Update to official 2.6.31 BSP release from Freescale.

Show diffs side-by-side

added added

removed removed

Lines of Context:
arch/arm/mach-mx35/dma.c
 
1
/*
 
2
 *  Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
 
3
 */
 
4
 
 
5
/*
 
6
 * The code contained herein is licensed under the GNU General Public
 
7
 * License. You may obtain a copy of the GNU General Public License
 
8
 * Version 2 or later at the following locations:
 
9
 *
 
10
 * http://www.opensource.org/licenses/gpl-license.html
 
11
 * http://www.gnu.org/copyleft/gpl.html
 
12
 */
 
13
#include <linux/init.h>
 
14
#include <linux/device.h>
 
15
#include <asm/dma.h>
 
16
#include <mach/hardware.h>
 
17
 
 
18
#include "serial.h"
 
19
 
 
20
#ifdef CONFIG_SND_MXC_SOC_IRAM
 
21
#define soc_trans_type  int_2_per
 
22
#else
 
23
#define soc_trans_type emi_2_per
 
24
#endif
 
25
 
 
26
#define MXC_SPDIF_TXFIFO_WML      8
 
27
#define MXC_SPDIF_RXFIFO_WML      8
 
28
#define MXC_SPDIF_TX_REG          0x2C
 
29
#define MXC_SPDIF_RX_REG          0x14
 
30
 
 
31
#define MXC_SSI_TX0_REG           0x0
 
32
#define MXC_SSI_TX1_REG           0x4
 
33
#define MXC_SSI_RX0_REG           0x8
 
34
#define MXC_SSI_RX1_REG           0xC
 
35
#define MXC_SSI_TXFIFO_WML        0x4
 
36
#define MXC_SSI_RXFIFO_WML        0x6
 
37
 
 
38
#define MXC_ASRC_FIFO_WML       0x40
 
39
#define MXC_ASRCA_RX_REG        0x60
 
40
#define MXC_ASRCA_TX_REG        0x64
 
41
#define MXC_ASRCB_RX_REG        0x68
 
42
#define MXC_ASRCB_TX_REG        0x6C
 
43
#define MXC_ASRCC_RX_REG        0x70
 
44
#define MXC_ASRCC_TX_REG        0x74
 
45
 
 
46
#define MXC_ESAI_TX_REG 0x00
 
47
#define MXC_ESAI_RX_REG 0x04
 
48
#define MXC_ESAI_FIFO_WML 0x40
 
49
 
 
50
struct mxc_sdma_info_entry_s {
 
51
        mxc_dma_device_t device;
 
52
        void *chnl_info;
 
53
};
 
54
 
 
55
static mxc_sdma_channel_params_t mxc_sdma_uart1_rx_params = {
 
56
        .chnl_params = {
 
57
                        .watermark_level = UART1_UFCR_RXTL,
 
58
                        .per_address = UART1_BASE_ADDR,
 
59
                        .peripheral_type = UART,
 
60
                        .transfer_type = per_2_emi,
 
61
                        .event_id = DMA_REQ_UART1_RX,
 
62
                        .bd_number = 32,
 
63
                        .word_size = TRANSFER_8BIT,
 
64
                        },
 
65
        .channel_num = MXC_DMA_CHANNEL_UART1_RX,
 
66
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
67
};
 
68
 
 
69
static mxc_sdma_channel_params_t mxc_sdma_uart1_tx_params = {
 
70
        .chnl_params = {
 
71
                        .watermark_level = UART1_UFCR_TXTL,
 
72
                        .per_address = UART1_BASE_ADDR + MXC_UARTUTXD,
 
73
                        .peripheral_type = UART,
 
74
                        .transfer_type = emi_2_per,
 
75
                        .event_id = DMA_REQ_UART1_TX,
 
76
                        .bd_number = 32,
 
77
                        .word_size = TRANSFER_8BIT,
 
78
                        },
 
79
        .channel_num = MXC_DMA_CHANNEL_UART1_TX,
 
80
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
81
};
 
82
 
 
83
static mxc_sdma_channel_params_t mxc_sdma_uart2_rx_params = {
 
84
        .chnl_params = {
 
85
                        .watermark_level = UART2_UFCR_RXTL,
 
86
                        .per_address = UART2_BASE_ADDR,
 
87
                        .peripheral_type = UART,
 
88
                        .transfer_type = per_2_emi,
 
89
                        .event_id = DMA_REQ_UART2_RX,
 
90
                        .bd_number = 32,
 
91
                        .word_size = TRANSFER_8BIT,
 
92
                        },
 
93
        .channel_num = MXC_DMA_CHANNEL_UART2_RX,
 
94
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
95
};
 
96
 
 
97
static mxc_sdma_channel_params_t mxc_sdma_uart2_tx_params = {
 
98
        .chnl_params = {
 
99
                        .watermark_level = UART2_UFCR_TXTL,
 
100
                        .per_address = UART2_BASE_ADDR + MXC_UARTUTXD,
 
101
                        .peripheral_type = UART,
 
102
                        .transfer_type = emi_2_per,
 
103
                        .event_id = DMA_REQ_UART2_TX,
 
104
                        .bd_number = 32,
 
105
                        .word_size = TRANSFER_8BIT,
 
106
                        },
 
107
        .channel_num = MXC_DMA_CHANNEL_UART2_TX,
 
108
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
109
};
 
110
 
 
111
static mxc_sdma_channel_params_t mxc_sdma_uart3_rx_params = {
 
112
        .chnl_params = {
 
113
                        .watermark_level = UART3_UFCR_RXTL,
 
114
                        .per_address = UART3_BASE_ADDR,
 
115
                        .peripheral_type = UART_SP,
 
116
                        .transfer_type = per_2_emi,
 
117
                        .event_id = DMA_REQ_UART3_RX,
 
118
                        .bd_number = 32,
 
119
                        .word_size = TRANSFER_8BIT,
 
120
                        },
 
121
        .channel_num = MXC_DMA_CHANNEL_UART3_RX,
 
122
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
123
};
 
124
 
 
125
static mxc_sdma_channel_params_t mxc_sdma_uart3_tx_params = {
 
126
        .chnl_params = {
 
127
                        .watermark_level = UART3_UFCR_TXTL,
 
128
                        .per_address = UART3_BASE_ADDR + MXC_UARTUTXD,
 
129
                        .peripheral_type = UART_SP,
 
130
                        .transfer_type = emi_2_per,
 
131
                        .event_id = DMA_REQ_UART3_TX,
 
132
                        .bd_number = 32,
 
133
                        .word_size = TRANSFER_8BIT,
 
134
                        },
 
135
        .channel_num = MXC_DMA_CHANNEL_UART3_TX,
 
136
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
137
};
 
138
 
 
139
static mxc_sdma_channel_params_t mxc_sdma_spdif_16bit_tx_params = {
 
140
        .chnl_params = {
 
141
                        .watermark_level = MXC_SPDIF_TXFIFO_WML,
 
142
                        .per_address = SPDIF_BASE_ADDR + MXC_SPDIF_TX_REG,
 
143
                        .peripheral_type = SPDIF,
 
144
                        .transfer_type = emi_2_per,
 
145
                        .event_id = DMA_REQ_SPDIF_TX,
 
146
                        .bd_number = 32,
 
147
                        .word_size = TRANSFER_16BIT,
 
148
                        },
 
149
        .channel_num = MXC_DMA_CHANNEL_SPDIF_TX,
 
150
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
151
};
 
152
 
 
153
static mxc_sdma_channel_params_t mxc_sdma_spdif_32bit_tx_params = {
 
154
        .chnl_params = {
 
155
                        .watermark_level = MXC_SPDIF_TXFIFO_WML,
 
156
                        .per_address = SPDIF_BASE_ADDR + MXC_SPDIF_TX_REG,
 
157
                        .peripheral_type = SPDIF,
 
158
                        .transfer_type = emi_2_per,
 
159
                        .event_id = DMA_REQ_SPDIF_TX,
 
160
                        .bd_number = 32,
 
161
                        .word_size = TRANSFER_32BIT,
 
162
                        },
 
163
        .channel_num = MXC_DMA_CHANNEL_SPDIF_TX,
 
164
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
165
};
 
166
 
 
167
static mxc_sdma_channel_params_t mxc_sdma_spdif_32bit_rx_params = {
 
168
        .chnl_params = {
 
169
                        .watermark_level = MXC_SPDIF_RXFIFO_WML,
 
170
                        .per_address = SPDIF_BASE_ADDR + MXC_SPDIF_RX_REG,
 
171
                        .peripheral_type = SPDIF,
 
172
                        .transfer_type = per_2_emi,
 
173
                        .event_id = DMA_REQ_SPDIF_RX,
 
174
                        .bd_number = 32,
 
175
                        .word_size = TRANSFER_32BIT,
 
176
                        },
 
177
        .channel_num = MXC_DMA_CHANNEL_SPDIF_RX,
 
178
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
179
};
 
180
 
 
181
static mxc_sdma_channel_params_t mxc_sdma_memory_params = {
 
182
        .chnl_params = {
 
183
                        .peripheral_type = MEMORY,
 
184
                        .transfer_type = emi_2_emi,
 
185
                        .bd_number = 32,
 
186
                        .word_size = TRANSFER_32BIT,
 
187
                        },
 
188
        .channel_num = MXC_DMA_CHANNEL_MEMORY,
 
189
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
190
};
 
191
 
 
192
static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_rx0_params = {
 
193
        .chnl_params = {
 
194
                        .watermark_level = MXC_SSI_RXFIFO_WML,
 
195
                        .per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG,
 
196
                        .peripheral_type = SSI,
 
197
                        .transfer_type = per_2_emi,
 
198
                        .event_id = DMA_REQ_SSI1_RX1,
 
199
                        .bd_number = 32,
 
200
                        .word_size = TRANSFER_8BIT,
 
201
                        },
 
202
        .channel_num = MXC_DMA_CHANNEL_SSI1_RX,
 
203
        .chnl_priority = 2,
 
204
};
 
205
 
 
206
static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_tx0_params = {
 
207
        .chnl_params = {
 
208
                        .watermark_level = MXC_SSI_TXFIFO_WML,
 
209
                        .per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG,
 
210
                        .peripheral_type = SSI,
 
211
                        .transfer_type = soc_trans_type,
 
212
                        .event_id = DMA_REQ_SSI1_TX1,
 
213
                        .bd_number = 32,
 
214
                        .word_size = TRANSFER_8BIT,
 
215
                        },
 
216
        .channel_num = MXC_DMA_CHANNEL_SSI1_TX,
 
217
        .chnl_priority = 2,
 
218
};
 
219
 
 
220
static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_rx0_params = {
 
221
        .chnl_params = {
 
222
                        .watermark_level = MXC_SSI_RXFIFO_WML,
 
223
                        .per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG,
 
224
                        .peripheral_type = SSI,
 
225
                        .transfer_type = per_2_emi,
 
226
                        .event_id = DMA_REQ_SSI1_RX1,
 
227
                        .bd_number = 32,
 
228
                        .word_size = TRANSFER_16BIT,
 
229
                        },
 
230
        .channel_num = MXC_DMA_CHANNEL_SSI1_RX,
 
231
        .chnl_priority = 2,
 
232
};
 
233
 
 
234
static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_tx0_params = {
 
235
        .chnl_params = {
 
236
                        .watermark_level = MXC_SSI_TXFIFO_WML,
 
237
                        .per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG,
 
238
                        .peripheral_type = SSI,
 
239
                        .transfer_type = soc_trans_type,
 
240
                        .event_id = DMA_REQ_SSI1_TX1,
 
241
                        .bd_number = 32,
 
242
                        .word_size = TRANSFER_16BIT,
 
243
                        },
 
244
        .channel_num = MXC_DMA_CHANNEL_SSI1_TX,
 
245
        .chnl_priority = 2,
 
246
};
 
247
 
 
248
static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_rx0_params = {
 
249
        .chnl_params = {
 
250
                        .watermark_level = MXC_SSI_RXFIFO_WML,
 
251
                        .per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG,
 
252
                        .peripheral_type = SSI,
 
253
                        .transfer_type = per_2_emi,
 
254
                        .event_id = DMA_REQ_SSI1_RX1,
 
255
                        .bd_number = 32,
 
256
                        .word_size = TRANSFER_32BIT,
 
257
                        },
 
258
        .channel_num = MXC_DMA_CHANNEL_SSI1_RX,
 
259
        .chnl_priority = 2,
 
260
};
 
261
 
 
262
static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_tx0_params = {
 
263
        .chnl_params = {
 
264
                        .watermark_level = MXC_SSI_TXFIFO_WML,
 
265
                        .per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG,
 
266
                        .peripheral_type = SSI,
 
267
                        .transfer_type = soc_trans_type,
 
268
                        .event_id = DMA_REQ_SSI1_TX1,
 
269
                        .bd_number = 32,
 
270
                        .word_size = TRANSFER_32BIT,
 
271
                        },
 
272
        .channel_num = MXC_DMA_CHANNEL_SSI1_TX,
 
273
        .chnl_priority = 2,
 
274
};
 
275
 
 
276
static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_rx1_params = {
 
277
        .chnl_params = {
 
278
                        .watermark_level = MXC_SSI_RXFIFO_WML,
 
279
                        .per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG,
 
280
                        .peripheral_type = SSI,
 
281
                        .transfer_type = per_2_emi,
 
282
                        .event_id = DMA_REQ_SSI1_RX2,
 
283
                        .bd_number = 32,
 
284
                        .word_size = TRANSFER_8BIT,
 
285
                        },
 
286
        .channel_num = MXC_DMA_CHANNEL_SSI1_RX,
 
287
        .chnl_priority = 2,
 
288
};
 
289
 
 
290
static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_tx1_params = {
 
291
        .chnl_params = {
 
292
                        .watermark_level = MXC_SSI_TXFIFO_WML,
 
293
                        .per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG,
 
294
                        .peripheral_type = SSI,
 
295
                        .transfer_type = soc_trans_type,
 
296
                        .event_id = DMA_REQ_SSI1_TX2,
 
297
                        .bd_number = 32,
 
298
                        .word_size = TRANSFER_8BIT,
 
299
                        },
 
300
        .channel_num = MXC_DMA_CHANNEL_SSI1_TX,
 
301
        .chnl_priority = 2,
 
302
};
 
303
 
 
304
static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_rx1_params = {
 
305
        .chnl_params = {
 
306
                        .watermark_level = MXC_SSI_RXFIFO_WML,
 
307
                        .per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG,
 
308
                        .peripheral_type = SSI,
 
309
                        .transfer_type = per_2_emi,
 
310
                        .event_id = DMA_REQ_SSI1_RX2,
 
311
                        .bd_number = 32,
 
312
                        .word_size = TRANSFER_16BIT,
 
313
                        },
 
314
        .channel_num = MXC_DMA_CHANNEL_SSI1_RX,
 
315
        .chnl_priority = 2,
 
316
};
 
317
 
 
318
static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_tx1_params = {
 
319
        .chnl_params = {
 
320
                        .watermark_level = MXC_SSI_TXFIFO_WML,
 
321
                        .per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG,
 
322
                        .peripheral_type = SSI,
 
323
                        .transfer_type = soc_trans_type,
 
324
                        .event_id = DMA_REQ_SSI1_TX2,
 
325
                        .bd_number = 32,
 
326
                        .word_size = TRANSFER_16BIT,
 
327
                        },
 
328
        .channel_num = MXC_DMA_CHANNEL_SSI1_TX,
 
329
        .chnl_priority = 2,
 
330
};
 
331
 
 
332
static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_rx1_params = {
 
333
        .chnl_params = {
 
334
                        .watermark_level = MXC_SSI_RXFIFO_WML,
 
335
                        .per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG,
 
336
                        .peripheral_type = SSI,
 
337
                        .transfer_type = per_2_emi,
 
338
                        .event_id = DMA_REQ_SSI1_RX2,
 
339
                        .bd_number = 32,
 
340
                        .word_size = TRANSFER_32BIT,
 
341
                        },
 
342
        .channel_num = MXC_DMA_CHANNEL_SSI1_RX,
 
343
        .chnl_priority = 2,
 
344
};
 
345
 
 
346
static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_tx1_params = {
 
347
        .chnl_params = {
 
348
                        .watermark_level = MXC_SSI_TXFIFO_WML,
 
349
                        .per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG,
 
350
                        .peripheral_type = SSI,
 
351
                        .transfer_type = soc_trans_type,
 
352
                        .event_id = DMA_REQ_SSI1_TX2,
 
353
                        .bd_number = 32,
 
354
                        .word_size = TRANSFER_32BIT,
 
355
                        },
 
356
        .channel_num = MXC_DMA_CHANNEL_SSI1_TX,
 
357
        .chnl_priority = 2,
 
358
};
 
359
 
 
360
static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_rx0_params = {
 
361
        .chnl_params = {
 
362
                        .watermark_level = MXC_SSI_RXFIFO_WML,
 
363
                        .per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG,
 
364
                        .peripheral_type = SSI_SP,
 
365
                        .transfer_type = per_2_emi,
 
366
                        .event_id = DMA_REQ_SSI2_RX1,
 
367
                        .bd_number = 32,
 
368
                        .word_size = TRANSFER_8BIT,
 
369
                        },
 
370
        .channel_num = MXC_DMA_CHANNEL_SSI2_RX,
 
371
        .chnl_priority = 2,
 
372
};
 
373
 
 
374
static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_tx0_params = {
 
375
        .chnl_params = {
 
376
                        .watermark_level = MXC_SSI_TXFIFO_WML,
 
377
                        .per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG,
 
378
                        .peripheral_type = SSI_SP,
 
379
                        .transfer_type = emi_2_per,
 
380
                        .event_id = DMA_REQ_SSI2_TX1,
 
381
                        .bd_number = 32,
 
382
                        .word_size = TRANSFER_8BIT,
 
383
                        },
 
384
        .channel_num = MXC_DMA_CHANNEL_SSI2_TX,
 
385
        .chnl_priority = 2,
 
386
};
 
387
 
 
388
static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_rx0_params = {
 
389
        .chnl_params = {
 
390
                        .watermark_level = MXC_SSI_RXFIFO_WML,
 
391
                        .per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG,
 
392
                        .peripheral_type = SSI_SP,
 
393
                        .transfer_type = per_2_emi,
 
394
                        .event_id = DMA_REQ_SSI2_RX1,
 
395
                        .bd_number = 32,
 
396
                        .word_size = TRANSFER_16BIT,
 
397
                        },
 
398
        .channel_num = MXC_DMA_CHANNEL_SSI2_RX,
 
399
        .chnl_priority = 2,
 
400
};
 
401
 
 
402
static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_tx0_params = {
 
403
        .chnl_params = {
 
404
                        .watermark_level = MXC_SSI_TXFIFO_WML,
 
405
                        .per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG,
 
406
                        .peripheral_type = SSI_SP,
 
407
                        .transfer_type = emi_2_per,
 
408
                        .event_id = DMA_REQ_SSI2_TX1,
 
409
                        .bd_number = 32,
 
410
                        .word_size = TRANSFER_16BIT,
 
411
                        },
 
412
        .channel_num = MXC_DMA_CHANNEL_SSI2_TX,
 
413
        .chnl_priority = 2,
 
414
};
 
415
 
 
416
static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_rx0_params = {
 
417
        .chnl_params = {
 
418
                        .watermark_level = MXC_SSI_RXFIFO_WML,
 
419
                        .per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG,
 
420
                        .peripheral_type = SSI_SP,
 
421
                        .transfer_type = per_2_emi,
 
422
                        .event_id = DMA_REQ_SSI2_RX1,
 
423
                        .bd_number = 32,
 
424
                        .word_size = TRANSFER_32BIT,
 
425
                        },
 
426
        .channel_num = MXC_DMA_CHANNEL_SSI2_RX,
 
427
        .chnl_priority = 2,
 
428
};
 
429
 
 
430
static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_tx0_params = {
 
431
        .chnl_params = {
 
432
                        .watermark_level = MXC_SSI_TXFIFO_WML,
 
433
                        .per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG,
 
434
                        .peripheral_type = SSI_SP,
 
435
                        .transfer_type = emi_2_per,
 
436
                        .event_id = DMA_REQ_SSI2_TX1,
 
437
                        .bd_number = 32,
 
438
                        .word_size = TRANSFER_32BIT,
 
439
                        },
 
440
        .channel_num = MXC_DMA_CHANNEL_SSI2_TX,
 
441
        .chnl_priority = 2,
 
442
};
 
443
 
 
444
static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_rx1_params = {
 
445
        .chnl_params = {
 
446
                        .watermark_level = MXC_SSI_RXFIFO_WML,
 
447
                        .per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG,
 
448
                        .peripheral_type = SSI_SP,
 
449
                        .transfer_type = per_2_emi,
 
450
                        .event_id = DMA_REQ_SSI2_RX2,
 
451
                        .bd_number = 32,
 
452
                        .word_size = TRANSFER_8BIT,
 
453
                        },
 
454
        .channel_num = MXC_DMA_CHANNEL_SSI2_RX,
 
455
        .chnl_priority = 2,
 
456
};
 
457
 
 
458
static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_tx1_params = {
 
459
        .chnl_params = {
 
460
                        .watermark_level = MXC_SSI_TXFIFO_WML,
 
461
                        .per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG,
 
462
                        .peripheral_type = SSI_SP,
 
463
                        .transfer_type = emi_2_per,
 
464
                        .event_id = DMA_REQ_SSI2_TX2,
 
465
                        .bd_number = 32,
 
466
                        .word_size = TRANSFER_8BIT,
 
467
                        },
 
468
        .channel_num = MXC_DMA_CHANNEL_SSI2_TX,
 
469
        .chnl_priority = 2,
 
470
};
 
471
 
 
472
static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_rx1_params = {
 
473
        .chnl_params = {
 
474
                        .watermark_level = MXC_SSI_RXFIFO_WML,
 
475
                        .per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG,
 
476
                        .peripheral_type = SSI_SP,
 
477
                        .transfer_type = per_2_emi,
 
478
                        .event_id = DMA_REQ_SSI2_RX2,
 
479
                        .bd_number = 32,
 
480
                        .word_size = TRANSFER_16BIT,
 
481
                        },
 
482
        .channel_num = MXC_DMA_CHANNEL_SSI2_RX,
 
483
        .chnl_priority = 2,
 
484
};
 
485
 
 
486
static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_tx1_params = {
 
487
        .chnl_params = {
 
488
                        .watermark_level = MXC_SSI_TXFIFO_WML,
 
489
                        .per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG,
 
490
                        .peripheral_type = SSI_SP,
 
491
                        .transfer_type = emi_2_per,
 
492
                        .event_id = DMA_REQ_SSI2_TX2,
 
493
                        .bd_number = 32,
 
494
                        .word_size = TRANSFER_16BIT,
 
495
                        },
 
496
        .channel_num = MXC_DMA_CHANNEL_SSI2_TX,
 
497
        .chnl_priority = 2,
 
498
};
 
499
 
 
500
static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_rx1_params = {
 
501
        .chnl_params = {
 
502
                        .watermark_level = MXC_SSI_RXFIFO_WML,
 
503
                        .per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG,
 
504
                        .peripheral_type = SSI_SP,
 
505
                        .transfer_type = per_2_emi,
 
506
                        .event_id = DMA_REQ_SSI2_RX2,
 
507
                        .bd_number = 32,
 
508
                        .word_size = TRANSFER_32BIT,
 
509
                        },
 
510
        .channel_num = MXC_DMA_CHANNEL_SSI2_RX,
 
511
        .chnl_priority = 2,
 
512
};
 
513
 
 
514
static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_tx1_params = {
 
515
        .chnl_params = {
 
516
                        .watermark_level = MXC_SSI_TXFIFO_WML,
 
517
                        .per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG,
 
518
                        .peripheral_type = SSI_SP,
 
519
                        .transfer_type = emi_2_per,
 
520
                        .event_id = DMA_REQ_SSI2_TX2,
 
521
                        .bd_number = 32,
 
522
                        .word_size = TRANSFER_32BIT,
 
523
                        },
 
524
        .channel_num = MXC_DMA_CHANNEL_SSI2_TX,
 
525
        .chnl_priority = 2,
 
526
};
 
527
 
 
528
static mxc_sdma_channel_params_t mxc_sdma_asrca_rx_params = {
 
529
        .chnl_params = {
 
530
                        .watermark_level = MXC_ASRC_FIFO_WML,
 
531
                        .per_address = ASRC_BASE_ADDR + MXC_ASRCA_RX_REG,
 
532
                        .peripheral_type = ASRC,
 
533
                        .transfer_type = emi_2_per,
 
534
                        .event_id = DMA_REQ_ASRC_DMA1,
 
535
                        .bd_number = 32,
 
536
                        .word_size = TRANSFER_32BIT,
 
537
                        },
 
538
        .channel_num = MXC_DMA_CHANNEL_ASRCA_RX,
 
539
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
540
};
 
541
 
 
542
static mxc_sdma_channel_params_t mxc_sdma_asrca_tx_params = {
 
543
        .chnl_params = {
 
544
                        .watermark_level = MXC_ASRC_FIFO_WML,
 
545
                        .per_address = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG,
 
546
                        .peripheral_type = ASRC,
 
547
                        .transfer_type = per_2_emi,
 
548
                        .event_id = DMA_REQ_ASRC_DMA4,
 
549
                        .bd_number = 32,
 
550
                        .word_size = TRANSFER_32BIT,
 
551
                        },
 
552
        .channel_num = MXC_DMA_CHANNEL_ASRCA_TX,
 
553
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
554
};
 
555
 
 
556
static mxc_sdma_channel_params_t mxc_sdma_asrcb_rx_params = {
 
557
        .chnl_params = {
 
558
                        .watermark_level = MXC_ASRC_FIFO_WML,
 
559
                        .per_address = ASRC_BASE_ADDR + MXC_ASRCB_RX_REG,
 
560
                        .peripheral_type = ASRC,
 
561
                        .transfer_type = emi_2_per,
 
562
                        .event_id = DMA_REQ_ASRC_DMA2,
 
563
                        .bd_number = 32,
 
564
                        .word_size = TRANSFER_32BIT,
 
565
                        },
 
566
        .channel_num = MXC_DMA_CHANNEL_ASRCB_RX,
 
567
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
568
};
 
569
 
 
570
static mxc_sdma_channel_params_t mxc_sdma_asrcb_tx_params = {
 
571
        .chnl_params = {
 
572
                        .watermark_level = MXC_ASRC_FIFO_WML,
 
573
                        .per_address = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG,
 
574
                        .peripheral_type = ASRC,
 
575
                        .transfer_type = per_2_emi,
 
576
                        .event_id = DMA_REQ_ASRC_DMA5,
 
577
                        .bd_number = 32,
 
578
                        .word_size = TRANSFER_32BIT,
 
579
                        },
 
580
        .channel_num = MXC_DMA_CHANNEL_ASRCB_TX,
 
581
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
582
};
 
583
 
 
584
static mxc_sdma_channel_params_t mxc_sdma_asrcc_rx_params = {
 
585
        .chnl_params = {
 
586
                        .watermark_level = MXC_ASRC_FIFO_WML * 3,
 
587
                        .per_address = ASRC_BASE_ADDR + MXC_ASRCC_RX_REG,
 
588
                        .peripheral_type = ASRC,
 
589
                        .transfer_type = emi_2_per,
 
590
                        .event_id = DMA_REQ_ASRC_DMA3,
 
591
                        .bd_number = 32,
 
592
                        .word_size = TRANSFER_32BIT,
 
593
                        },
 
594
        .channel_num = MXC_DMA_CHANNEL_ASRCC_RX,
 
595
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
596
};
 
597
 
 
598
static mxc_sdma_channel_params_t mxc_sdma_asrcc_tx_params = {
 
599
        .chnl_params = {
 
600
                        .watermark_level = MXC_ASRC_FIFO_WML * 3,
 
601
                        .per_address = ASRC_BASE_ADDR + MXC_ASRCC_TX_REG,
 
602
                        .peripheral_type = ASRC,
 
603
                        .transfer_type = per_2_emi,
 
604
                        .event_id = DMA_REQ_ASRC_DMA6,
 
605
                        .bd_number = 32,
 
606
                        .word_size = TRANSFER_32BIT,
 
607
                        },
 
608
        .channel_num = MXC_DMA_CHANNEL_ASRCC_TX,
 
609
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
610
};
 
611
 
 
612
static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_ssi1_tx0_params = {
 
613
        .chnl_ext_params = {
 
614
                            .common = {
 
615
                                       .watermark_level =
 
616
                                       MXC_ASRC_FIFO_WML >> 1,
 
617
                                       .per_address =
 
618
                                       SSI1_BASE_ADDR + MXC_SSI_TX0_REG,
 
619
                                       .peripheral_type = ASRC,
 
620
                                       .transfer_type = per_2_per,
 
621
                                       .event_id = DMA_REQ_SSI1_TX1,
 
622
                                       .event_id2 = DMA_REQ_ASRC_DMA4,
 
623
                                       .bd_number = 32,
 
624
                                       .word_size = TRANSFER_32BIT,
 
625
                                       .ext = 1,
 
626
                                       },
 
627
                            .p2p_dir = 0,
 
628
                            .info_bits =
 
629
                            SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP,
 
630
                            .watermark_level2 = MXC_SSI_TXFIFO_WML,
 
631
                            .per_address2 = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG,
 
632
                            },
 
633
        .channel_num = MXC_DMA_CHANNEL_ASRCA_SSI1_TX0,
 
634
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
635
};
 
636
 
 
637
static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_ssi1_tx1_params = {
 
638
        .chnl_ext_params = {
 
639
                            .common = {
 
640
                                       .watermark_level =
 
641
                                       MXC_ASRC_FIFO_WML >> 1,
 
642
                                       .per_address =
 
643
                                       SSI1_BASE_ADDR + MXC_SSI_TX1_REG,
 
644
                                       .peripheral_type = ASRC,
 
645
                                       .transfer_type = per_2_per,
 
646
                                       .event_id = DMA_REQ_SSI1_TX2,
 
647
                                       .event_id2 = DMA_REQ_ASRC_DMA4,
 
648
                                       .bd_number = 32,
 
649
                                       .word_size = TRANSFER_32BIT,
 
650
                                       .ext = 1,
 
651
                                       },
 
652
                            .p2p_dir = 0,
 
653
                            .info_bits =
 
654
                            SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP,
 
655
                            .watermark_level2 = MXC_SSI_TXFIFO_WML,
 
656
                            .per_address2 = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG,
 
657
                            },
 
658
        .channel_num = MXC_DMA_CHANNEL_ASRCA_SSI1_TX1,
 
659
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
660
};
 
661
 
 
662
static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_ssi2_tx0_params = {
 
663
        .chnl_ext_params = {
 
664
                            .common = {
 
665
                                       .watermark_level =
 
666
                                       MXC_ASRC_FIFO_WML >> 1,
 
667
                                       .per_address =
 
668
                                       SSI2_BASE_ADDR + MXC_SSI_TX0_REG,
 
669
                                       .peripheral_type = ASRC,
 
670
                                       .transfer_type = per_2_per,
 
671
                                       .event_id = DMA_REQ_SSI2_TX1,
 
672
                                       .event_id2 = DMA_REQ_ASRC_DMA4,
 
673
                                       .bd_number = 32,
 
674
                                       .word_size = TRANSFER_32BIT,
 
675
                                       .ext = 1,
 
676
                                       },
 
677
                            .p2p_dir = 0,
 
678
                            .info_bits =
 
679
                            SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP |
 
680
                            SDMA_ASRC_P2P_INFO_DP,
 
681
                            .watermark_level2 = MXC_SSI_TXFIFO_WML,
 
682
                            .per_address2 = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG,
 
683
                            },
 
684
        .channel_num = MXC_DMA_CHANNEL_ASRCA_SSI2_TX0,
 
685
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
686
};
 
687
 
 
688
static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_ssi2_tx1_params = {
 
689
        .chnl_ext_params = {
 
690
                            .common = {
 
691
                                       .watermark_level =
 
692
                                       MXC_ASRC_FIFO_WML >> 1,
 
693
                                       .per_address =
 
694
                                       SSI2_BASE_ADDR + MXC_SSI_TX1_REG,
 
695
                                       .peripheral_type = ASRC,
 
696
                                       .transfer_type = per_2_per,
 
697
                                       .event_id = DMA_REQ_SSI2_TX2,
 
698
                                       .event_id2 = DMA_REQ_ASRC_DMA4,
 
699
                                       .bd_number = 32,
 
700
                                       .word_size = TRANSFER_32BIT,
 
701
                                       .ext = 1,
 
702
                                       },
 
703
                            .p2p_dir = 0,
 
704
                            .info_bits =
 
705
                            SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP |
 
706
                            SDMA_ASRC_P2P_INFO_DP,
 
707
                            .watermark_level2 = MXC_SSI_TXFIFO_WML,
 
708
                            .per_address2 = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG,
 
709
                            },
 
710
        .channel_num = MXC_DMA_CHANNEL_ASRCA_SSI2_TX1,
 
711
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
712
};
 
713
 
 
714
static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_ssi1_tx0_params = {
 
715
        .chnl_ext_params = {
 
716
                            .common = {
 
717
                                       .watermark_level =
 
718
                                       MXC_ASRC_FIFO_WML >> 1,
 
719
                                       .per_address =
 
720
                                       SSI1_BASE_ADDR + MXC_SSI_TX0_REG,
 
721
                                       .peripheral_type = ASRC,
 
722
                                       .transfer_type = per_2_per,
 
723
                                       .event_id = DMA_REQ_SSI1_TX1,
 
724
                                       .event_id2 = DMA_REQ_ASRC_DMA5,
 
725
                                       .bd_number = 32,
 
726
                                       .word_size = TRANSFER_32BIT,
 
727
                                       .ext = 1,
 
728
                                       },
 
729
                            .p2p_dir = 0,
 
730
                            .info_bits =
 
731
                            SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP,
 
732
                            .watermark_level2 = MXC_SSI_TXFIFO_WML,
 
733
                            .per_address2 = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG,
 
734
                            },
 
735
        .channel_num = MXC_DMA_CHANNEL_ASRCB_SSI1_TX0,
 
736
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
737
};
 
738
 
 
739
static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_ssi1_tx1_params = {
 
740
        .chnl_ext_params = {
 
741
                            .common = {
 
742
                                       .watermark_level =
 
743
                                       MXC_ASRC_FIFO_WML >> 1,
 
744
                                       .per_address =
 
745
                                       SSI1_BASE_ADDR + MXC_SSI_TX1_REG,
 
746
                                       .peripheral_type = ASRC,
 
747
                                       .transfer_type = per_2_per,
 
748
                                       .event_id = DMA_REQ_SSI1_TX2,
 
749
                                       .event_id2 = DMA_REQ_ASRC_DMA5,
 
750
                                       .bd_number = 32,
 
751
                                       .word_size = TRANSFER_32BIT,
 
752
                                       .ext = 1,
 
753
                                       },
 
754
                            .p2p_dir = 0,
 
755
                            .info_bits =
 
756
                            SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP,
 
757
                            .watermark_level2 = MXC_SSI_TXFIFO_WML,
 
758
                            .per_address2 = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG,
 
759
                            },
 
760
        .channel_num = MXC_DMA_CHANNEL_ASRCB_SSI1_TX1,
 
761
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
762
};
 
763
 
 
764
static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_ssi2_tx0_params = {
 
765
        .chnl_ext_params = {
 
766
                            .common = {
 
767
                                       .watermark_level =
 
768
                                       MXC_ASRC_FIFO_WML >> 1,
 
769
                                       .per_address =
 
770
                                       SSI2_BASE_ADDR + MXC_SSI_TX0_REG,
 
771
                                       .peripheral_type = ASRC,
 
772
                                       .transfer_type = per_2_per,
 
773
                                       .event_id = DMA_REQ_SSI2_TX1,
 
774
                                       .event_id2 = DMA_REQ_ASRC_DMA5,
 
775
                                       .bd_number = 32,
 
776
                                       .word_size = TRANSFER_32BIT,
 
777
                                       .ext = 1,
 
778
                                       },
 
779
                            .p2p_dir = 0,
 
780
                            .info_bits =
 
781
                            SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP |
 
782
                            SDMA_ASRC_P2P_INFO_DP,
 
783
                            .watermark_level2 = MXC_SSI_TXFIFO_WML,
 
784
                            .per_address2 = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG,
 
785
                            },
 
786
        .channel_num = MXC_DMA_CHANNEL_ASRCB_SSI2_TX0,
 
787
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
788
};
 
789
 
 
790
static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_ssi2_tx1_params = {
 
791
        .chnl_ext_params = {
 
792
                            .common = {
 
793
                                       .watermark_level =
 
794
                                       MXC_ASRC_FIFO_WML >> 1,
 
795
                                       .per_address =
 
796
                                       SSI2_BASE_ADDR + MXC_SSI_TX1_REG,
 
797
                                       .peripheral_type = ASRC,
 
798
                                       .transfer_type = per_2_per,
 
799
                                       .event_id = DMA_REQ_SSI2_TX2,
 
800
                                       .event_id2 = DMA_REQ_ASRC_DMA5,
 
801
                                       .bd_number = 32,
 
802
                                       .word_size = TRANSFER_32BIT,
 
803
                                       .ext = 1,
 
804
                                       },
 
805
                            .p2p_dir = 0,
 
806
                            .info_bits =
 
807
                            SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP |
 
808
                            SDMA_ASRC_P2P_INFO_DP,
 
809
                            .watermark_level2 = MXC_SSI_TXFIFO_WML,
 
810
                            .per_address2 = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG,
 
811
                            },
 
812
        .channel_num = MXC_DMA_CHANNEL_ASRCB_SSI2_TX1,
 
813
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
814
};
 
815
 
 
816
static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_esai_params = {
 
817
        .chnl_ext_params = {
 
818
                            .common = {
 
819
                                       .watermark_level =
 
820
                                       MXC_ASRC_FIFO_WML >> 1,
 
821
                                       .per_address =
 
822
                                       ESAI_BASE_ADDR + MXC_ESAI_TX_REG,
 
823
                                       .peripheral_type = ASRC,
 
824
                                       .transfer_type = per_2_per,
 
825
                                       .event_id = DMA_REQ_ESAI_TX,
 
826
                                       .event_id2 = DMA_REQ_ASRC_DMA4,
 
827
                                       .bd_number = 32,
 
828
                                       .word_size = TRANSFER_32BIT,
 
829
                                       .ext = 1,
 
830
                                       },
 
831
                            .p2p_dir = 0,
 
832
                            .info_bits =
 
833
                            SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP |
 
834
                            SDMA_ASRC_P2P_INFO_DP,
 
835
                            .watermark_level2 = MXC_ESAI_FIFO_WML,
 
836
                            .per_address2 = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG,
 
837
                            },
 
838
        .channel_num = MXC_DMA_CHANNEL_ASRCA_ESAI,
 
839
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
840
};
 
841
 
 
842
static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_esai_params = {
 
843
        .chnl_ext_params = {
 
844
                            .common = {
 
845
                                       .watermark_level =
 
846
                                       MXC_ASRC_FIFO_WML >> 1,
 
847
                                       .per_address =
 
848
                                       ESAI_BASE_ADDR + MXC_ESAI_TX_REG,
 
849
                                       .peripheral_type = ASRC,
 
850
                                       .transfer_type = per_2_per,
 
851
                                       .event_id = DMA_REQ_ESAI_TX,
 
852
                                       .event_id2 = DMA_REQ_ASRC_DMA5,
 
853
                                       .bd_number = 32,
 
854
                                       .word_size = TRANSFER_32BIT,
 
855
                                       .ext = 1,
 
856
                                       },
 
857
                            .p2p_dir = 0,
 
858
                            .info_bits =
 
859
                            SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP |
 
860
                            SDMA_ASRC_P2P_INFO_DP,
 
861
                            .watermark_level2 = MXC_ESAI_FIFO_WML,
 
862
                            .per_address2 = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG,
 
863
                            },
 
864
        .channel_num = MXC_DMA_CHANNEL_ASRCB_ESAI,
 
865
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
866
};
 
867
 
 
868
static mxc_sdma_channel_ext_params_t mxc_sdma_asrcc_esai_params = {
 
869
        .chnl_ext_params = {
 
870
                            .common = {
 
871
                                       .watermark_level =
 
872
                                       MXC_ASRC_FIFO_WML >> 1,
 
873
                                       .per_address =
 
874
                                       ESAI_BASE_ADDR + MXC_ESAI_TX_REG,
 
875
                                       .peripheral_type = ASRC,
 
876
                                       .transfer_type = per_2_per,
 
877
                                       .event_id = DMA_REQ_ESAI_TX,
 
878
                                       .event_id2 = DMA_REQ_ASRC_DMA6,
 
879
                                       .bd_number = 32,
 
880
                                       .word_size = TRANSFER_32BIT,
 
881
                                       .ext = 1,
 
882
                                       },
 
883
                            .p2p_dir = 0,
 
884
                            .info_bits =
 
885
                            SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP |
 
886
                            SDMA_ASRC_P2P_INFO_DP,
 
887
                            .watermark_level2 = MXC_ASRC_FIFO_WML,
 
888
                            .per_address2 = ASRC_BASE_ADDR + MXC_ASRCC_TX_REG,
 
889
                            },
 
890
        .channel_num = MXC_DMA_CHANNEL_ASRCC_ESAI,
 
891
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
892
};
 
893
 
 
894
static mxc_sdma_channel_params_t mxc_sdma_esai_16bit_rx_params = {
 
895
        .chnl_params = {
 
896
                        .watermark_level = MXC_ESAI_FIFO_WML,
 
897
                        .per_address = ESAI_BASE_ADDR + MXC_ESAI_RX_REG,
 
898
                        .peripheral_type = ESAI,
 
899
                        .transfer_type = per_2_emi,
 
900
                        .event_id = DMA_REQ_ESAI_RX,
 
901
                        .bd_number = 32,
 
902
                        .word_size = TRANSFER_16BIT,
 
903
                        },
 
904
        .channel_num = MXC_DMA_CHANNEL_ESAI_RX,
 
905
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
906
};
 
907
 
 
908
static mxc_sdma_channel_params_t mxc_sdma_esai_16bit_tx_params = {
 
909
        .chnl_params = {
 
910
                        .watermark_level = MXC_ESAI_FIFO_WML,
 
911
                        .per_address = ESAI_BASE_ADDR + MXC_ESAI_TX_REG,
 
912
                        .peripheral_type = ESAI,
 
913
                        .transfer_type = soc_trans_type,
 
914
                        .event_id = DMA_REQ_ESAI_TX,
 
915
                        .bd_number = 32,
 
916
                        .word_size = TRANSFER_16BIT,
 
917
                        },
 
918
        .channel_num = MXC_DMA_CHANNEL_ESAI_TX,
 
919
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
920
};
 
921
 
 
922
static mxc_sdma_channel_params_t mxc_sdma_esai_24bit_rx_params = {
 
923
        .chnl_params = {
 
924
                        .watermark_level = MXC_ESAI_FIFO_WML,
 
925
                        .per_address = ESAI_BASE_ADDR + MXC_ESAI_RX_REG,
 
926
                        .peripheral_type = ESAI,
 
927
                        .transfer_type = per_2_emi,
 
928
                        .event_id = DMA_REQ_ESAI_RX,
 
929
                        .bd_number = 32,
 
930
                        .word_size = TRANSFER_32BIT,
 
931
                        },
 
932
        .channel_num = MXC_DMA_CHANNEL_ESAI_RX,
 
933
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
934
};
 
935
 
 
936
static mxc_sdma_channel_params_t mxc_sdma_esai_24bit_tx_params = {
 
937
        .chnl_params = {
 
938
                        .watermark_level = MXC_ESAI_FIFO_WML,
 
939
                        .per_address = ESAI_BASE_ADDR + MXC_ESAI_TX_REG,
 
940
                        .peripheral_type = ESAI,
 
941
                        .transfer_type = soc_trans_type,
 
942
                        .event_id = DMA_REQ_ESAI_TX,
 
943
                        .bd_number = 32,
 
944
                        .word_size = TRANSFER_32BIT,
 
945
                        },
 
946
        .channel_num = MXC_DMA_CHANNEL_ESAI_TX,
 
947
        .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
 
948
};
 
949
 
 
950
static struct mxc_sdma_info_entry_s mxc_sdma_active_dma_info[] = {
 
951
        {MXC_DMA_UART1_RX, &mxc_sdma_uart1_rx_params},
 
952
        {MXC_DMA_UART1_TX, &mxc_sdma_uart1_tx_params},
 
953
        {MXC_DMA_UART2_RX, &mxc_sdma_uart2_rx_params},
 
954
        {MXC_DMA_UART2_TX, &mxc_sdma_uart2_tx_params},
 
955
        {MXC_DMA_UART3_RX, &mxc_sdma_uart3_rx_params},
 
956
        {MXC_DMA_UART3_TX, &mxc_sdma_uart3_tx_params},
 
957
        {MXC_DMA_SPDIF_16BIT_TX, &mxc_sdma_spdif_16bit_tx_params},
 
958
        {MXC_DMA_SPDIF_32BIT_TX, &mxc_sdma_spdif_32bit_tx_params},
 
959
        {MXC_DMA_SPDIF_32BIT_RX, &mxc_sdma_spdif_32bit_rx_params},
 
960
        {MXC_DMA_SSI1_8BIT_RX0, &mxc_sdma_ssi1_8bit_rx0_params},
 
961
        {MXC_DMA_SSI1_8BIT_TX0, &mxc_sdma_ssi1_8bit_tx0_params},
 
962
        {MXC_DMA_SSI1_16BIT_RX0, &mxc_sdma_ssi1_16bit_rx0_params},
 
963
        {MXC_DMA_SSI1_16BIT_TX0, &mxc_sdma_ssi1_16bit_tx0_params},
 
964
        {MXC_DMA_SSI1_24BIT_RX0, &mxc_sdma_ssi1_24bit_rx0_params},
 
965
        {MXC_DMA_SSI1_24BIT_TX0, &mxc_sdma_ssi1_24bit_tx0_params},
 
966
        {MXC_DMA_SSI1_8BIT_RX1, &mxc_sdma_ssi1_8bit_rx1_params},
 
967
        {MXC_DMA_SSI1_8BIT_TX1, &mxc_sdma_ssi1_8bit_tx1_params},
 
968
        {MXC_DMA_SSI1_16BIT_RX1, &mxc_sdma_ssi1_16bit_rx1_params},
 
969
        {MXC_DMA_SSI1_16BIT_TX1, &mxc_sdma_ssi1_16bit_tx1_params},
 
970
        {MXC_DMA_SSI1_24BIT_RX1, &mxc_sdma_ssi1_24bit_rx1_params},
 
971
        {MXC_DMA_SSI1_24BIT_TX1, &mxc_sdma_ssi1_24bit_tx1_params},
 
972
        {MXC_DMA_SSI2_8BIT_RX0, &mxc_sdma_ssi2_8bit_rx0_params},
 
973
        {MXC_DMA_SSI2_8BIT_TX0, &mxc_sdma_ssi2_8bit_tx0_params},
 
974
        {MXC_DMA_SSI2_16BIT_RX0, &mxc_sdma_ssi2_16bit_rx0_params},
 
975
        {MXC_DMA_SSI2_16BIT_TX0, &mxc_sdma_ssi2_16bit_tx0_params},
 
976
        {MXC_DMA_SSI2_24BIT_RX0, &mxc_sdma_ssi2_24bit_rx0_params},
 
977
        {MXC_DMA_SSI2_24BIT_TX0, &mxc_sdma_ssi2_24bit_tx0_params},
 
978
        {MXC_DMA_SSI2_8BIT_RX1, &mxc_sdma_ssi2_8bit_rx1_params},
 
979
        {MXC_DMA_SSI2_8BIT_TX1, &mxc_sdma_ssi2_8bit_tx1_params},
 
980
        {MXC_DMA_SSI2_16BIT_RX1, &mxc_sdma_ssi2_16bit_rx1_params},
 
981
        {MXC_DMA_SSI2_16BIT_TX1, &mxc_sdma_ssi2_16bit_tx1_params},
 
982
        {MXC_DMA_SSI2_24BIT_RX1, &mxc_sdma_ssi2_24bit_rx1_params},
 
983
        {MXC_DMA_SSI2_24BIT_TX1, &mxc_sdma_ssi2_24bit_tx1_params},
 
984
        {MXC_DMA_ASRC_A_RX, &mxc_sdma_asrca_rx_params},
 
985
        {MXC_DMA_ASRC_A_TX, &mxc_sdma_asrca_tx_params},
 
986
        {MXC_DMA_ASRC_B_RX, &mxc_sdma_asrcb_rx_params},
 
987
        {MXC_DMA_ASRC_B_TX, &mxc_sdma_asrcb_tx_params},
 
988
        {MXC_DMA_ASRC_C_RX, &mxc_sdma_asrcc_rx_params},
 
989
        {MXC_DMA_ASRC_C_TX, &mxc_sdma_asrcc_tx_params},
 
990
        {MXC_DMA_ASRCA_SSI1_TX0, &mxc_sdma_asrca_ssi1_tx0_params},
 
991
        {MXC_DMA_ASRCA_SSI1_TX1, &mxc_sdma_asrca_ssi1_tx1_params},
 
992
        {MXC_DMA_ASRCA_SSI2_TX0, &mxc_sdma_asrca_ssi2_tx0_params},
 
993
        {MXC_DMA_ASRCA_SSI2_TX1, &mxc_sdma_asrca_ssi2_tx1_params},
 
994
        {MXC_DMA_ASRCB_SSI1_TX0, &mxc_sdma_asrcb_ssi1_tx0_params},
 
995
        {MXC_DMA_ASRCB_SSI1_TX1, &mxc_sdma_asrcb_ssi1_tx1_params},
 
996
        {MXC_DMA_ASRCB_SSI2_TX0, &mxc_sdma_asrcb_ssi2_tx0_params},
 
997
        {MXC_DMA_ASRCB_SSI2_TX1, &mxc_sdma_asrcb_ssi2_tx1_params},
 
998
        {MXC_DMA_ASRCA_ESAI, &mxc_sdma_asrca_esai_params},
 
999
        {MXC_DMA_ASRCB_ESAI, &mxc_sdma_asrcb_esai_params},
 
1000
        {MXC_DMA_ASRCC_ESAI, &mxc_sdma_asrcc_esai_params},
 
1001
        {MXC_DMA_ESAI_16BIT_RX, &mxc_sdma_esai_16bit_rx_params},
 
1002
        {MXC_DMA_ESAI_16BIT_TX, &mxc_sdma_esai_16bit_tx_params},
 
1003
        {MXC_DMA_ESAI_24BIT_RX, &mxc_sdma_esai_24bit_rx_params},
 
1004
        {MXC_DMA_ESAI_24BIT_TX, &mxc_sdma_esai_24bit_tx_params},
 
1005
        {MXC_DMA_MEMORY, &mxc_sdma_memory_params},
 
1006
};
 
1007
 
 
1008
static int mxc_sdma_info_entrys =
 
1009
    sizeof(mxc_sdma_active_dma_info) / sizeof(mxc_sdma_active_dma_info[0]);
 
1010
/*!
 
1011
 * This functions Returns the SDMA paramaters associated for a module
 
1012
 *
 
1013
 * @param channel_id the ID of the module requesting DMA
 
1014
 * @return returns the sdma parameters structure for the device
 
1015
 */
 
1016
mxc_sdma_channel_params_t *mxc_sdma_get_channel_params(mxc_dma_device_t
 
1017
                                                       channel_id)
 
1018
{
 
1019
        struct mxc_sdma_info_entry_s *p = mxc_sdma_active_dma_info;
 
1020
        int i;
 
1021
 
 
1022
        for (i = 0; i < mxc_sdma_info_entrys; i++, p++) {
 
1023
                if (p->device == channel_id)
 
1024
                        return p->chnl_info;
 
1025
        }
 
1026
        return NULL;
 
1027
}
 
1028
 
 
1029
EXPORT_SYMBOL(mxc_sdma_get_channel_params);
 
1030
 
 
1031
/*!
 
1032
 * This functions marks the SDMA channels that are statically allocated
 
1033
 *
 
1034
 * @param chnl the channel array used to store channel information
 
1035
 */
 
1036
void mxc_get_static_channels(mxc_dma_channel_t *chnl)
 
1037
{
 
1038
        /* No channels statically allocated for MX35 */
 
1039
#ifdef CONFIG_SDMA_IRAM
 
1040
        int i;
 
1041
        for (i = MXC_DMA_CHANNEL_IRAM; i < MAX_DMA_CHANNELS; i++)
 
1042
                chnl[i].dynamic = 0;
 
1043
#endif
 
1044
}
 
1045
 
 
1046
EXPORT_SYMBOL(mxc_get_static_channels);