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* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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#include <mach/hardware.h>
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#include <asm/proc-fns.h>
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#include <asm/system.h>
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#include <asm/cacheflush.h>
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#include <mach/clock.h>
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* @defgroup MSL_MX37 i.MX37 Machine Specific Layer (MSL)
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* @file mach-mx37/system.c
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* @brief This file contains idle and reset functions.
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extern int mxc_jtag_enabled;
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extern int low_bus_freq_mode;
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static struct clk *gpc_dvfs_clk;
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/* set cpu low power mode before WFI instruction */
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void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
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u32 plat_lpc, gpc_pgr, arm_srpgcr, empgcr0, empgcr1, ccm_clpcr;
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/* always allow platform to issue a deep sleep mode request */
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plat_lpc = __raw_readl(MXC_ARM1176_PLAT_LPC) &
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~(MXC_ARM1176_PLAT_LPC_DSM);
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ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK);
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gpc_pgr = __raw_readl(MXC_GPC_PGR) & ~(MXC_GPC_PGR_ARMPG_MASK);
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arm_srpgcr = __raw_readl(MXC_SRPGC_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR);
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empgcr0 = __raw_readl(MXC_EMPGC0_ARM_EMPGCR) & ~(MXC_EMPGCR_PCR);
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empgcr1 = __raw_readl(MXC_EMPGC1_ARM_EMPGCR) & ~(MXC_EMPGCR_PCR);
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ccm_clpcr |= (0x1 << MXC_CCM_CLPCR_LPM_OFFSET);
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case WAIT_UNCLOCKED_POWER_OFF:
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plat_lpc |= MXC_ARM1176_PLAT_LPC_DSM;
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if (mode == WAIT_UNCLOCKED_POWER_OFF)
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ccm_clpcr |= (0x1 << MXC_CCM_CLPCR_LPM_OFFSET);
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ccm_clpcr |= (0x2 << MXC_CCM_CLPCR_LPM_OFFSET);
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ccm_clpcr |= (0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET);
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ccm_clpcr |= MXC_CCM_CLPCR_VSTBY;
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ccm_clpcr |= MXC_CCM_CLPCR_SBYOS;
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gpc_pgr |= (0x1 << MXC_GPC_PGR_ARMPG_OFFSET);
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arm_srpgcr |= MXC_SRPGCR_PCR;
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empgcr0 |= MXC_EMPGCR_PCR;
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empgcr1 |= MXC_EMPGCR_PCR;
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if (tzic_enable_wake(1) != 0)
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ccm_clpcr |= (0x2 << MXC_CCM_CLPCR_LPM_OFFSET);
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printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode);
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__raw_writel(plat_lpc, MXC_ARM1176_PLAT_LPC);
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__raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
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__raw_writel(gpc_pgr, MXC_GPC_PGR);
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__raw_writel(arm_srpgcr, MXC_SRPGC_ARM_SRPGCR);
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if ((mxc_cpu_is_rev(CHIP_REV_1_0)) != 1)
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__raw_writel(empgcr0, MXC_EMPGC0_ARM_EMPGCR);
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if (gpc_dvfs_clk == NULL)
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gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs_clk");
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/* gpc clock is needed for SRPG */
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clk_enable(gpc_dvfs_clk);
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void mxc_pg_enable(struct platform_device *pdev)
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if (strcmp(pdev->name, "mxc_ipu") == 0) {
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__raw_writel(MXC_PGCR_PCR, MXC_PGC_IPU_PGCR);
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__raw_writel(MXC_PGSR_PSR, MXC_PGC_IPU_PGSR);
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} else if (strcmp(pdev->name, "mxc_vpu") == 0) {
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__raw_writel(MXC_PGCR_PCR, MXC_PGC_VPU_PGCR);
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__raw_writel(MXC_PGSR_PSR, MXC_PGC_VPU_PGSR);
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EXPORT_SYMBOL(mxc_pg_enable);
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void mxc_pg_disable(struct platform_device *pdev)
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if (strcmp(pdev->name, "mxc_ipu") == 0) {
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__raw_writel(0x0, MXC_PGC_IPU_PGCR);
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if (__raw_readl(MXC_PGC_IPU_PGSR) & MXC_PGSR_PSR)
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dev_dbg(&pdev->dev, "power gating successful\n");
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__raw_writel(MXC_PGSR_PSR, MXC_PGC_IPU_PGSR);
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} else if (strcmp(pdev->name, "mxc_vpu") == 0) {
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__raw_writel(0x0, MXC_PGC_VPU_PGCR);
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if (__raw_readl(MXC_PGC_VPU_PGSR) & MXC_PGSR_PSR)
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dev_dbg(&pdev->dev, "power gating successful\n");
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__raw_writel(MXC_PGSR_PSR, MXC_PGC_VPU_PGSR);
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EXPORT_SYMBOL(mxc_pg_disable);
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/* To change the idle power mode, need to set arch_idle_mode to a different
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* power mode as in enum mxc_cpu_pwr_mode.
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* May allow dynamically changing the idle mode.
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static int arch_idle_mode = WAIT_UNCLOCKED_POWER_OFF;
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* This function puts the CPU into idle mode. It is called by default_idle()
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if (likely(!mxc_jtag_enabled)) {
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mxc_cpu_lp_set(arch_idle_mode);
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/* gpc clock is needed for SRPG */
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clk_disable(gpc_dvfs_clk);
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* This function resets the system. It is called by machine_restart().
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* @param mode indicates different kinds of resets
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void arch_reset(char mode)
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/* Assert SRS signal */