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// Scintilla source code edit control
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/** @file LexVHDL.cxx
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** Written by Phil Reid,
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** Written by Phil Reid,
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** - The Verilog Lexer by Avi Yegudin
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** - The Verilog Lexer by Avi Yegudin
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** - The Fortran Lexer by Chuan-jian Shen
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** - The C++ lexer by Neil Hodgson
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sc.SetState(SCE_VHDL_IDENTIFIER);
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} else if (sc.Match('-', '-')) {
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sc.SetState(SCE_VHDL_COMMENT);
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} else if (sc.Match('-', '-')) {
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if (sc.Match("--!")) // Nice to have a different comment style
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sc.SetState(SCE_VHDL_COMMENTLINEBANG);
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char chPrev = '\0';
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char chNextNonBlank;
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int styleNext = styler.StyleAt(startPos);
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int style = initStyle;
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//Platform::DebugPrintf("Line[%04d] Prev[%20s] ************************* Level[%x]\n", lineCurrent+1, prevWord, levelCurrent);
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/***************************************/
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chNextNonBlank = styler.SafeGetCharAt(j);
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int style = styleNext;
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styleNext = styler.StyleAt(i + 1);
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bool atEOL = (ch == '\r' && chNext != '\n') || (ch == '\n');
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if (foldComment && atEOL && IsCommentLine(lineCurrent, styler))
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if (foldComment && atEOL && IsCommentLine(lineCurrent, styler))
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if(!IsCommentLine(lineCurrent-1, styler) && IsCommentLine(lineCurrent+1, styler))
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else if(IsCommentLine(lineCurrent-1, styler) && !IsCommentLine(lineCurrent+1, styler))
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((strcmp(s, "begin") == 0) && (strcmp(prevWord, "function") == 0)) ||
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((strcmp(s, "begin") == 0) && (strcmp(prevWord, "procedure") == 0)))
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levelMinCurrentBegin = levelNext - 1;
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levelMinCurrentBegin = levelNext - 1;
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//Platform::DebugPrintf("Line[%04d] Prev[%20s] Cur[%20s] Level[%x]\n", lineCurrent+1, prevWord, s, levelCurrent);
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strcpy(prevWord, s);
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// access after alias all architecture array assert attribute begin block body buffer bus case component
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// configuration constant disconnect downto else elsif end entity exit file for function generate generic
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// group guarded if impure in inertial inout is label library linkage literal loop map new next null of
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// on open others out package port postponed procedure process pure range record register reject report
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// return select severity shared signal subtype then to transport type unaffected units until use variable
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// access after alias all architecture array assert attribute begin block body buffer bus case component
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// configuration constant disconnect downto else elsif end entity exit file for function generate generic
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// group guarded if impure in inertial inout is label library linkage literal loop map new next null of
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// on open others out package port postponed procedure process pure range record register reject report
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// return select severity shared signal subtype then to transport type unaffected units until use variable
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// wait when while with
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// abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor
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// left right low high ascending image value pos val succ pred leftof rightof base range reverse_range
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// length delayed stable quiet transaction event active last_event last_active last_value driving
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// left right low high ascending image value pos val succ pred leftof rightof base range reverse_range
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// length delayed stable quiet transaction event active last_event last_active last_value driving
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// driving_value simple_name path_name instance_name
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// Std Functions:
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// now readline read writeline write endfile resolved to_bit to_bitvector to_stdulogic to_stdlogicvector
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// to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x shift_left shift_right rotate_left
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// now readline read writeline write endfile resolved to_bit to_bitvector to_stdulogic to_stdlogicvector
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// to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x shift_left shift_right rotate_left
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// rotate_right resize to_integer to_unsigned to_signed std_match to_01
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// std ieee work standard textio std_logic_1164 std_logic_arith std_logic_misc std_logic_signed
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// std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex math_real vital_primitives
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// std ieee work standard textio std_logic_1164 std_logic_arith std_logic_misc std_logic_signed
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// std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex math_real vital_primitives
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// boolean bit character severity_level integer real time delay_length natural positive string bit_vector
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// file_open_kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic
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// boolean bit character severity_level integer real time delay_length natural positive string bit_vector
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// file_open_kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic
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// std_logic_vector X01 X01Z UX01 UX01Z unsigned signed
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scintilla/LexVHDL.cxx
